Two changes, both very significant:

* vreg <-> vreg joining now works, enable it unconditionally when joining
  is enabled (which is the default).
* Fix a serious pessimization of spill code where we were saying that a
  spilled DEF operand was live into the subsequent instruction.  This allows
  for substantially better code when spilling starts to happen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14993 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 9687e589812678fe0372117c7555fb4e5387810d..ee988b10a40228af7af08c62cecb8864d25d0ac0 100644 (file)
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -60,11 +60,6 @@ namespace {
     EnableJoining("join-liveintervals",
                   cl::desc("Join compatible live intervals"),
                   cl::init(true));
-
-    cl::opt<bool>
-    EnableVirtVirtJoining("join-liveintervals-virtvirtjoining",
-                      cl::desc("Join live intervals for virtreg pairs (buggy)"),
-                          cl::init(false));
 };
 
 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
@@ -251,7 +246,7 @@ std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills(
                         // use of the next instruction. Otherwise we end
                         // after the use of this instruction.
                         unsigned end = 1 + (mop.isDef() ?
-                                            getUseIndex(index+InstrSlots::NUM) :
+                                            getStoreIndex(index) :
                                             getUseIndex(index));
 
                         // create a new register for this spill
@@ -545,11 +540,7 @@ void LiveIntervals::joinIntervals()
                 Intervals::iterator intB = r2iB->second;
 
                 // both A and B are virtual registers
-
-                // FIXME: coallescing two virtual registers together is
-                // apparently broken.
-                if (EnableVirtVirtJoining && 
-                    MRegisterInfo::isVirtualRegister(intA->reg) &&
+                if (MRegisterInfo::isVirtualRegister(intA->reg) &&
                     MRegisterInfo::isVirtualRegister(intB->reg)) {
 
                     const TargetRegisterClass *rcA, *rcB;