The dag isel generator generates this now

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23984 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 236622ea1f74b83ebb448795b32d758ac4106f6b..ac87a4ef3f00a404235648cfac57917b68dc9251 100644 (file)
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -183,38 +183,6 @@ SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
     return SDOperand(N, 0);
   }
 
-  case ISD::TokenFactor: {
-    SDOperand New;
-    if (N->getNumOperands() == 2) {
-      SDOperand Op0 = Select(N->getOperand(0));
-      SDOperand Op1 = Select(N->getOperand(1));
-      New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
-    } else {
-      std::vector<SDOperand> Ops;
-      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-        Ops.push_back(Select(N->getOperand(i)));
-      New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
-    }
-    
-    CodeGenMap[Op] = New;
-    return New;
-  }
-  case ISD::CopyFromReg: {
-    SDOperand Chain = Select(N->getOperand(0));
-    if (Chain == N->getOperand(0)) return Op; // No change
-    SDOperand New = CurDAG->getCopyFromReg(Chain,
-         cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
-    return New.getValue(Op.ResNo);
-  }
-  case ISD::CopyToReg: {
-    SDOperand Chain = Select(N->getOperand(0));
-    SDOperand Reg = N->getOperand(1);
-    SDOperand Val = Select(N->getOperand(2));
-    SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
-                                    Chain, Reg, Val);
-    CodeGenMap[Op] = New;
-    return New;
-  }
   case ISD::UNDEF:
     if (N->getValueType(0) == MVT::i64)
       CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 16622693ded4bff97eb95b506ca79aae90b7ce49..d299b79104b6da29bafa1aba29e8ac2bf9274ee3 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -844,38 +844,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
   case ISD::CALL:               return SelectCALL(Op);
   case ISD::TAILCALL:           return SelectCALL(Op);
 
-  case ISD::TokenFactor: {
-    SDOperand New;
-    if (N->getNumOperands() == 2) {
-      SDOperand Op0 = Select(N->getOperand(0));
-      SDOperand Op1 = Select(N->getOperand(1));
-      New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
-    } else {
-      std::vector<SDOperand> Ops;
-      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
-        Ops.push_back(Select(N->getOperand(i)));
-      New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
-    }
-    
-    CodeGenMap[Op] = New;
-    return New;
-  }
-  case ISD::CopyFromReg: {
-    SDOperand Chain = Select(N->getOperand(0));
-    if (Chain == N->getOperand(0)) return Op; // No change
-    SDOperand New = CurDAG->getCopyFromReg(Chain,
-         cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
-    return New.getValue(Op.ResNo);
-  }
-  case ISD::CopyToReg: {
-    SDOperand Chain = Select(N->getOperand(0));
-    SDOperand Reg = N->getOperand(1);
-    SDOperand Val = Select(N->getOperand(2));
-    SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
-                                    Chain, Reg, Val);
-    CodeGenMap[Op] = New;
-    return New;
-  }
   case ISD::UNDEF:
     if (N->getValueType(0) == MVT::i32)
       CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);