video: rockchip: hdmi: set hdcp hclk to modify standby crash
authorxuhuicong <xhc@rock-chips.com>
Wed, 15 Jun 2016 06:09:42 +0000 (14:09 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Thu, 16 Jun 2016 01:48:12 +0000 (09:48 +0800)
Change-Id: I032f85abe08932a2b14dcc71e732bd334825fed2
Signed-off-by: xuhuicong <xhc@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2.c
drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2.h

index 59c0907b10f9513e65bdda9489bebaa541272402..71b29ba60a753af900b6f196b1e0a9775fa8b94e 100644 (file)
                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru PCLK_HDMI_CTRL>,
-                        <&cru SCLK_HDMI_SFR>,
+                        <&cru HCLK_HDCP>,
                         <&cru SCLK_HDMI_CEC>,
-                        <&cru PLL_VPLL>;
+                        <&cru PLL_VPLL>,
+                        <&cru SCLK_HDMI_SFR>;
                clock-names = "pclk_hdmi",
                              "hdcp_clk_hdmi",
                              "cec_clk_hdmi",
-                             "dclk_hdmi_phy";
+                             "dclk_hdmi_phy",
+                             "sclk_hdmi_sfr";
                resets = <&cru SRST_HDMI_CTRL>;
                reset-names = "hdmi";
                pinctrl-names = "default", "gpio";
index c5a757b75fb213604f404443f7da5fb16f38add4..44150376b927f5c76904cfd4fd8bf67a7f1efdc3 100644 (file)
@@ -270,6 +270,21 @@ static int rockchip_hdmiv2_clk_enable(struct hdmi_dev *hdmi_dev)
                clk_prepare_enable(hdmi_dev->cec_clk);
                hdmi_dev->clk_on |= HDMI_CECCLK_ON;
        }
+
+       if ((hdmi_dev->clk_on & HDMI_SFRCLK_ON) == 0) {
+               if (!hdmi_dev->sfr_clk) {
+                       hdmi_dev->sfr_clk =
+                               devm_clk_get(hdmi_dev->dev, "sclk_hdmi_sfr");
+                       if (IS_ERR(hdmi_dev->sfr_clk)) {
+                               dev_err(hdmi_dev->dev,
+                                       "Unable to get hdmi sfr_clk\n");
+                               return -1;
+                       }
+               }
+               clk_prepare_enable(hdmi_dev->sfr_clk);
+               hdmi_dev->clk_on |= HDMI_SFRCLK_ON;
+       }
+
        return 0;
 }
 
@@ -300,6 +315,14 @@ static int rockchip_hdmiv2_clk_disable(struct hdmi_dev *hdmi_dev)
                clk_disable_unprepare(hdmi_dev->pclk_phy);
                hdmi_dev->clk_on &= ~HDMI_EXT_PHY_CLK_ON;
        }
+
+       if ((hdmi_dev->clk_on & HDMI_SFRCLK_ON) &&
+           (hdmi_dev->sfr_clk)) {
+               clk_disable_unprepare(hdmi_dev->sfr_clk);
+               hdmi_dev->clk_on &= ~HDMI_SFRCLK_ON;
+       }
+
+
        return 0;
 }
 
@@ -540,7 +563,7 @@ static int rockchip_hdmiv2_probe(struct platform_device *pdev)
                goto failed;
        }
        pm_runtime_enable(hdmi_dev->dev);
-       /*enable pd and pclk and hdcp_clk*/
+       /*enable pd and clk*/
        if (rockchip_hdmiv2_clk_enable(hdmi_dev) < 0) {
                dev_err(&pdev->dev, "failed to enable hdmi clk\n");
                ret = -ENXIO;
index 8f97c4c6f13fb645de76aedba2fe60b5d0b132ca..885527755de891c437ca0c865453b2598b5ac069 100644 (file)
@@ -20,6 +20,7 @@
 #define HDMI_HDCPCLK_ON                BIT(2)
 #define HDMI_CECCLK_ON         BIT(3)
 #define HDMI_EXT_PHY_CLK_ON    BIT(4)
+#define HDMI_SFRCLK_ON         BIT(5)
 
 struct hdmi_dev_phy_para {
        u32 maxfreq;
@@ -43,6 +44,7 @@ struct hdmi_dev {
        struct clk              *hdcp_clk;
        struct clk              *cec_clk;
        struct clk              *pclk_phy;
+       struct clk              *sfr_clk;
        struct hdmi             *hdmi;
        struct device           *dev;
        struct dentry           *debugfs_dir;