interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>,
- <&cru SCLK_HDMI_SFR>,
+ <&cru HCLK_HDCP>,
<&cru SCLK_HDMI_CEC>,
- <&cru PLL_VPLL>;
+ <&cru PLL_VPLL>,
+ <&cru SCLK_HDMI_SFR>;
clock-names = "pclk_hdmi",
"hdcp_clk_hdmi",
"cec_clk_hdmi",
- "dclk_hdmi_phy";
+ "dclk_hdmi_phy",
+ "sclk_hdmi_sfr";
resets = <&cru SRST_HDMI_CTRL>;
reset-names = "hdmi";
pinctrl-names = "default", "gpio";
clk_prepare_enable(hdmi_dev->cec_clk);
hdmi_dev->clk_on |= HDMI_CECCLK_ON;
}
+
+ if ((hdmi_dev->clk_on & HDMI_SFRCLK_ON) == 0) {
+ if (!hdmi_dev->sfr_clk) {
+ hdmi_dev->sfr_clk =
+ devm_clk_get(hdmi_dev->dev, "sclk_hdmi_sfr");
+ if (IS_ERR(hdmi_dev->sfr_clk)) {
+ dev_err(hdmi_dev->dev,
+ "Unable to get hdmi sfr_clk\n");
+ return -1;
+ }
+ }
+ clk_prepare_enable(hdmi_dev->sfr_clk);
+ hdmi_dev->clk_on |= HDMI_SFRCLK_ON;
+ }
+
return 0;
}
clk_disable_unprepare(hdmi_dev->pclk_phy);
hdmi_dev->clk_on &= ~HDMI_EXT_PHY_CLK_ON;
}
+
+ if ((hdmi_dev->clk_on & HDMI_SFRCLK_ON) &&
+ (hdmi_dev->sfr_clk)) {
+ clk_disable_unprepare(hdmi_dev->sfr_clk);
+ hdmi_dev->clk_on &= ~HDMI_SFRCLK_ON;
+ }
+
+
return 0;
}
goto failed;
}
pm_runtime_enable(hdmi_dev->dev);
- /*enable pd and pclk and hdcp_clk*/
+ /*enable pd and clk*/
if (rockchip_hdmiv2_clk_enable(hdmi_dev) < 0) {
dev_err(&pdev->dev, "failed to enable hdmi clk\n");
ret = -ENXIO;
#define HDMI_HDCPCLK_ON BIT(2)
#define HDMI_CECCLK_ON BIT(3)
#define HDMI_EXT_PHY_CLK_ON BIT(4)
+#define HDMI_SFRCLK_ON BIT(5)
struct hdmi_dev_phy_para {
u32 maxfreq;
struct clk *hdcp_clk;
struct clk *cec_clk;
struct clk *pclk_phy;
+ struct clk *sfr_clk;
struct hdmi *hdmi;
struct device *dev;
struct dentry *debugfs_dir;