For post-regalloc scheduling, remove the instructions from the block

before re-inserting them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59281 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index d60dd493576c530584ae748db10f5d215c7919fb..0c679734ea1fb7691755420be096b16337ef399b 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -675,6 +675,12 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU,
 
 /// EmitSchedule - Emit the machine code in scheduled order.
 MachineBasicBlock *ScheduleDAG::EmitSchedule() {
+  // For post-regalloc scheduling, we're rescheduling the instructions in the
+  // block, so start by removing them from the block.
+  if (!DAG)
+    while (!BB->empty())
+      BB->remove(BB->begin());
+
   DenseMap<SDValue, unsigned> VRBaseMap;
   DenseMap<SUnit*, unsigned> CopyVRBaseMap;
   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {