ARM: tegra: provide the correct max rates for pclk and sclk

Change-Id: Ieb1ae5356df26e0c9be631b9f58c641a350dc4eb
Signed-off-by: Dima Zavin <dima@android.com>

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index c11e4a7be7559e4869e4239a84a98217aa14cfe6..59ca5b0ec412d0c529009b0304951d24d648d401 100644 (file)
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1632,7 +1632,7 @@ static struct clk tegra_clk_sclk = {
        .inputs = mux_sclk,
        .reg    = 0x28,
        .ops    = &tegra_super_ops,
-       .max_rate = 600000000,
+       .max_rate = 240000000,
 };
 
 static struct clk tegra_clk_virtual_cpu = {
@@ -1669,7 +1669,7 @@ static struct clk tegra_clk_pclk = {
        .reg            = 0x30,
        .reg_shift      = 0,
        .ops            = &tegra_bus_ops,
-       .max_rate       = 108000000,
+       .max_rate       = 120000000,
 };
 
 static struct clk tegra_clk_blink = {