#include <linux/io.h>\r
#include <linux/hrtimer.h>\r
\r
-#if 1\r
-#define DVFS_DBG(fmt, args...) {while(0);}\r
-#else\r
+#if 0\r
#define DVFS_DBG(fmt, args...) printk(KERN_DEBUG "DVFS DBG:\t"fmt, ##args)\r
+#else\r
+#define DVFS_DBG(fmt, args...) {while(0);}\r
#endif\r
\r
#define DVFS_SET_VOLT_FAILURE 1\r
static DEFINE_MUTEX(mutex);\r
static DEFINE_MUTEX(rk_dvfs_mutex);\r
\r
-static int dump_dbg_map(char* buf);\r
+static int dump_dbg_map(char *buf);\r
\r
#define PD_ON 1\r
#define PD_OFF 0\r
\r
/* read back to judge if it is already effect */\r
mdelay(2);\r
- read_back = dvfs_regulator_get_voltage(regulator); \r
+ read_back = dvfs_regulator_get_voltage(regulator);\r
if (read_back == max_uV) {\r
DVFS_ERR("%s set ERROR but already effected, volt=%d\n", __func__, read_back);\r
ret = 0;\r
return ret;\r
}\r
\r
-struct regulator* dvfs_get_regulator(char *regulator_name)\r
+struct regulator *dvfs_get_regulator(char *regulator_name) \r
{\r
struct vd_node *vd;\r
list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
\r
int dvfs_clk_enable_limit(struct clk *clk, unsigned int min_rate, unsigned max_rate)\r
{\r
- struct clk_node* dvfs_clk;\r
+ struct clk_node *dvfs_clk;\r
u32 rate = 0;\r
dvfs_clk = clk->dvfs_info;\r
\r
dvfs_clk->freq_limit_en = 1;\r
dvfs_clk->min_rate = min_rate;\r
dvfs_clk->max_rate = max_rate;\r
- \r
+\r
rate = clk_get_rate(clk);\r
- if (rate < min_rate) \r
+ if (rate < min_rate)\r
dvfs_clk_set_rate(clk, min_rate);\r
else if (rate > max_rate)\r
dvfs_clk_set_rate(clk, max_rate);\r
\r
int dvfs_clk_disable_limit(struct clk *clk)\r
{\r
- struct clk_node* dvfs_clk;\r
+ struct clk_node *dvfs_clk;\r
dvfs_clk = clk->dvfs_info;\r
- \r
+\r
dvfs_clk->freq_limit_en = 0;\r
- \r
+\r
return 0;\r
}\r
\r
if (dvfs_clk->dvfs_table[i].frequency >= rate_khz) {\r
clk_fv->frequency = dvfs_clk->dvfs_table[i].frequency;\r
clk_fv->index = dvfs_clk->dvfs_table[i].index;\r
- // DVFS_DBG("%s,%s rate=%ukhz(vol=%d)\n",__func__,dvfs_clk->name, \r
+ // DVFS_DBG("%s,%s rate=%ukhz(vol=%d)\n",__func__,dvfs_clk->name,\r
// clk_fv->frequency, clk_fv->index);\r
return 0;\r
}\r
void dvfs_clk_register_set_rate_callback(struct clk *clk, clk_dvfs_target_callback clk_dvfs_target)\r
{\r
struct clk_node *dvfs_clk = clk_get_dvfs_info(clk);\r
- if (IS_ERR_OR_NULL(dvfs_clk)){\r
+ if (IS_ERR_OR_NULL(dvfs_clk)) {\r
DVFS_ERR("%s %s get dvfs_clk err\n", __func__, clk->name);\r
return ;\r
}\r
return 0;\r
}\r
\r
-int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table, \r
+int dvfs_set_arm_logic_volt(struct dvfs_arm_table *dvfs_cpu_logic_table,\r
struct cpufreq_frequency_table *cpu_dvfs_table,\r
struct cpufreq_frequency_table *dep_cpu2core_table)\r
{\r
\r
dvfs_clk->set_freq = dvfs_clk_get_rate_kz(clk);\r
// DVFS_DBG("%s ,%s get freq%u!\n",__func__,dvfs_clk->name,dvfs_clk->set_freq);\r
- \r
+\r
if (dvfs_clk_get_ref_volt(dvfs_clk, dvfs_clk->set_freq, &clk_fv)) {\r
if (dvfs_clk->dvfs_table[0].frequency == CPUFREQ_TABLE_END) {\r
DVFS_ERR("%s table empty\n", __func__);\r
#if 0\r
if (dvfs_clk->dvfs_nb) {\r
// must unregister when clk disable\r
- rk30_clk_notifier_register(clk, dvfs_clk->dvfs_nb);\r
+ clk_notifier_register(clk, dvfs_clk->dvfs_nb);\r
}\r
#endif\r
dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
- if(dvfs_clk->vd->cur_volt<dvfs_clk->set_volt)\r
- {\r
+ if(dvfs_clk->vd->cur_volt < dvfs_clk->set_volt) {\r
int ret;\r
mutex_lock(&rk_dvfs_mutex);\r
ret = dvfs_regulator_set_voltage_readback(dvfs_clk->vd->regulator, dvfs_clk->set_volt, dvfs_clk->set_volt);\r
.notifier_call = rk_dvfs_clk_notifier_event,\r
};\r
\r
-static struct clk_node *dvfs_get_dvfs_clk_byname(char *name)\r
+static struct clk_node *dvfs_get_dvfs_clk_byname(char *name) \r
{\r
struct vd_node *vd;\r
struct pd_node *pd;\r
int volt = 0;\r
struct regulator *regulator;\r
\r
- if (rate_old <= rate_new) \r
+ if (rate_old <= rate_new)\r
return 0;\r
list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {\r
ret = dvfs_clk_get_ref_volt_depend(depend, rate_new / 1000, &clk_fv);\r
#endif\r
\r
#ifdef CONFIG_ARCH_RK3066B\r
-#define ARM_HIGHER_LOGIC (50 * 1000)\r
-#define LOGIC_HIGHER_ARM (150 * 1000)\r
+static int g_arm_high_logic = 50 * 1000;\r
+static int g_logic_high_arm = 100 * 1000;\r
#else\r
-#define ARM_HIGHER_LOGIC (150 * 1000)\r
-#define LOGIC_HIGHER_ARM (100 * 1000)\r
+static int g_arm_high_logic = 150 * 1000;\r
+static int g_logic_high_arm = 100 * 1000;\r
#endif\r
\r
-int check_volt_correct(int volt_old, int *volt_new, int volt_dep_old, int *volt_dep_new, \r
- int clk_biger_than_dep, int dep_biger_than_clk)\r
+int correct_volt(int *volt_clk, int *volt_dep, int clk_biger_than_dep, int dep_biger_than_clk)\r
{\r
int up_boundary = 0, low_boundary = 0;\r
- DVFS_DBG("%d %d\n", clk_biger_than_dep, dep_biger_than_clk);\r
- up_boundary = volt_old + dep_biger_than_clk;\r
- low_boundary = volt_old - clk_biger_than_dep;\r
- \r
- if (volt_dep_old < low_boundary || volt_dep_old > up_boundary) {\r
- DVFS_ERR("%s current volt out of bondary volt=%d(old=%d), volt_dep=%d(dep_old=%d), up_bnd=%d(dn=%d)\n",\r
- __func__, *volt_new, volt_old, *volt_dep_new, volt_dep_old, up_boundary, low_boundary);\r
- return -1;\r
- }\r
- \r
- up_boundary = *volt_new + dep_biger_than_clk;\r
- low_boundary = *volt_new - clk_biger_than_dep;\r
- \r
- if (*volt_dep_new < low_boundary || *volt_dep_new > up_boundary) {\r
-\r
- if (*volt_dep_new < low_boundary) {\r
- *volt_dep_new = low_boundary;\r
- \r
- } else if (*volt_dep_new > up_boundary) {\r
- *volt_new = *volt_dep_new - dep_biger_than_clk;\r
+\r
+ up_boundary = *volt_clk + dep_biger_than_clk;\r
+ low_boundary = *volt_clk - clk_biger_than_dep;\r
+\r
+ if (*volt_dep < low_boundary || *volt_dep > up_boundary) {\r
+\r
+ if (*volt_dep < low_boundary) {\r
+ *volt_dep = low_boundary;\r
+\r
+ } else if (*volt_dep > up_boundary) {\r
+ *volt_clk = *volt_dep - dep_biger_than_clk;\r
}\r
- DVFS_DBG("%s target volt out of bondary volt=%d(old=%d), volt_dep=%d(dep_old=%d), up_bnd=%d(dn=%d)\n",\r
- __func__, *volt_new, volt_old, *volt_dep_new, volt_dep_old, up_boundary, low_boundary); \r
- return 0;\r
}\r
- return 0;\r
\r
+ return 0;\r
}\r
-int dvfs_scale_volt(struct vd_node *vd_clk, struct vd_node *vd_dep, \r
+\r
+int dvfs_scale_volt(struct vd_node *vd_clk, struct vd_node *vd_dep,\r
int volt_old, int volt_new, int volt_dep_old, int volt_dep_new, int clk_biger_than_dep, int dep_biger_than_clk)\r
{\r
struct regulator *regulator, *regulator_dep;\r
regulator = vd_clk->regulator;\r
regulator_dep = vd_dep->regulator;\r
\r
- if (IS_ERR_OR_NULL(regulator) || IS_ERR(regulator_dep)) { \r
+ if (IS_ERR_OR_NULL(regulator) || IS_ERR(regulator_dep)) {\r
DVFS_ERR("%s dvfs_clk->vd->regulator or depend->dep_vd->regulator == NULL\n", __func__);\r
return -1;\r
}\r
DVFS_DBG("step * step_dep < 0\n");\r
volt = volt_new;\r
volt_dep = volt_dep_new;\r
- \r
+\r
} else if (step > 0) {\r
// up voltage\r
DVFS_DBG("step > 0\n");\r
volt_dep = volt_dep < volt_dep_new ? volt_dep_new : volt_dep;\r
\r
} else {\r
- DVFS_ERR("Oops, some bugs here:Volt_new=%d(old=%d), volt_dep_new=%d(dep_old=%d)\n", \r
+ DVFS_ERR("Oops, some bugs here:Volt_new=%d(old=%d), volt_dep_new=%d(dep_old=%d)\n",\r
volt_new, volt_old, volt_dep_new, volt_dep_old);\r
goto fail;\r
}\r
\r
- DVFS_DBG("\t\tNOW:Volt=%d, volt_dep=%d\n", volt, volt_dep);\r
-\r
if (vd_clk->cur_volt != volt) {\r
+ DVFS_DBG("\t\t%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt);\r
ret = dvfs_regulator_set_voltage_readback(regulator, volt, volt);\r
udelay(get_volt_up_delay(volt, volt_pre));\r
if (ret < 0) {\r
- DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n", \r
+ DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_clk->name, ret, volt_new, volt_old);\r
goto fail;\r
}\r
vd_clk->cur_volt = volt;\r
}\r
-\r
if (vd_dep->cur_volt != volt_dep) {\r
+ DVFS_DBG("\t\t%s:%d->%d\n", vd_dep->name, vd_dep->cur_volt, volt_dep);\r
ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep, volt_dep);\r
udelay(get_volt_up_delay(volt_dep, volt_dep_pre));\r
if (ret < 0) {\r
- DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n", \r
+ DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
goto fail;\r
}\r
vd_dep->cur_volt = volt_dep;\r
}\r
\r
- } while (volt != volt_new || volt_dep!= volt_dep_new);\r
- \r
+ DVFS_DBG("\t\tNOW:Volt=%d, volt_dep=%d\n", volt, volt_dep);\r
+\r
+ } while (volt != volt_new || volt_dep != volt_dep_new);\r
+\r
vd_clk->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
vd_clk->cur_volt = volt_new;\r
- \r
+\r
return 0;\r
fail:\r
- DVFS_ERR("+++++++++++++++++FAIL AREA\n"); \r
+ DVFS_ERR("+++++++++++++++++FAIL AREA\n");\r
vd_clk->cur_volt = volt_old;\r
vd_dep->cur_volt = volt_dep_old;\r
vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
ret = dvfs_regulator_set_voltage_readback(regulator, volt_old, volt_old);\r
if (ret < 0) {\r
vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n", \r
+ DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_clk->name, ret, volt_new, volt_old);\r
}\r
- \r
+\r
ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep_old, volt_dep_old);\r
if (ret < 0) {\r
vd_dep->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n", \r
+ DVFS_ERR("%s %s set callback voltage err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
}\r
\r
ret = dvfs_regulator_set_voltage_readback(vd_clk->regulator, volt_new, volt_new);\r
if (ret < 0) {\r
vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
- DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n", \r
+ DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_clk->name, ret, volt_new, vd_clk->cur_volt);\r
return -1;\r
}\r
\r
}\r
\r
-int dvfs_scale_volt_bystep(struct vd_node *vd_clk, struct vd_node *vd_dep, int volt_new, int volt_dep_new, \r
- int clk_biger_than_dep, int dep_biger_than_clk)\r
-\r
+int dvfs_scale_volt_bystep(struct vd_node *vd_clk, struct vd_node *vd_dep, int volt_new, int volt_dep_new,\r
+ int cur_clk_biger_than_dep, int cur_dep_biger_than_clk, int new_clk_biger_than_dep, int new_dep_biger_than_clk)\r
{\r
- int ret = 0;\r
+\r
+ struct regulator *regulator, *regulator_dep;\r
+ int volt_new_corrected = 0, volt_dep_new_corrected = 0;\r
int volt_old = 0, volt_dep_old = 0;\r
+ int ret = 0;\r
\r
volt_old = vd_clk->cur_volt;\r
volt_dep_old = vd_dep->cur_volt;\r
\r
- DVFS_DBG("ENTER %s, volt=%d(old=%d) vd_dep=%d(dep_old=%d)\n", __func__, \r
- volt_new, volt_old, volt_dep_new, volt_dep_old);\r
-\r
- if (check_volt_correct(volt_old, &volt_new, volt_dep_old, &volt_dep_new, \r
- clk_biger_than_dep, dep_biger_than_clk) < 0) {\r
- DVFS_ERR("CURRENT VOLT INCORRECT, VD=%s, VD_DEP=%s\n", vd_clk->name, vd_dep->name);\r
- return -1;\r
- }\r
- DVFS_DBG("ENTER %s, volt=%d(old=%d), volt_dep=%d(dep_old=%d)\n", __func__, \r
+ DVFS_DBG("ENTER %s, volt=%d(old=%d) vd_dep=%d(dep_old=%d)\n", __func__,\r
volt_new, volt_old, volt_dep_new, volt_dep_old);\r
- ret = dvfs_scale_volt(vd_clk, vd_dep, volt_old, volt_new, volt_dep_old, volt_dep_new, \r
- clk_biger_than_dep, dep_biger_than_clk);\r
+ DVFS_DBG("ENTER %s, VOLT_DIFF: clk_cur=%d(clk_new=%d) dep_cur=%d(dep_new=%d)\n", __func__,\r
+ cur_clk_biger_than_dep, new_clk_biger_than_dep, \r
+ cur_dep_biger_than_clk, new_dep_biger_than_clk);\r
+\r
+ volt_new_corrected = volt_new;\r
+ volt_dep_new_corrected = volt_dep_new;\r
+ correct_volt(&volt_new_corrected, &volt_dep_new_corrected, cur_clk_biger_than_dep, cur_dep_biger_than_clk);\r
+ ret = dvfs_scale_volt(vd_clk, vd_dep, volt_old, volt_new_corrected, volt_dep_old, volt_dep_new_corrected,\r
+ cur_clk_biger_than_dep, cur_dep_biger_than_clk);\r
if (ret < 0) {\r
vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
DVFS_ERR("set volt error\n");\r
return -1;\r
}\r
\r
+ if (cur_clk_biger_than_dep != new_clk_biger_than_dep || cur_dep_biger_than_clk != new_dep_biger_than_clk) {\r
+ regulator = vd_clk->regulator;\r
+ regulator_dep = vd_dep->regulator;\r
+\r
+ volt_new_corrected = volt_new;\r
+ volt_dep_new_corrected = volt_dep_new;\r
+ correct_volt(&volt_new_corrected, &volt_dep_new_corrected, new_clk_biger_than_dep, new_dep_biger_than_clk);\r
+\r
+ if (vd_clk->cur_volt != volt_new_corrected) {\r
+ DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_new_corrected);\r
+ ret = dvfs_regulator_set_voltage_readback(regulator, volt_new_corrected, volt_new_corrected);\r
+ udelay(get_volt_up_delay(volt_new_corrected, vd_clk->cur_volt));\r
+ if (ret < 0) {\r
+ DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
+ __func__, vd_clk->name, ret, volt_new_corrected, vd_clk->cur_volt);\r
+ return -1;\r
+ }\r
+ vd_clk->cur_volt = volt_new_corrected;\r
+ }\r
+ if (vd_dep->cur_volt != volt_dep_new_corrected) {\r
+ DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_dep_new_corrected);\r
+ ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep_new_corrected, volt_dep_new_corrected);\r
+ udelay(get_volt_up_delay(volt_dep_new_corrected, vd_dep->cur_volt));\r
+ if (ret < 0) {\r
+ DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
+ __func__, vd_dep->name, ret, volt_dep_new_corrected, vd_dep->cur_volt);\r
+ return -1;\r
+ }\r
+ vd_dep->cur_volt = volt_dep_new_corrected;\r
+ }\r
+ }\r
+\r
return 0;\r
}\r
\r
int dvfs_reset_volt(struct vd_node *dvfs_vd)\r
-{ \r
+{\r
int flag_set_volt_correct = 0;\r
if (!IS_ERR_OR_NULL(dvfs_vd->regulator))\r
flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_vd->regulator);\r
return -1;\r
}\r
if (flag_set_volt_correct <= 0) {\r
- DVFS_ERR("%s (clk:%s), try to reload arm_volt error %d!!! stop scaling\n", \r
+ DVFS_ERR("%s (clk:%s), try to reload arm_volt error %d!!! stop scaling\n",\r
__func__, dvfs_vd->name, flag_set_volt_correct);\r
return -1;\r
}\r
dvfs_vd->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
- DVFS_ERR("%s (clk:%s), try to reload arm_volt! arm_volt_correct = %d\n", \r
+ DVFS_ERR("%s (clk:%s), try to reload arm_volt! arm_volt_correct = %d\n",\r
__func__, dvfs_vd->name, flag_set_volt_correct);\r
\r
/* Reset vd's voltage */\r
DVFS_ERR("%s can not find vd node %s\n", __func__, dvfs_vd_dep->name);\r
return -1;\r
}\r
+\r
+static struct cpufreq_frequency_table arm_high_logic_table[] = {\r
+ {.frequency = 1416 * DVFS_KHZ, .index = 50 * DVFS_MV},\r
+ {.frequency = 1608 * DVFS_KHZ, .index = 100 * DVFS_MV},\r
+ {.frequency = CPUFREQ_TABLE_END},\r
+};\r
+\r
+static struct cpufreq_frequency_table logic_high_arm_table[] = {\r
+ {.frequency = 816 * DVFS_KHZ, .index = 200 * DVFS_MV},\r
+ {.frequency = 1416 * DVFS_KHZ, .index = 150 * DVFS_MV},\r
+ {.frequency = 1608 * DVFS_KHZ, .index = 100 * DVFS_MV},\r
+ {.frequency = CPUFREQ_TABLE_END},\r
+};\r
+\r
+int get_arm_logic_limit(unsigned long arm_rate, int *arm_high_logic, int *logic_high_arm)\r
+{\r
+ int i;\r
+\r
+ for (i = 0; arm_high_logic_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
+ if (arm_rate <= arm_high_logic_table[i].frequency) {\r
+ *arm_high_logic = arm_high_logic_table[i].index;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (arm_high_logic_table[i].frequency == CPUFREQ_TABLE_END) {\r
+ *arm_high_logic = arm_high_logic_table[i-1].index;\r
+ }\r
+\r
+ for (i = 0; logic_high_arm_table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
+ if (arm_rate <= logic_high_arm_table[i].frequency) {\r
+ *logic_high_arm = logic_high_arm_table[i].index;\r
+ break;\r
+ }\r
+ }\r
+ if (logic_high_arm_table[i].frequency == CPUFREQ_TABLE_END)\r
+ *logic_high_arm = logic_high_arm_table[i-1].index;\r
+\r
+ return 0;\r
+}\r
+\r
static struct clk_node *dvfs_clk_cpu;\r
static struct vd_node vd_core;\r
int dvfs_target_cpu(struct clk *clk, unsigned long rate_hz)\r
struct cpufreq_frequency_table clk_fv;\r
int ret = 0;\r
unsigned long rate_new, rate_old;\r
- \r
+ int cur_arm_high_logic, cur_logic_high_arm;\r
+\r
if (!clk) {\r
DVFS_ERR("%s is not a clk\n", __func__);\r
return -1;\r
rate_hz = dvfs_clk->max_rate;\r
}\r
}\r
- \r
+\r
/* need round rate */\r
rate_old = clk_get_rate(clk);\r
rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new==rate_old)\r
+ if(rate_new == rate_old)\r
return 0;\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n", \r
+\r
+ DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
dvfs_clk->name, rate_hz, rate_new, rate_old);\r
\r
/* find the clk corresponding voltage */\r
ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
if (ret <= 0)\r
goto fail_roll_back;\r
- \r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0) \r
- goto fail_roll_back;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new, \r
- ARM_HIGHER_LOGIC, LOGIC_HIGHER_ARM); \r
- if (ret < 0) \r
- goto fail_roll_back;\r
- } else {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0) \r
- goto fail_roll_back;\r
}\r
+ volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
+ if (volt_dep_new <= 0)\r
+ goto fail_roll_back;\r
+\r
+ cur_arm_high_logic = g_arm_high_logic;\r
+ cur_logic_high_arm = g_logic_high_arm;\r
+\r
+#ifdef CONFIG_ARCH_RK3066B\r
+ get_arm_logic_limit(rate_new / 1000, &g_arm_high_logic, &g_logic_high_arm);\r
+#endif\r
+\r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new,\r
+ cur_arm_high_logic, cur_logic_high_arm, g_arm_high_logic, g_logic_high_arm);\r
+ if (ret < 0)\r
+ goto fail_roll_back;\r
+\r
}\r
\r
/* scale rate */\r
ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_new);\r
if (ret <= 0)\r
goto out;\r
- \r
- volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
- if (volt_dep_new <= 0) \r
- goto out;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new, \r
- ARM_HIGHER_LOGIC, LOGIC_HIGHER_ARM); \r
- if (ret < 0) \r
- goto out;\r
- } else {\r
- ret = dvfs_scale_volt_direct(dvfs_clk->vd, volt_new);\r
- if (ret < 0) \r
- goto out;\r
}\r
+\r
+ volt_dep_new = dvfs_vd_get_newvolt_bypd(&vd_core);\r
+ if (volt_dep_new <= 0)\r
+ goto out;\r
+\r
+#ifdef CONFIG_ARCH_RK3066B\r
+ get_arm_logic_limit(rate_new / 1000, &g_arm_high_logic, &g_logic_high_arm);\r
+#endif\r
+ cur_arm_high_logic = g_arm_high_logic;\r
+ cur_logic_high_arm = g_logic_high_arm;\r
+\r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, &vd_core, volt_new, volt_dep_new,\r
+ cur_arm_high_logic, cur_logic_high_arm, g_arm_high_logic, g_logic_high_arm);\r
+ if (ret < 0)\r
+ goto out;\r
+\r
}\r
\r
return ret;\r
{\r
struct clk_node *dvfs_clk;\r
int volt_new = 0, volt_dep_new = 0, clk_volt_store = 0;\r
- \r
struct cpufreq_frequency_table clk_fv;\r
- \r
int ret = 0;\r
unsigned long rate_new, rate_old;\r
- \r
+\r
if (!clk) {\r
DVFS_ERR("%s is not a clk\n", __func__);\r
return -1;\r
rate_hz = dvfs_clk->max_rate;\r
}\r
}\r
- \r
+\r
/* need round rate */\r
rate_old = clk_get_rate(clk);\r
rate_new = clk_round_rate_nolock(clk, rate_hz);\r
- if(rate_new==rate_old)\r
+ if(rate_new == rate_old)\r
return 0;\r
- DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n", \r
+ DVFS_DBG("dvfs(%s) round rate (%lu)(rount %lu) old (%lu)\n",\r
dvfs_clk->name, rate_hz, rate_new, rate_old);\r
\r
/* find the clk corresponding voltage */\r
DVFS_DBG("-----------------------------rate_new > rate_old\n");\r
volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
\r
- if (volt_dep_new < 0) \r
+ if (volt_dep_new < 0)\r
goto fail_roll_back;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new, \r
- LOGIC_HIGHER_ARM, ARM_HIGHER_LOGIC); \r
- if (ret < 0) \r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new,\r
+ g_logic_high_arm, g_arm_high_logic, g_logic_high_arm, g_arm_high_logic);\r
+ if (ret < 0)\r
goto fail_roll_back;\r
}\r
\r
if (dvfs_clk->clk_dvfs_target) {\r
ret = dvfs_clk->clk_dvfs_target(clk, rate_new, clk_set_rate_locked);\r
} else {\r
- \r
+\r
ret = clk_set_rate_locked(clk, rate_new);\r
}\r
\r
DVFS_DBG("-----------------------------rate_new < rate_old\n");\r
volt_dep_new = dvfs_vd_get_newvolt_byclk(dvfs_clk_cpu);\r
\r
- if (volt_dep_new < 0) \r
- goto out;\r
- ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new, \r
- LOGIC_HIGHER_ARM, ARM_HIGHER_LOGIC); \r
- if (ret < 0) \r
+ if (volt_dep_new < 0)\r
goto out;\r
+ ret = dvfs_scale_volt_bystep(dvfs_clk->vd, dvfs_clk_cpu->vd, volt_new, volt_dep_new,\r
+ g_logic_high_arm, g_arm_high_logic, g_logic_high_arm, g_arm_high_logic);\r
+ goto out;\r
}\r
\r
return ret;\r
-fail_roll_back: \r
+fail_roll_back:\r
dvfs_clk->set_volt = clk_volt_store;\r
ret = dvfs_get_depend_volt(dvfs_clk, &vd_core, rate_old);\r
if (ret <= 0) {\r
static struct vd_node vd_cpu = {\r
.name = "vd_cpu",\r
.regulator_name = "vdd_cpu",\r
- .volt_set_flag =DVFS_SET_VOLT_FAILURE,\r
+ .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
.vd_dvfs_target = dvfs_target_cpu,\r
};\r
\r
static struct vd_node vd_core = {\r
.name = "vd_core",\r
.regulator_name = "vdd_core",\r
- .volt_set_flag =DVFS_SET_VOLT_FAILURE,\r
+ .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
.vd_dvfs_target = dvfs_target_core,\r
};\r
\r
static struct vd_node vd_rtc = {\r
.name = "vd_rtc",\r
.regulator_name = "vdd_rtc",\r
- .volt_set_flag =DVFS_SET_VOLT_FAILURE,\r
+ .volt_set_flag = DVFS_SET_VOLT_FAILURE,\r
.vd_dvfs_target = NULL,\r
};\r
\r
}\r
\r
static struct depend_lookup rk30_depends[] = {\r
+#ifndef CONFIG_ARCH_RK3066B\r
RK_DEPPENDS("cpu", &vd_core, dep_cpu2core_table),\r
+#endif\r
//RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
//RK_DEPPENDS("gpu", &vd_cpu, NULL),\r
};\r
for(j = 0; j < init_avs_st_num; j++) {\r
if(init_avs_paramet[j].vol <= 0)\r
continue;\r
- s += sprintf(s, "%s ,vol=%d,paramet following\n", \r
+ s += sprintf(s, "%s ,vol=%d,paramet following\n",\r
init_avs_paramet[j].s, init_avs_paramet[j].vol);\r
for(i = 0; i < init_avs_times; i++) {\r
s += sprintf(s, "%d ", init_avs_paramet[j].paramet[i]);\r
{\r
char *s = buf;\r
u32 i;\r
- \r
- if(avs_dyn_data==NULL)\r
+\r
+ if(avs_dyn_data == NULL)\r
return (s - buf);\r
- \r
+\r
if(avs_dyn_start) {\r
int start_cnt;\r
int end_cnt;\r
\r
s += sprintf(s, "\n");\r
\r
- s += sprintf(s, "max=%d,min=%d,totolcnt=%d,line=%d\n", \r
+ s += sprintf(s, "max=%d,min=%d,totolcnt=%d,line=%d\n",\r
dly_max, dly_min, avs_dyn_data_cnt, show_line_cnt);\r
show_line_cnt++;\r
if(((show_line_cnt * line_pre_show)*val_per_line) >= avs_dyn_data_cnt) {\r
const char *pbuf;\r
\r
if((strncmp(buf, "start", strlen("start")) == 0)) {\r
- if(avs_dyn_data==NULL) \r
+ if(avs_dyn_data == NULL)\r
avs_dyn_data = kmalloc(avs_dyn_data_num, GFP_KERNEL);\r
- if(avs_dyn_data==NULL)\r
+ if(avs_dyn_data == NULL)\r
return n;\r
- \r
+\r
pbuf = &buf[strlen("start")];\r
avs_dyn_data_cnt = 0;\r
show_line_cnt = 0;\r
struct clk_list *child;\r
struct clk_node *dvfs_clk;\r
struct depend_list *depend;\r
- char* s = buf;\r
- \r
+ char *s = buf;\r
+\r
s += sprintf(s, "-------------DVFS TREE-----------\n\n\n");\r
s += sprintf(s, "RK30 DVFS TREE:\n");\r
list_for_each_entry(vd, &rk_dvfs_tree, node) {\r
list_for_each_entry(child, &pd->clk_list, node) {\r
dvfs_clk = child->dvfs_clk;\r
s += sprintf(s, "| | |\n| | |- clock: %s current: rate %d, volt = %d, enable_dvfs = %s\n",\r
- dvfs_clk->name, dvfs_clk->set_freq, dvfs_clk->set_volt, \r
+ dvfs_clk->name, dvfs_clk->set_freq, dvfs_clk->set_volt,\r
dvfs_clk->enable_dvfs == 0 ? "DISABLE" : "ENABLE");\r
for (i = 0; dvfs_clk->pds[i].pd != NULL; i++) {\r
clkparent = dvfs_clk->pds[i].pd;\r
- s += sprintf(s, "| | | |- clock parents: %s, vd_parent = %s\n", \r
+ s += sprintf(s, "| | | |- clock parents: %s, vd_parent = %s\n",\r
clkparent->name, clkparent->vd->name);\r
}\r
\r
for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- s += sprintf(s, "| | | |- freq = %d, volt = %d\n", \r
- dvfs_clk->dvfs_table[i].frequency, \r
+ s += sprintf(s, "| | | |- freq = %d, volt = %d\n",\r
+ dvfs_clk->dvfs_table[i].frequency,\r
dvfs_clk->dvfs_table[i].index);\r
\r
}\r
\r
list_for_each_entry(depend, &dvfs_clk->depend_list, node2clk) {\r
- s += sprintf(s, "| | | | |- DEPEND VD: %s\n", depend->dep_vd->name); \r
+ s += sprintf(s, "| | | | |- DEPEND VD: %s\n", depend->dep_vd->name);\r
for (i = 0; (depend->dep_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
- s += sprintf(s, "| | | | |- freq = %d, req_volt = %d\n", \r
- depend->dep_table[i].frequency, \r
+ s += sprintf(s, "| | | | |- freq = %d, req_volt = %d\n",\r
+ depend->dep_table[i].frequency,\r
\r
depend->dep_table[i].index);\r
}\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff