let isTwoAddress = 0 in {
def OR8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"bis.b\t{$src, $dst}",
- [(store (or (load addr:$dst), GR8:$src), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
def OR16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
"bis.w\t{$src, $dst}",
- [(store (or (load addr:$dst), GR16:$src), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>;
def OR8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
"bis.b\t{$src, $dst}",
- [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>;
def OR16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
"bis.w\t{$src, $dst}",
- [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>;
def OR8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bis.b\t{$src, $dst}",
- [(store (or (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (i8 (load addr:$dst)),
+ (i8 (load addr:$src))), addr:$dst)]>;
def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bis.w\t{$src, $dst}",
- [(store (or (load addr:$dst), (i16 (load addr:$src))), addr:$dst),
- (implicit SRW)]>;
+ [(store (or (i16 (load addr:$dst)),
+ (i16 (load addr:$src))), addr:$dst)]>;
}
} // isTwoAddress = 1
--- /dev/null
+; RUN: llc -march=msp430 < %s
+; PR4779
+define void @foo() nounwind {
+entry:
+ %r = alloca i8 ; <i8*> [#uses=2]
+ %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
+ volatile load i8* %r, align 1 ; <i8>:0 [#uses=1]
+ or i8 %0, 1 ; <i8>:1 [#uses=1]
+ volatile store i8 %1, i8* %r, align 1
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}