ARM: zynq: DT: Migrate UART to Cadence binding
authorSoren Brinkmann <soren.brinkmann@xilinx.com>
Sat, 5 Apr 2014 00:23:45 +0000 (17:23 -0700)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 18 Jul 2014 09:54:24 +0000 (11:54 +0200)
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/boot/dts/zynq-7000.dtsi

index 760bbc463c5b18afbfb60a7b3510d70f52e27547..029cbac3045450d053f1f441cde85c3360e8f8f3 100644 (file)
                };
 
                uart0: serial@e0000000 {
-                       compatible = "xlnx,xuartps";
+                       compatible = "xlnx,xuartps", "cdns,uart-r1p8";
                        status = "disabled";
                        clocks = <&clkc 23>, <&clkc 40>;
-                       clock-names = "ref_clk", "aper_clk";
+                       clock-names = "uart_clk", "pclk";
                        reg = <0xE0000000 0x1000>;
                        interrupts = <0 27 4>;
                };
 
                uart1: serial@e0001000 {
-                       compatible = "xlnx,xuartps";
+                       compatible = "xlnx,xuartps", "cdns,uart-r1p8";
                        status = "disabled";
                        clocks = <&clkc 24>, <&clkc 41>;
-                       clock-names = "ref_clk", "aper_clk";
+                       clock-names = "uart_clk", "pclk";
                        reg = <0xE0001000 0x1000>;
                        interrupts = <0 50 4>;
                };