add uart\sdmmc 48M supporting

diff --git a/arch/arm/mach-rk30/board-rk3168-tb.c b/arch/arm/mach-rk30/board-rk3168-tb.c
index ea2cebf2310d1adeefb1129ffb40db413cceced9..e91118552272f1317f85626c2a0426d8174d5e3a 100644 (file)
--- a/arch/arm/mach-rk30/board-rk3168-tb.c
+++ b/arch/arm/mach-rk30/board-rk3168-tb.c
@@ -2579,7 +2579,8 @@ static struct cpufreq_frequency_table dvfs_ddr_table[] = {
 
 void __init board_clock_init(void)
 {
-       rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
+       rk30_clock_data_init(periph_pll_384mhz, codec_pll_594mhz, RK30_CLOCKS_DEFAULT_FLAGS);
+       //rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
        //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);    
        dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
        dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index 3f9d2420b96eb42c71cb4ac4c5f92f34e7808031..905862112554b299a9e2d4ca2593ac8d6ab434d0 100755 (executable)
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -1288,6 +1288,7 @@ static const struct pll_clk_set cpll_clks[] = {
        _PLL_SET_CLKS(456000, 1,  76,   4),
        _PLL_SET_CLKS(504000, 1,  84,   4),
        _PLL_SET_CLKS(552000, 1,  46,   2),
+       _PLL_SET_CLKS(594000, 2,  198,  4),
        _PLL_SET_CLKS(600000, 1,  50,   2),
        _PLL_SET_CLKS(742500, 8,  495,  2),
        _PLL_SET_CLKS(768000, 1,  64,   2),
@@ -1309,6 +1310,7 @@ static const struct pll_clk_set gpll_clks[] = {
        _PLL_SET_CLKS(148500,   2,      99,     8),
        _PLL_SET_CLKS(297000,   2,      198,    8),
        _PLL_SET_CLKS(300000,   1,      50,     4),
+       _PLL_SET_CLKS(384000,   1,      64,     4),
        _PLL_SET_CLKS(594000,   2,      198,    4),
        _PLL_SET_CLKS(891000,   8,      594,    2),
        _PLL_SET_CLKS(1188000,  2,      99,     1),
@@ -3272,6 +3274,11 @@ static void periph_clk_set_init(void)
                        hclk_p = aclk_p >> 0;
                        pclk_p = aclk_p >> 1;
                        break;
+               case 384 * MHZ: 
+                       aclk_p = ppll_rate >> 1; 
+                       hclk_p = aclk_p >> 1; 
+                       pclk_p = aclk_p >> 2; 
+                       break; 
                case 594 * MHZ:
                        aclk_p = ppll_rate >> 2;
                        hclk_p = aclk_p >> 0;
@@ -3312,7 +3319,12 @@ static void cpu_axi_init(void)
                        hclk_cpu_rate = aclk_cpu_rate >> 1;
                        pclk_cpu_rate = aclk_cpu_rate >> 2;
                        break;
-
+               case 384 * MHZ:
+                       cpu_div_rate = gpll_rate >> 1;
+                       aclk_cpu_rate = cpu_div_rate >> 0;
+                       hclk_cpu_rate = aclk_cpu_rate >> 1;
+                       pclk_cpu_rate = aclk_cpu_rate >> 2;
+                       break;
                case 594 * MHZ:
                        cpu_div_rate = gpll_rate >> 1;
                        aclk_cpu_rate = cpu_div_rate >> 0;
@@ -3377,6 +3389,51 @@ void rk30_clock_common_i2s_init(void)
                        clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
        }
 }
+void rk30_clock_common_uart_init(struct clk *cpll_clk,struct clk *gpll_clk)
+{
+       struct clk *p_clk;
+       unsigned long rate;
+       if(!(gpll_clk->rate%(48*MHZ)))
+       {
+               p_clk=gpll_clk;
+               rate=48*MHZ;
+       }
+       else if(!(cpll_clk->rate%(48*MHZ)))
+       {
+               p_clk=cpll_clk;
+               rate=48*MHZ;
+       }
+       else if(!(gpll_clk->rate%(49500*KHZ)))
+       {
+               p_clk=gpll_clk;
+               rate=(49500*KHZ);
+       }
+       else if(!(cpll_clk->rate%(49500*KHZ)))
+       {
+               p_clk=cpll_clk;
+               rate=(49500*KHZ);
+       }
+       else
+       {
+               if(cpll_clk->rate>gpll_clk->rate)
+               {
+                       p_clk=cpll_clk;
+               }
+               else
+               {
+                       p_clk=gpll_clk;
+               }       
+               rate=50*MHZ;
+       }
+       printk("rk30_clock_common_uart_init\n");
+       printk("%s rate%lu,gpll_clk->rate=%lu\n",__FUNCTION__,rate,gpll_clk->rate);
+       clk_set_parent_nolock(&clk_uart_pll, p_clk);
+       clk_set_rate_nolock(&clk_uart0_div,rate);
+       clk_set_rate_nolock(&clk_uart1_div,rate);
+       clk_set_rate_nolock(&clk_uart2_div,rate);
+       clk_set_rate_nolock(&clk_uart3_div,rate);
+       clk_set_rate_nolock(&clk_uart1,rate);
+}
 
 static void inline clock_set_div(struct clk *clk,u32 div)
 {
@@ -3433,10 +3490,8 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long
        clk_set_rate_nolock(&clk_spi1, clk_spi1.parent->rate);
 
        // uart
-       if((rk30_clock_flags & CLK_FLG_UART_1_3M) && (cpll_rate != 24 * MHZ))
-               clk_set_parent_nolock(&clk_uart_pll, &codec_pll_clk);
-       else
-               clk_set_parent_nolock(&clk_uart_pll, &general_pll_clk);
+       rk30_clock_common_uart_init(&codec_pll_clk,&general_pll_clk);
+
        //mac
        if(!(gpll_rate % (50 * MHZ))) {
                clk_set_parent_nolock(&clk_mac_pll_div, &general_pll_clk);

diff --git a/arch/arm/mach-rk3188/include/mach/board.h b/arch/arm/mach-rk3188/include/mach/board.h
old mode 100644 (file)
new mode 100755 (executable)
index 028ade1..2ebb501
--- a/arch/arm/mach-rk3188/include/mach/board.h
+++ b/arch/arm/mach-rk3188/include/mach/board.h
@@ -33,6 +33,7 @@ enum _periph_pll {
        periph_pll_1485mhz = 148500000,
        periph_pll_297mhz = 297000000,
        periph_pll_300mhz = 300000000,
+       periph_pll_384mhz = 384000000,
        periph_pll_594mhz = 594000000,
        periph_pll_1188mhz = 1188000000, /* for box*/
 };
@@ -42,6 +43,7 @@ enum _codec_pll {
        codec_pll_456mhz = 456000000,
        codec_pll_504mhz = 504000000,
        codec_pll_552mhz = 552000000, /* for HDMI */
+       codec_pll_594mhz = 594000000, /* for HDMI */
        codec_pll_600mhz = 600000000,
        codec_pll_742_5khz = 742500000,
        codec_pll_768mhz = 768000000,

diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index c40ddda2abb9d1958d04521ecf434fb895fd4058..54a673e28a52e5a474e3acec8330d5b8aacffe83 100644 (file)
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -349,7 +349,7 @@ struct _mmc_csd {
 //In rk2926 machine,very prone to occur data-timeout-error,the machine reduces the frequency.
 #define SDHC_FPP_FREQ         (39500000)  // SDHC in the highspeed. unit is hz,  max is 50Mhz.
 #else
-#define SDHC_FPP_FREQ         (43500000)  // SDHC in the highspeed. unit is hz,  max is 50Mhz.
+#define SDHC_FPP_FREQ         (49500000)  // SDHC in the highspeed. unit is hz,  max is 50Mhz.
 #endif
 #define MMC_FPP_FREQ          (19000000)  // MMC freq, unit is hz,   max is 20MHz
 #define MMCHS_26_FPP_FREQ     (24000000)  //  highspeed mode support 26M  HS-MMC, unit is hz, max is 26Mhz,