ARM: Cortex-A9: Enable dynamic clock gating

Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM.  This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.

Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.

Change-Id: I48e51d907e593f26982ea91b0a811553f68e3c86
Signed-off-by: Todd Poynor <toddpoynor@google.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9c26ba7244fb450b0c73f15ca2565336033e152b..34c5f56a91e07f8c5afcacd33b354f7c8b079346 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1115,6 +1115,16 @@ config ARM_ERRATA_743622
          visible impact on the overall performance or power consumption of the
          processor.
 
+config ARM_ERRATA_720791
+       bool "ARM errata: Dynamic high-level clock gating corrupts the Jazelle instruction stream"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 720791 Cortex-A9
+         (r1p0..r1p2) erratum.  The Jazelle instruction stream may be
+         corrupted when dynamic high-level clock gating is enabled.
+         This workaround disables gating the Core clock when the Instruction
+         side is waiting for a Page Table Walk answer or linefill completion.
+
 endmenu
 
 source "arch/arm/common/Kconfig"

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 197f21bed5e919f3a13f3cbc9404d428ad80fb97..f5e22615a1fe1fdab25c6b6ebadf6e0b114c89a5 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -238,6 +238,16 @@ __v7_setup:
 2:     ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
        teq     r0, r10
        bne     3f
+       cmp     r6, #0x10                       @ power ctrl reg added r1p0
+       mrcge   p15, 0, r10, c15, c0, 0         @ read power control register
+       orrge   r10, r10, #1                    @ enable dynamic clock gating
+       mcrge   p15, 0, r10, c15, c0, 0         @ write power control register
+#ifdef CONFIG_ARM_ERRATA_720791
+       teq     r5, #0x00100000                 @ only present in r1p*
+       mrceq   p15, 0, r10, c15, c0, 2         @ read "chicken power ctrl" reg
+       orreq   r10, r10, #0x30                 @ disable core clk gate on
+       mcreq   p15, 0, r10, c15, c0, 2         @ instr-side waits
+#endif
 #ifdef CONFIG_ARM_ERRATA_742230
        cmp     r6, #0x22                       @ only present up to r2p2
        mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register