ARM64: dts: rk3399: quirk for extra long delay for dwc3 xHCI

It has been reported that xHCI on this SoC really cannot
sleep without extraordinary delay. This quirk can ensure
the xHCI enter the Halted state after the Run/Stop (R/S)
bit is cleared to '0'.

Change-Id: Ibccf0c5c2da4533817b998b523e3a3a09ed7dcea
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b52e00ca6cafa429ad2e7389a1a005e0ec3308be..a5beae6b822a123f9caf151e412747e8d703dea8 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -436,6 +436,7 @@
                        snps,phyif_utmi_16_bits;
                        snps,dis_u2_freeclk_exists_quirk;
                        snps,dis_del_phy_power_chg_quirk;
+                       snps,xhci_slow_suspend_quirk;
                        status = "disabled";
                };
        };
@@ -462,6 +463,7 @@
                        snps,phyif_utmi_16_bits;
                        snps,dis_u2_freeclk_exists_quirk;
                        snps,dis_del_phy_power_chg_quirk;
+                       snps,xhci_slow_suspend_quirk;
                        status = "disabled";
                };
        };