};
#endif
+#ifdef CONFIG_RGA_RK30
+static struct resource resource_rga[] = {
+ [0] = {
+ .start = RK30_RGA_PHYS,
+ .end = RK30_RGA_PHYS + RK30_RGA_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_RGA,
+ .end = IRQ_RGA,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device device_rga = {
+ .name = "rga",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(resource_rga),
+ .resource = resource_rga,
+};
+#endif
+
#ifdef CONFIG_KEYS_RK29
extern struct rk29_keys_platform_data rk29_keys_pdata;
static struct platform_device device_keys = {
#ifdef CONFIG_KEYS_RK29
platform_device_register(&device_keys);
#endif
+#ifdef CONFIG_RGA_RK30
+ platform_device_register(&device_rga);
+#endif
#ifdef CONFIG_LCDC_RK30
platform_device_register(&device_lcdc);
#endif
obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
obj-$(CONFIG_FB_PS3) += ps3fb.o
obj-$(CONFIG_FB_RK29) += rk29_fb.o
-obj-$(CONFIG_FB_ROCKCHIP) += rockchip/
+obj-y += rockchip/
obj-$(CONFIG_FB_SM501) += sm501fb.o
obj-$(CONFIG_FB_UDL) += udlfb.o
obj-$(CONFIG_FB_XILINX) += xilinxfb.o
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
- Framebuffer driver for rochip based Platform
+ Framebuffer driver for rockchip based platform
+
config LCDC_RK30
tristate "Frame buffer driver support for rk30 lcdc "
depends on FB_ROCKCHIP
help
Frame buffer driver for rk30 lcdc based boards.
+
+source "drivers/video/rockchip/rga/Kconfig"
obj-$(CONFIG_FB_ROCKCHIP) += rk_fb.o
obj-$(CONFIG_LCDC_RK30) += chips/rk30_lcdc.o
+obj-$(CONFIG_RGA_RK30) += rga/
--- /dev/null
+menu "RGA"
+ depends on ARCH_RK30
+
+config RGA_RK30
+ tristate "ROCKCHIP RK30 RGA"
+ help
+ rk30 rga module.
+
+endmenu
--- /dev/null
+rga-y := rga_drv.o rga_mmu_info.o rga_reg_info.o RGA_API.o
+
+obj-$(CONFIG_RGA_RK30) += rga.o
--- /dev/null
+\r
+#include <linux/memory.h>\r
+#include "RGA_API.h"\r
+#include "rga.h"\r
+//#include "rga_angle.h"\r
+\r
+#define IS_YUV_420(format) \\r
+ ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \\r
+ (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP)) \r
+\r
+#define IS_YUV_422(format) \\r
+ ((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \\r
+ (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP)) \r
+\r
+#define IS_YUV(format) \\r
+ ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \\r
+ (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \\r
+ (format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \\r
+ (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))\r
+ \r
+\r
+extern rga_service_info rga_service;\r
+\r
+\r
+void\r
+matrix_cal(const struct rga_req *msg, TILE_INFO *tile)\r
+{\r
+ uint32_t x_time, y_time;\r
+ uint64_t sina, cosa;\r
+\r
+ int s_act_w, s_act_h, d_act_w, d_act_h;\r
+\r
+ s_act_w = msg->src.act_w;\r
+ s_act_h = msg->src.act_h;\r
+ d_act_w = msg->dst.act_w;\r
+ d_act_h = msg->dst.act_h;\r
+\r
+ if (s_act_w == 1) s_act_w += 1;\r
+ if (s_act_h == 1) s_act_h += 1;\r
+ if (d_act_h == 1) d_act_h += 1;\r
+ if (d_act_w == 1) d_act_w += 1;\r
+\r
+ x_time = ((s_act_w - 1)<<16) / (d_act_w - 1);\r
+ y_time = ((s_act_h - 1)<<16) / (d_act_h - 1);\r
+ \r
+ sina = msg->sina;\r
+ cosa = msg->cosa;\r
+\r
+ switch(msg->rotate_mode)\r
+ {\r
+ /* 16.16 x 16.16 */\r
+ /* matrix[] is 64 bit wide */\r
+ case 1 :\r
+ tile->matrix[0] = cosa*x_time; \r
+ tile->matrix[1] = -sina*y_time; \r
+ tile->matrix[2] = sina*x_time; \r
+ tile->matrix[3] = cosa*y_time;\r
+ break;\r
+ case 2 :\r
+ tile->matrix[0] = -(x_time<<16); \r
+ tile->matrix[1] = 0; \r
+ tile->matrix[2] = 0; \r
+ tile->matrix[3] = (y_time<<16);\r
+ break;\r
+ case 3 :\r
+ tile->matrix[0] = (x_time<<16); \r
+ tile->matrix[1] = 0; \r
+ tile->matrix[2] = 0; \r
+ tile->matrix[3] = -(y_time<<16);\r
+ break;\r
+ default :\r
+ tile->matrix[0] = (uint64_t)1<<32; \r
+ tile->matrix[1] = 0; \r
+ tile->matrix[2] = 0; \r
+ tile->matrix[3] = (uint64_t)1<<32;\r
+ break; \r
+ } \r
+}\r
+\r
+\r
+\r
+\r
+u32\r
+RGA_dst_act_addr_temp(const struct rga_req *msg)\r
+{\r
+ u32 pw;\r
+ u32 x_off, y_off;\r
+ u32 stride;\r
+ u32 p;\r
+ \r
+ pw = RGA_pixel_width_init(msg->dst.format);\r
+ stride = (msg->dst.vir_w * pw + 3) & (~3); \r
+ \r
+ x_off = msg->dst.x_offset;\r
+ y_off = msg->dst.y_offset;\r
+\r
+ p = (u32)((stride * y_off) + (x_off * pw));\r
+\r
+ return p;\r
+}\r
+\r
+void\r
+RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr)\r
+{\r
+ u32 reg = 0;\r
+ \r
+ //reg = rRGA_SYS_CTRL;\r
+ reg |= ((cmd_mode & 1) << 1);\r
+ rRGA_SYS_CTRL = reg; \r
+ rRGA_CMD_ADDR = cmd_addr;\r
+}\r
+\r
+void\r
+RGA_start(void) \r
+{\r
+ u32 reg = 0;\r
+ u8 cmd_mode;\r
+ \r
+ reg = rRGA_SYS_CTRL;\r
+ cmd_mode = (reg >> 2) & 1;\r
+ \r
+ if (cmd_mode == 0)\r
+ {\r
+ /* passive */\r
+ reg |= (1<<1);\r
+ rRGA_SYS_CTRL = reg; \r
+ }\r
+ else\r
+ {\r
+ /* master */\r
+ reg = rRGA_CMD_CTRL;\r
+ reg |= 1;\r
+ rRGA_CMD_CTRL = reg; \r
+ } \r
+}\r
+\r
+\r
+void\r
+RGA_soft_reset(void)\r
+{\r
+ u32 reg = 0;\r
+\r
+ reg = rRGA_SYS_CTRL;\r
+ reg |= 1;\r
+ rRGA_SYS_CTRL = reg; \r
+}\r
+\r
+\r
+#if 0\r
+/*****************************************/\r
+//hxx add,2011.6.24\r
+void rga_one_op_st_master(RGA_INFO *p_rga_info)\r
+{\r
+ rRGA_SYS_CTRL = 0x4;\r
+ \r
+ rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(p_rga_info->int_info.all_cmd_done_int_en)|\r
+ s_RGA_INT_MMU_INT_EN(p_rga_info->int_info.mmu_int_en)|\r
+ s_RGA_INT_ERROR_INT_EN(p_rga_info->int_info.error_int_en);\r
+ \r
+ rRGA_CMD_ADDR = (u32) p_rga_info->sys_info.p_cmd_mst;\r
+ \r
+ rRGA_CMD_CTRL = 0x3;\r
+}\r
+\r
+\r
+void rga_set_int_info(MSG *p_msg,RGA_INFO *p_rga_info)\r
+{\r
+ p_msg->CMD_fin_int_enable = p_rga_info->int_info.cur_cmd_done_int_en;\r
+}\r
+\r
+\r
+void rga_check_int_all_cmd_finish(RGA_INFO *p_rga_info)\r
+{\r
+ u8 int_flag;\r
+ \r
+ int_flag = 0;\r
+ while(!int_flag)\r
+ {\r
+ int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG;\r
+ }\r
+ rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1);\r
+ \r
+ //if(p_rga_info->sys_info.p_cmd_mst != NULL)\r
+ // free(p_rga_info->sys_info.p_cmd_mst);\r
+}\r
+#endif\r
+\r
+void rga_start_cmd_AXI(u8 *base, u32 num)\r
+{\r
+ rRGA_SYS_CTRL = 0x4;\r
+ rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(ENABLE)| s_RGA_INT_MMU_INT_EN(ENABLE)| s_RGA_INT_ERROR_INT_EN(ENABLE);\r
+ rRGA_CMD_ADDR = (u32)base; \r
+ rRGA_CMD_CTRL |= (num<<3); \r
+ rRGA_CMD_CTRL |= 0x3;\r
+}\r
+\r
+void rga_check_cmd_finish(void)\r
+{\r
+ u8 int_flag;\r
+ u8 error_flag;\r
+ \r
+ int_flag = 0;\r
+ error_flag = 0;\r
+ \r
+ while(!int_flag)\r
+ {\r
+ int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG;\r
+ error_flag = rRGA_INT & (m_RGA_INT_ERROR_INT_FLAG);\r
+\r
+ if(error_flag)\r
+ { \r
+ printk("~~~~~ ERROR INTTUR OCCUR ~~~~~\n");\r
+ }\r
+ error_flag = rRGA_INT & m_RGA_INT_MMU_INT_FLAG;\r
+ if(error_flag)\r
+ { \r
+ printk("~~~~~ MMU ERROR INTTUR OCCUR ~~~~~\n");\r
+ }\r
+ }\r
+ rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1); \r
+}\r
+\r
+\r
+\r
+void rga_start_cmd_AHB(u8 *base)\r
+{\r
+ u32 *base_p32;\r
+ \r
+ base_p32 = (u32 *)base;\r
+ *base_p32 = (*base_p32 | (1<<29));\r
+\r
+ memcpy((u8 *)(RGA_BASE + 0x100), base, 28*4);\r
+ \r
+ rRGA_SYS_CTRL = 0x2;\r
+}\r
+\r
+\r
+void rga_check_cmd_AHB_finish(void)\r
+{\r
+ u8 int_flag;\r
+ \r
+ int_flag = 0;\r
+ while(!int_flag)\r
+ {\r
+ int_flag = rRGA_INT & m_RGA_INT_NOW_CMD_DONE_INT_FLAG;\r
+ }\r
+ rRGA_INT = rRGA_INT | s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(0x1);\r
+}\r
+\r
+\r
+\r
+uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)\r
+{\r
+ \r
+ struct rga_req *mp;\r
+ u32 w_ratio, h_ratio;\r
+ u32 stride;\r
+\r
+ u32 daw, dah;\r
+ u32 pl;\r
+\r
+ daw = dah = 0;\r
+ \r
+ mp = msg1;\r
+ w_ratio = (msg->src.act_w << 16) / msg->dst.act_w;\r
+ h_ratio = (msg->src.act_h << 16) / msg->dst.act_h;\r
+\r
+ memcpy(&mp->src, &msg->src, sizeof(rga_img_info_t));\r
+\r
+ mp->dst.format = msg->src.format;\r
+\r
+ /*pre_scale_w cal*/\r
+ if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) { \r
+ daw = (msg->src.act_w + 1) >> 1;\r
+ if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {\r
+ mp->src.act_w = (daw - 1) << 1; \r
+ } \r
+ }\r
+ else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) {\r
+ daw = (msg->src.act_w + 3) >> 2; \r
+ if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {\r
+ mp->src.act_w = (daw - 1) << 2; \r
+ }\r
+ }\r
+ else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) {\r
+ daw = (msg->src.act_w + 7) >> 3;\r
+ if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {\r
+ mp->src.act_w = (daw - 1) << 3; \r
+ }\r
+ }\r
+\r
+ pl = (RGA_pixel_width_init(msg->src.format));\r
+ stride = (pl * daw + 3) & (~3);\r
+ mp->dst.act_w = daw;\r
+ mp->dst.vir_w = stride / pl;\r
+\r
+ /*pre_scale_h cal*/ \r
+ if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) { \r
+ dah = (msg->src.act_h + 1) >> 1; \r
+ if((IS_YUV(mp->dst.format)) && (dah & 1)) {\r
+ mp->src.act_h = (dah - 1) << 1; \r
+ } \r
+ }\r
+ else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) {\r
+ dah = (msg->src.act_h + 3) >> 2; \r
+ if((IS_YUV(mp->dst.format)) && (dah & 1)) {\r
+ mp->src.act_h = (dah - 1) << 2; \r
+ }\r
+ }\r
+ else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) {\r
+ dah = (msg->src.act_h + 7) >> 3;\r
+ if((IS_YUV(mp->dst.format)) && (dah & 1)) {\r
+ mp->src.act_h = (dah - 1) << 3; \r
+ }\r
+ }\r
+ mp->dst.act_h = dah;\r
+ mp->dst.vir_h = dah;\r
+ \r
+ mp->dst.yrgb_addr = (u32)rga_service.pre_scale_buf;\r
+ mp->dst.uv_addr = mp->dst.yrgb_addr + stride * dah;\r
+ mp->dst.v_addr = mp->dst.uv_addr + ((stride * dah) >> 1);\r
+\r
+ mp->render_mode = pre_scaling_mode;\r
+\r
+ memcpy(&msg->src, &mp->dst, sizeof(rga_img_info_t));\r
+ \r
+ return 0;\r
+}\r
+\r
+\r
--- /dev/null
+#ifndef __RGA_API_H__\r
+#define __RGA_API_H__\r
+\r
+#include "rga_reg_info.h"\r
+#include "rga.h"\r
+\r
+#define ENABLE 1\r
+#define DISABLE 0\r
+\r
+#if 0\r
+int\r
+RGA_set_src_act_info(\r
+ msg_t *msg,\r
+ unsigned int width, /* act width */\r
+ unsigned int height, /* act height */\r
+ unsigned int x_off, /* x_off */\r
+ unsigned int y_off /* y_off */\r
+ );\r
+\r
+int\r
+RGA_set_src_vir_info(\r
+ msg_t *msg,\r
+ unsigned int yrgb_addr, /* yrgb_addr */\r
+ unsigned int uv_addr, /* uv_addr */\r
+ unsigned int v_addr, /* v_addr */\r
+ unsigned int vir_w, /* vir width */\r
+ unsigned int vir_h, /* vir height */\r
+ unsigned char format, /* format */\r
+ unsigned char a_swap_en\r
+ );\r
+\r
+int\r
+RGA_set_dst_act_info(\r
+ msg_t *msg,\r
+ unsigned int width, /* act width */\r
+ unsigned int height, /* act height */\r
+ unsigned int x_off, /* x_off */\r
+ unsigned int y_off /* y_off */\r
+ );\r
+\r
+int\r
+RGA_set_dst_vir_info(\r
+ msg_t *msg,\r
+ unsigned int yrgb_addr, /* yrgb_addr */\r
+ unsigned int uv_addr, /* uv_addr */\r
+ unsigned int v_addr, /* v_addr */\r
+ unsigned int vir_w, /* vir width */\r
+ unsigned int vir_h, /* vir height */\r
+ RECT clip, /* clip window*/\r
+ unsigned char format, /* format */\r
+ unsigned char a_swap_en );\r
+\r
+\r
+\r
+int\r
+RGA_set_rop_mask_info(\r
+ msg_t *msg, \r
+ u32 rop_mask_addr, \r
+ u32 rop_mask_endian_mode);\r
+\r
+int \r
+RGA_set_pat_info(\r
+ msg_t *msg,\r
+ u32 width,\r
+ u32 height,\r
+ u32 x_off,\r
+ u32 y_off,\r
+ u32 pat_format); \r
+\r
+int\r
+RGA_set_alpha_en_info(\r
+ msg_t *msg,\r
+ unsigned int alpha_cal_mode,\r
+ unsigned int alpha_mode,\r
+ unsigned int global_a_value,\r
+ unsigned int PD_en,\r
+ unsigned int PD_mode\r
+ );\r
+\r
+int\r
+RGA_set_rop_en_info(\r
+ msg_t *msg,\r
+ unsigned int ROP_mode,\r
+ unsigned int ROP_code,\r
+ unsigned int color_mode,\r
+ unsigned int solid_color);\r
+\r
+/*\r
+int\r
+RGA_set_MMU_info(\r
+ MSG *msg,\r
+ unsigned int base_addr,\r
+ unsigned int src_flush,\r
+ unsigned int dst_flush,\r
+ unsigned int cmd_flush,\r
+ unsigned int page_size\r
+ );\r
+*/\r
+\r
+int\r
+RGA_set_MMU_info(\r
+ msg_t *msg,\r
+ u8 mmu_en,\r
+ u8 src_flush,\r
+ u8 dst_flush,\r
+ u8 cmd_flush,\r
+ u32 base_addr,\r
+ u8 page_size);\r
+\r
+\r
+int\r
+RGA_set_bitblt_mode(\r
+ msg_t *msg,\r
+ unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic \r
+ unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror \r
+ unsigned int angle, // rotate angle (0~359) \r
+ unsigned int dither_en, // dither en flag \r
+ unsigned int AA_en, // AA flag \r
+ unsigned int yuv2rgb_mode\r
+ );\r
+\r
+\r
+int\r
+RGA_set_color_palette_mode(\r
+ msg_t *msg,\r
+ u8 palette_mode, /* 1bpp/2bpp/4bpp/8bpp */\r
+ u8 endian_mode, /* src endian mode sel */\r
+ u32 bpp1_0_color, /* BPP1 = 0 */\r
+ u32 bpp1_1_color /* BPP1 = 1 */\r
+ );\r
+\r
+\r
+\r
+int\r
+RGA_set_color_fill_mode(\r
+ msg_t *msg,\r
+ CF_GR_COLOR gr_color, /* gradient color part*/\r
+ u8 gr_satur_mode, /* saturation mode */\r
+ u8 cf_mode, /* patten fill or solid fill */\r
+ u32 color, /* solid color */\r
+ u16 pat_width, /* pat_width */\r
+ u16 pat_height, /* pat_height */\r
+ u8 pat_x_off, /* patten x offset */\r
+ u8 pat_y_off, /* patten y offset */\r
+ u8 aa_en /* alpha en */\r
+ );\r
+\r
+\r
+int\r
+RGA_set_line_point_drawing_mode(\r
+ msg_t *msg,\r
+ POINT sp, /* start point */\r
+ POINT ep, /* end point */\r
+ unsigned int color, /* line point drawing color */\r
+ unsigned int line_width, /* line width */\r
+ unsigned char AA_en, /* AA en */\r
+ unsigned char last_point_en /* last point en */\r
+ );\r
+\r
+\r
+\r
+int\r
+RGA_set_blur_sharp_filter_mode(\r
+ msg_t *msg,\r
+ unsigned char filter_mode, /* blur/sharpness */\r
+ unsigned char filter_type, /* filter intensity */\r
+ unsigned char dither_en /* dither_en flag */\r
+ );\r
+\r
+int\r
+RGA_set_pre_scaling_mode(\r
+ msg_t *msg,\r
+ unsigned char dither_en\r
+ );\r
+\r
+\r
+int\r
+RGA_update_palette_table_mode(\r
+ msg_t *msg,\r
+ unsigned int LUT_addr, /* LUT table addr */\r
+ unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */\r
+ );\r
+\r
+\r
+int\r
+RGA_set_update_patten_buff_mode(\r
+ msg_t *msg,\r
+ unsigned int pat_addr, /* patten addr */\r
+ unsigned int w, /* patten width */\r
+ unsigned int h, /* patten height */\r
+ unsigned int format /* patten format */\r
+ );\r
+/*\r
+int\r
+RGA_set_MMU_info(\r
+ MSG *msg,\r
+ unsigned int base_addr,\r
+ unsigned int src_flush,\r
+ unsigned int dst_flush,\r
+ unsigned int cmd_flush,\r
+ unsigned int page_size\r
+ );\r
+*/\r
+\r
+int\r
+RGA_set_mmu_info(\r
+ msg_t *msg,\r
+ u8 mmu_en,\r
+ u8 src_flush,\r
+ u8 dst_flush,\r
+ u8 cmd_flush,\r
+ u32 base_addr,\r
+ u8 page_size);\r
+\r
+msg_t * RGA_init_msg(void);\r
+int RGA_free_msg(msg_t *msg);\r
+void matrix_cal(msg_t *msg, TILE_INFO *tile);\r
+unsigned char * RGA_set_reg_info(msg_t *msg, u8 *base);\r
+void RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr);\r
+void RGA_start(void);\r
+void RGA_soft_reset(void);\r
+#endif\r
+\r
+uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1);\r
+\r
+\r
+#endif\r
--- /dev/null
+#ifndef _RGA_DRIVER_H_\r
+#define _RGA_DRIVER_H_\r
+\r
+#include "rga_type.h"\r
+#include <linux/types.h>\r
+#include <linux/miscdevice.h>\r
+#include <linux/platform_device.h>\r
+\r
+\r
+#define RGA_BLIT_SYNC 0x5017\r
+#define RGA_BLIT_ASYNC 0x5018\r
+#define RGA_FLUSH 0x5019\r
+\r
+\r
+#define RGA_REG_CTRL_LEN 0x8 /* 8 */\r
+#define RGA_REG_CMD_LEN 0x1c /* 28 */\r
+#define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */\r
+\r
+\r
+/* RGA process mode enum */\r
+enum\r
+{ \r
+ bitblt_mode = 0x0,\r
+ color_palette_mode = 0x1,\r
+ color_fill_mode = 0x2,\r
+ line_point_drawing_mode = 0x3,\r
+ blur_sharp_filter_mode = 0x4,\r
+ pre_scaling_mode = 0x5,\r
+ update_palette_table_mode = 0x6,\r
+ update_patten_buff_mode = 0x7,\r
+};\r
+\r
+\r
+enum\r
+{\r
+ rop_enable_mask = 0x2,\r
+ dither_enable_mask = 0x8,\r
+ fading_enable_mask = 0x10,\r
+ PD_enbale_mask = 0x20,\r
+};\r
+\r
+enum\r
+{\r
+ yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */\r
+ yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */\r
+ yuv2rgb_mode2 = 0x2, /* BT.709 */\r
+};\r
+\r
+\r
+/* RGA rotate mode */\r
+enum \r
+{\r
+ rotate_mode0 = 0x0, /* no rotate */\r
+ rotate_mode1 = 0x1, /* rotate */\r
+ rotate_mode2 = 0x2, /* x_mirror */\r
+ rotate_mode3 = 0x3, /* y_mirror */\r
+};\r
+\r
+enum\r
+{\r
+ color_palette_mode0 = 0x0, /* 1K */\r
+ color_palette_mode1 = 0x1, /* 2K */\r
+ color_palette_mode2 = 0x2, /* 4K */\r
+ color_palette_mode3 = 0x3, /* 8K */\r
+};\r
+\r
+\r
+\r
+/*\r
+// Alpha Red Green Blue \r
+{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 \r
+{ 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 \r
+{ 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888\r
+{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888\r
+{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 \r
+{ 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 \r
+{ 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444\r
+{ 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888\r
+\r
+*/\r
+enum\r
+{\r
+ RK_FORMAT_RGBA_8888 = 0x0,\r
+ RK_FORMAT_RGBX_8888 = 0x1,\r
+ RK_FORMAT_RGB_888 = 0x2,\r
+ RK_FORMAT_BGRA_8888 = 0x3,\r
+ RK_FORMAT_RGB_565 = 0x4,\r
+ RK_FORMAT_RGBA_5551 = 0x5,\r
+ RK_FORMAT_RGBA_4444 = 0x6,\r
+ RK_FORMAT_BGR_888 = 0x7,\r
+ \r
+ RK_FORMAT_YCbCr_422_SP = 0x8, \r
+ RK_FORMAT_YCbCr_422_P = 0x9, \r
+ RK_FORMAT_YCbCr_420_SP = 0xa, \r
+ RK_FORMAT_YCbCr_420_P = 0xb,\r
+\r
+ RK_FORMAT_YCrCb_422_SP = 0xc, \r
+ RK_FORMAT_YCrCb_422_P = 0xd, \r
+ RK_FORMAT_YCrCb_420_SP = 0xe, \r
+ RK_FORMAT_YCrCb_420_P = 0xf,\r
+ \r
+ RK_FORMAT_BPP1 = 0x10,\r
+ RK_FORMAT_BPP2 = 0x11,\r
+ RK_FORMAT_BPP4 = 0x12,\r
+ RK_FORMAT_BPP8 = 0x13,\r
+};\r
+ \r
+ \r
+typedef struct rga_img_info_t\r
+{\r
+ uint32 yrgb_addr; /* yrgb mem addr */\r
+ uint32 uv_addr; /* cb/cr mem addr */\r
+ uint32 v_addr; /* cr mem addr */\r
+ uint32 format; //definition by RK_FORMAT\r
+ \r
+ UWORD16 act_w;\r
+ UWORD16 act_h;\r
+ UWORD16 x_offset;\r
+ UWORD16 y_offset;\r
+ \r
+ UWORD16 vir_w;\r
+ UWORD16 vir_h;\r
+ \r
+ UWORD16 endian_mode; //for BPP\r
+ UWORD16 alpha_swap;\r
+}\r
+rga_img_info_t;\r
+\r
+\r
+typedef struct mdp_img_act\r
+{\r
+ UWORD16 w; // width\r
+ UWORD16 h; // height\r
+ WORD16 x_off; // x offset for the vir\r
+ WORD16 y_off; // y offset for the vir\r
+}\r
+mdp_img_act;\r
+\r
+\r
+\r
+typedef struct RANGE\r
+{\r
+ UWORD16 min;\r
+ UWORD16 max;\r
+}\r
+RANGE;\r
+\r
+typedef struct POINT\r
+{\r
+ UWORD16 x;\r
+ UWORD16 y;\r
+}\r
+POINT;\r
+\r
+typedef struct RECT\r
+{\r
+ WORD16 xmin;\r
+ WORD16 xmax; // width - 1\r
+ WORD16 ymin; \r
+ WORD16 ymax; // height - 1 \r
+} RECT;\r
+\r
+typedef struct RGB\r
+{\r
+ unsigned char r;\r
+ unsigned char g;\r
+ unsigned char b;\r
+ unsigned char res;\r
+}RGB;\r
+\r
+\r
+typedef struct MMU\r
+{\r
+ unsigned char mmu_en;\r
+ uint32 base_addr;\r
+ uint32 mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/\r
+} MMU;\r
+\r
+\r
+\r
+\r
+typedef struct COLOR_FILL\r
+{\r
+ short gr_x_a;\r
+ short gr_y_a;\r
+ short gr_x_b;\r
+ short gr_y_b;\r
+ short gr_x_g;\r
+ short gr_y_g;\r
+ short gr_x_r;\r
+ short gr_y_r;\r
+\r
+ //u8 cp_gr_saturation;\r
+}\r
+COLOR_FILL;\r
+\r
+typedef struct FADING\r
+{\r
+ UBYTE b;\r
+ UBYTE g;\r
+ UBYTE r;\r
+ UBYTE res;\r
+}\r
+FADING;\r
+\r
+\r
+typedef struct line_draw_t\r
+{\r
+ POINT start_point; /* LineDraw_start_point */\r
+ POINT end_point; /* LineDraw_end_point */\r
+ uint32 color; /* LineDraw_color */\r
+ uint32 flag; /* (enum) LineDrawing mode sel */\r
+ uint32 line_width; /* range 1~16 */\r
+}\r
+line_draw_t;\r
+\r
+\r
+\r
+struct rga_req {\r
+ UBYTE render_mode; /* (enum) process mode sel */\r
+ \r
+ rga_img_info_t src; /* src image info */\r
+ rga_img_info_t dst; /* dst image info */\r
+ rga_img_info_t pat; /* patten image info */\r
+\r
+ uint32 rop_mask_addr; /* rop4 mask addr */\r
+ uint32 LUT_addr; /* LUT addr */\r
+ \r
+ RECT clip; /* dst clip window default value is dst_vir */\r
+ /* value from [0, w-1] / [0, h-1]*/\r
+ \r
+ int32_t sina; /* dst angle default value 0 16.16 scan from table */\r
+ int32_t cosa; /* dst angle default value 0 16.16 scan from table */ \r
+\r
+ uint16_t alpha_rop_flag; /* alpha rop process flag */\r
+ /* ([0] = 1 alpha_rop_enable) */\r
+ /* ([1] = 1 rop enable) */ \r
+ /* ([2] = 1 fading_enable) */\r
+ /* ([3] = 1 PD_enable) */\r
+ /* ([4] = 1 alpha cal_mode_sel) */\r
+ /* ([5] = 1 dither_enable) */\r
+ /* ([6] = 1 gradient fill mode sel) */\r
+ /* ([7] = 1 AA_enable) */\r
+\r
+ uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ \r
+ \r
+ uint32 color_key_max; /* color key max */\r
+ uint32 color_key_min; /* color key min */ \r
+\r
+ uint32 fg_color; /* foreground color */\r
+ uint32 bg_color; /* background color */\r
+\r
+ COLOR_FILL gr_color; /* color fill use gradient */\r
+ \r
+ line_draw_t line_draw_info;\r
+ \r
+ FADING fading;\r
+ \r
+ uint8_t PD_mode; /* porter duff alpha mode sel */\r
+ \r
+ uint8_t alpha_global_value; /* global alpha value */\r
+ \r
+ uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/\r
+ \r
+ uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/\r
+ \r
+ uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/\r
+\r
+ uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ \r
+ \r
+ uint8_t endian_mode; /* 0/big endian 1/little endian*/\r
+\r
+ uint8_t rotate_mode; /* (enum) rotate mode */\r
+ /* 0x0, no rotate */\r
+ /* 0x1, rotate */\r
+ /* 0x2, x_mirror */\r
+ /* 0x3, y_mirror */\r
+\r
+ uint8_t color_fill_mode; /* 0 solid color / 1 patten color */\r
+ \r
+ MMU mmu_info; /* mmu information */\r
+\r
+ uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */\r
+ /* ([2~3] rop mode) */\r
+ /* ([4] zero mode en) */\r
+ /* ([5] dst alpha mode) */\r
+\r
+ uint8_t src_trans_mode;\r
+\r
+ uint8_t CMD_fin_int_enable; \r
+\r
+ /* completion is reported through a callback */\r
+ void (*complete)(int retval);\r
+};\r
+\r
+ \r
+typedef struct TILE_INFO\r
+{\r
+ int64_t matrix[4];\r
+ \r
+ uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */\r
+ uint16_t tile_y_num; /* y axis tile num */\r
+\r
+ int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */\r
+ int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */\r
+\r
+ uint16_t tile_w;\r
+ uint16_t tile_h;\r
+ int16_t tile_start_x_coor;\r
+ int16_t tile_start_y_coor;\r
+ int32_t tile_xoff;\r
+ int32_t tile_yoff;\r
+\r
+ int32_t tile_temp_xstart;\r
+ int32_t tile_temp_ystart;\r
+\r
+ /* src tile incr */\r
+ int32_t x_dx;\r
+ int32_t x_dy;\r
+ int32_t y_dx;\r
+ int32_t y_dy;\r
+\r
+ mdp_img_act dst_ctrl;\r
+ \r
+}\r
+TILE_INFO; \r
+\r
+\r
+/**\r
+ * struct for process session which connect to rga\r
+ *\r
+ * @author ZhangShengqin (2012-2-15)\r
+ */\r
+typedef struct rga_session {\r
+ /* a linked list of data so we can access them for debugging */\r
+ struct list_head list_session;\r
+ /* a linked list of register data waiting for process */\r
+ struct list_head waiting;\r
+ /* a linked list of register data in processing */\r
+ struct list_head running;\r
+ /* all coommand this thread done */\r
+ uint32_t done;\r
+ wait_queue_head_t wait;\r
+ pid_t pid;\r
+ atomic_t task_running;\r
+} rga_session;\r
+\r
+struct rga_reg {\r
+ rga_session *session;\r
+ struct list_head session_link; /* link to rga service session */\r
+ struct list_head status_link; /* link to register set list */\r
+ uint32_t sys_reg[RGA_REG_CTRL_LEN];\r
+ uint32_t cmd_reg[RGA_REG_CMD_LEN];\r
+ uint32_t *MMU_base;\r
+ atomic_t int_enable;\r
+};\r
+\r
+\r
+\r
+typedef struct rga_service_info {\r
+ spinlock_t lock;\r
+ struct timer_list timer; /* timer for power off */\r
+ struct list_head waiting; /* link to link_reg in struct vpu_reg */\r
+ struct list_head running; /* link to link_reg in struct vpu_reg */\r
+ struct list_head done; /* link to link_reg in struct vpu_reg */\r
+ struct list_head session; /* link to list_session in struct vpu_session */\r
+ atomic_t total_running;\r
+ bool enabled;\r
+ struct rga_reg *reg;\r
+ uint32_t cmd_buff[28*16];/* cmd_buff for rga */\r
+ uint32_t *pre_scale_buf;\r
+ atomic_t int_disable; /* 0 int enable 1 int disable */\r
+} rga_service_info;\r
+\r
+\r
+\r
+\r
+struct rga_drvdata {\r
+ struct miscdevice miscdev;\r
+ struct device dev;\r
+ void *rga_base;\r
+ int irq0;\r
+\r
+ struct clk *pd_display;\r
+ struct clk *aclk_lcdc;\r
+ struct clk *hclk_lcdc;\r
+ struct clk *aclk_ddr_lcdc;\r
+ struct clk *hclk_cpu_display;\r
+ struct clk *aclk_disp_matrix;\r
+ struct clk *hclk_disp_matrix;\r
+ struct clk *axi_clk;\r
+ struct clk *ahb_clk;\r
+ \r
+ struct mutex mutex; // mutex\r
+ \r
+ struct delayed_work power_off_work;\r
+ bool enable; //clk enable or disable\r
+ void (*rga_irq_callback)(int rga_retval); //callback function used by aync call\r
+};\r
+\r
+\r
+\r
+\r
+\r
+#define RGA_BASE 0x10114000\r
+\r
+//General Registers\r
+#define RGA_SYS_CTRL 0x000\r
+#define RGA_CMD_CTRL 0x004\r
+#define RGA_CMD_ADDR 0x008\r
+#define RGA_STATUS 0x00c\r
+#define RGA_INT 0x010\r
+#define RGA_AXI_ID 0x014\r
+#define RGA_MMU_STA_CTRL 0x018\r
+#define RGA_MMU_STA 0x01c\r
+\r
+//Command code start\r
+#define RGA_MODE_CTRL 0x100\r
+\r
+//Source Image Registers\r
+#define RGA_SRC_Y_MST 0x104\r
+#define RGA_SRC_CB_MST 0x108\r
+#define RGA_MASK_READ_MST 0x108 //repeat\r
+#define RGA_SRC_CR_MST 0x10c\r
+#define RGA_SRC_VIR_INFO 0x110\r
+#define RGA_SRC_ACT_INFO 0x114\r
+#define RGA_SRC_X_PARA 0x118\r
+#define RGA_SRC_Y_PARA 0x11c\r
+#define RGA_SRC_TILE_XINFO 0x120\r
+#define RGA_SRC_TILE_YINFO 0x124\r
+#define RGA_SRC_TILE_H_INCR 0x128\r
+#define RGA_SRC_TILE_V_INCR 0x12c\r
+#define RGA_SRC_TILE_OFFSETX 0x130\r
+#define RGA_SRC_TILE_OFFSETY 0x134\r
+#define RGA_SRC_BG_COLOR 0x138\r
+#define RGA_SRC_FG_COLOR 0x13c\r
+#define RGA_LINE_DRAWING_COLOR 0x13c //repeat\r
+#define RGA_SRC_TR_COLOR0 0x140\r
+#define RGA_CP_GR_A 0x140 //repeat\r
+#define RGA_SRC_TR_COLOR1 0x144\r
+#define RGA_CP_GR_B 0x144 //repeat\r
+\r
+#define RGA_LINE_DRAW 0x148\r
+#define RGA_PAT_START_POINT 0x148 //repeat\r
+\r
+//Destination Image Registers\r
+#define RGA_DST_MST 0x14c\r
+#define RGA_LUT_MST 0x14c //repeat\r
+#define RGA_PAT_MST 0x14c //repeat\r
+#define RGA_LINE_DRAWING_MST 0x14c //repeat\r
+\r
+#define RGA_DST_VIR_INFO 0x150\r
+\r
+#define RGA_DST_CTR_INFO 0x154\r
+#define RGA_LINE_DRAW_XY_INFO 0x154 //repeat \r
+\r
+//Alpha/ROP Registers\r
+#define RGA_ALPHA_CON 0x158\r
+\r
+#define RGA_PAT_CON 0x15c\r
+#define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat\r
+\r
+#define RGA_ROP_CON0 0x160\r
+#define RGA_CP_GR_G 0x160 //repeat\r
+#define RGA_PRESCL_CB_MST 0x160 //repeat\r
+\r
+#define RGA_ROP_CON1 0x164\r
+#define RGA_CP_GR_R 0x164 //repeat\r
+#define RGA_PRESCL_CR_MST 0x164 //repeat\r
+\r
+//MMU Register\r
+#define RGA_FADING_CON 0x168\r
+#define RGA_MMU_CTRL 0x168 //repeat\r
+\r
+#define RGA_MMU_TBL 0x16c //repeat\r
+\r
+\r
+#define RGA_BLIT_COMPLETE_EVENT 1\r
+\r
+\r
+\r
+\r
+#endif /*_RK29_IPP_DRIVER_H_*/\r
--- /dev/null
+/* \r
+ * Copyright (C) 2012 ROCKCHIP, Inc.\r
+ *\r
+ * This software is licensed under the terms of the GNU General Public\r
+ * License version 2, as published by the Free Software Foundation, and\r
+ * may be copied, distributed, and modified under those terms.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ */\r
+\r
+#include <linux/kernel.h>\r
+#include <linux/init.h>\r
+#include <linux/module.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/sched.h>\r
+#include <linux/mutex.h>\r
+#include <linux/err.h>\r
+#include <linux/clk.h>\r
+#include <asm/delay.h>\r
+#include <linux/dma-mapping.h>\r
+#include <linux/delay.h>\r
+#include <asm/io.h>\r
+#include <linux/irq.h>\r
+#include <linux/interrupt.h>\r
+#include <mach/io.h>\r
+#include <mach/irqs.h>\r
+#include <linux/fs.h>\r
+#include <asm/uaccess.h>\r
+#include <linux/firmware.h>\r
+#include <linux/miscdevice.h>\r
+#include <linux/poll.h>\r
+#include <linux/delay.h>\r
+#include <linux/wait.h>\r
+#include <linux/syscalls.h>\r
+#include <linux/timer.h>\r
+#include <linux/time.h>\r
+#include <asm/cacheflush.h>\r
+#include <linux/compiler.h>\r
+#include <linux/slab.h>\r
+\r
+\r
+#include "rga.h"\r
+#include "rga_reg_info.h"\r
+#include "rga_mmu_info.h"\r
+#include "RGA_API.h"\r
+\r
+\r
+#define PRE_SCALE_BUF_SIZE 2048*1024*4\r
+\r
+#define RGA_POWER_OFF_DELAY 4*HZ /* 4s */\r
+#define RGA_TIMEOUT_DELAY 2*HZ /* 2s */\r
+\r
+\r
+\r
+\r
+static struct rga_drvdata *drvdata = NULL;\r
+rga_service_info rga_service;\r
+\r
+\r
+static int rga_blit_async(rga_session *session, struct rga_req *req);\r
+\r
+\r
+#define RGA_MAJOR 232\r
+\r
+#define RK30_RGA_PHYS 0x10114000\r
+#define RK30_RGA_SIZE SZ_8K\r
+#define RGA_RESET_TIMEOUT 1000\r
+\r
+/* Driver information */\r
+#define DRIVER_DESC "RGA Device Driver"\r
+#define DRIVER_NAME "rga"\r
+\r
+\r
+/* Logging */\r
+#define RGA_DEBUG 0\r
+#if RGA_DEBUG\r
+#define DBG(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)\r
+#define ERR(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)\r
+#define WARNING(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)\r
+#define INFO(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)\r
+#else\r
+#define DBG(format, args...)\r
+#define ERR(format, args...)\r
+#define WARNING(format, args...)\r
+#define INFO(format, args...)\r
+#endif\r
+\r
+\r
+static inline void rga_write(u32 b, u32 r)\r
+{\r
+ __raw_writel(b, drvdata->rga_base + r);\r
+}\r
+\r
+static inline u32 rga_read(u32 r)\r
+{\r
+ return __raw_readl(drvdata->rga_base + r);\r
+}\r
+\r
+static void rga_soft_reset(void)\r
+{\r
+ u32 i;\r
+ u32 reg;\r
+\r
+ rga_write(1, RGA_SYS_CTRL); //RGA_SYS_CTRL\r
+\r
+ for(i = 0; i < RGA_RESET_TIMEOUT; i++) {\r
+ reg = rga_read(RGA_SYS_CTRL) & 1; //RGA_SYS_CTRL\r
+\r
+ if(reg == 0)\r
+ break;\r
+\r
+ udelay(1);\r
+ }\r
+\r
+ if(i == RGA_RESET_TIMEOUT)\r
+ ERR("soft reset timeout.\n");\r
+}\r
+\r
+static void rga_dump(void)\r
+{\r
+ int running;\r
+ struct rga_reg *reg, *reg_tmp;\r
+ rga_session *session, *session_tmp;\r
+\r
+ running = atomic_read(&rga_service.total_running);\r
+ printk("total_running %d\n", running);\r
+\r
+ list_for_each_entry_safe(session, session_tmp, &rga_service.session, list_session) \r
+ {\r
+ printk("session pid %d:\n", session->pid);\r
+ running = atomic_read(&session->task_running);\r
+ printk("task_running %d\n", running);\r
+ list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) \r
+ {\r
+ printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
+ }\r
+ list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) \r
+ {\r
+ printk("running register set 0x%.8x\n", (unsigned int)reg);\r
+ }\r
+ }\r
+}\r
+\r
+\r
+static void rga_power_on(void)\r
+{\r
+ //printk("rga_power_on\n");\r
+ cancel_delayed_work_sync(&drvdata->power_off_work);\r
+ if (drvdata->enable)\r
+ return;\r
+ \r
+ clk_enable(drvdata->pd_display);\r
+ clk_enable(drvdata->aclk_lcdc);\r
+ clk_enable(drvdata->hclk_lcdc);\r
+ clk_enable(drvdata->aclk_ddr_lcdc);\r
+ clk_enable(drvdata->hclk_cpu_display);\r
+ clk_enable(drvdata->aclk_disp_matrix);\r
+ clk_enable(drvdata->hclk_disp_matrix);\r
+ clk_enable(drvdata->axi_clk);\r
+ clk_enable(drvdata->ahb_clk);\r
+\r
+ drvdata->enable = true;\r
+}\r
+\r
+\r
+static void rga_power_off(struct work_struct *work)\r
+{\r
+ int total_running;\r
+ \r
+ //printk("rga_power_off\n");\r
+ if(!drvdata->enable)\r
+ return;\r
+\r
+ total_running = atomic_read(&rga_service.total_running);\r
+ if (total_running) {\r
+ pr_alert("power off when %d task running!!\n", total_running); \r
+ mdelay(50);\r
+ pr_alert("delay 50 ms for running task\n"); \r
+ rga_dump();\r
+ }\r
+ \r
+ clk_disable(drvdata->pd_display);\r
+ clk_disable(drvdata->aclk_lcdc);\r
+ clk_disable(drvdata->hclk_lcdc);\r
+ clk_disable(drvdata->aclk_ddr_lcdc);\r
+ clk_disable(drvdata->hclk_cpu_display);\r
+ clk_disable(drvdata->aclk_disp_matrix);\r
+ clk_disable(drvdata->hclk_disp_matrix);\r
+ clk_disable(drvdata->axi_clk);\r
+ clk_disable(drvdata->ahb_clk);\r
+\r
+ drvdata->enable = false;\r
+}\r
+\r
+\r
+static int rga_flush(rga_session *session, unsigned long arg)\r
+{\r
+ //printk("rga_get_result %d\n",drvdata->rga_result);\r
+ \r
+ int ret;\r
+\r
+ ret = wait_event_interruptible_timeout(session->wait, session->done, RGA_TIMEOUT_DELAY);\r
+ \r
+ if (unlikely(ret < 0)) {\r
+ pr_err("pid %d wait task ret %d\n", session->pid, ret);\r
+ } else if (0 == ret) {\r
+ pr_err("pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
+ ret = -ETIMEDOUT;\r
+ }\r
+ \r
+ return ret;\r
+}\r
+\r
+\r
+static int rga_check_param(const struct rga_req *req)\r
+{\r
+ #if 1\r
+ /*RGA can support up to 8192*8192 resolution in RGB format,but we limit the image size to 8191*8191 here*/\r
+ //check src width and height\r
+ if (unlikely((req->src.act_w < 0) || (req->src.act_w > 8191) || (req->src.act_h < 0) || (req->src.act_h > 8191))) {\r
+ ERR("invalid source resolution\n");\r
+ return -EINVAL;\r
+ }\r
+\r
+ //check dst width and height\r
+ if (unlikely((req->dst.act_w < 0) || (req->dst.act_w > 2048) || (req->dst.act_h < 16) || (req->dst.act_h > 2048))) {\r
+ ERR("invalid destination resolution\n");\r
+ return -EINVAL;\r
+ }\r
+\r
+ //check src_vir_w\r
+ if(unlikely(req->src.vir_w < req->src.act_w)){\r
+ ERR("invalid src_vir_w\n");\r
+ return -EINVAL;\r
+ }\r
+\r
+ //check dst_vir_w\r
+ if(unlikely(req->dst.vir_w < req->dst.act_w)){\r
+ ERR("invalid dst_vir_w\n");\r
+ return -EINVAL;\r
+ }\r
+\r
+ //check src address\r
+ if (unlikely(req->src.yrgb_addr == 0))\r
+ {\r
+ ERR("could not retrieve src image from memory\n");\r
+ return -EINVAL;\r
+ }\r
+ \r
+ //check src address\r
+ if (unlikely(req->dst.yrgb_addr == 0))\r
+ {\r
+ ERR("could not retrieve dst image from memory\n");\r
+ return -EINVAL;\r
+ }\r
+ #endif\r
+ \r
+ \r
+ return 0;\r
+}\r
+\r
+static void rga_copy_reg(struct rga_reg *reg, uint32_t offset)\r
+{ \r
+ uint32_t i;\r
+ uint32_t *cmd_buf;\r
+ uint32_t *reg_p;\r
+ \r
+ atomic_add(1, &rga_service.total_running);\r
+ atomic_add(1, ®->session->task_running);\r
+ \r
+ cmd_buf = (uint32_t *)rga_service.cmd_buff + offset*28;\r
+ reg_p = (uint32_t *)reg->cmd_reg;\r
+ \r
+ for(i=0; i<28; i++) \r
+ {\r
+ cmd_buf[i] = reg_p[i];\r
+ } \r
+}\r
+\r
+\r
+static struct rga_reg * rga_reg_init(rga_session *session, struct rga_req *req)\r
+{\r
+ unsigned long flag;\r
+ struct rga_reg *reg = kmalloc(sizeof(struct rga_reg), GFP_KERNEL);\r
+ if (NULL == reg) {\r
+ pr_err("kmalloc fail in rga_reg_init\n");\r
+ return NULL;\r
+ }\r
+\r
+ reg->session = session;\r
+ INIT_LIST_HEAD(®->session_link);\r
+ INIT_LIST_HEAD(®->status_link);\r
+\r
+ rga_set_mmu_info(reg, req);\r
+ RGA_gen_reg_info(req, (uint8_t *)reg->cmd_reg); \r
+\r
+ spin_lock_irqsave(&rga_service.lock, flag);\r
+ list_add_tail(®->status_link, &rga_service.waiting);\r
+ list_add_tail(®->session_link, &session->waiting);\r
+ spin_unlock_irqrestore(&rga_service.lock, flag);\r
+\r
+ return reg;\r
+}\r
+\r
+static void rga_reg_deinit(struct rga_reg *reg)\r
+{\r
+ list_del_init(®->session_link);\r
+ list_del_init(®->status_link);\r
+ kfree(reg); \r
+}\r
+\r
+static void rga_reg_from_wait_to_run(struct rga_reg *reg)\r
+{\r
+ list_del_init(®->status_link);\r
+ list_add_tail(®->status_link, &rga_service.running);\r
+\r
+ list_del_init(®->session_link);\r
+ list_add_tail(®->session_link, ®->session->running);\r
+}\r
+\r
+#if 0\r
+static void rga_reg_from_run_to_done(struct rga_reg *reg)\r
+{\r
+ spin_lock(&rga_service.lock);\r
+ list_del_init(®->status_link);\r
+ list_add_tail(®->status_link, &rga_service.done);\r
+\r
+ list_del_init(®->session_link);\r
+ list_add_tail(®->session_link, ®->session->done);\r
+ \r
+ atomic_sub(1, ®->session->task_running);\r
+ atomic_sub(1, &rga_service.total_running);\r
+ wake_up_interruptible_sync(®->session->wait);\r
+ spin_unlock(&rga_service.lock);\r
+}\r
+#endif\r
+\r
+\r
+static void rga_service_session_clear(rga_session *session)\r
+{\r
+ struct rga_reg *reg, *n;\r
+\r
+ list_for_each_entry_safe(reg, n, &session->waiting, session_link) \r
+ {\r
+ rga_reg_deinit(reg);\r
+ }\r
+\r
+ list_for_each_entry_safe(reg, n, &session->running, session_link) \r
+ {\r
+ rga_reg_deinit(reg);\r
+ }\r
+}\r
+\r
+\r
+static void rga_try_set_reg(void)\r
+{\r
+ unsigned long flag;\r
+ \r
+ // first get reg from reg list\r
+ spin_lock_irqsave(&rga_service.lock, flag);\r
+ if (!list_empty(&rga_service.waiting)) \r
+ {\r
+ struct rga_reg *reg = list_entry(rga_service.waiting.next, struct rga_reg, status_link);\r
+\r
+ if(!(rga_read(RGA_STATUS) & 0x1)) \r
+ { \r
+ /* RGA is busy */\r
+ if((atomic_read(&rga_service.total_running) <= 0xf) && (atomic_read(&rga_service.int_disable) == 0)) \r
+ {\r
+ rga_copy_reg(reg, atomic_read(&rga_service.total_running));\r
+ rga_reg_from_wait_to_run(reg);\r
+ rga_write(RGA_INT, 0x1<<10);\r
+ reg->session->done = 0;\r
+ rga_write(RGA_CMD_CTRL, (0x1<<3)|(0x1<<1));\r
+ if(atomic_read(®->int_enable))\r
+ atomic_set(&rga_service.int_disable, 1);\r
+ }\r
+ }\r
+ else \r
+ { \r
+ /* RGA is idle */\r
+ rga_copy_reg(reg, 0); \r
+ rga_reg_from_wait_to_run(reg);\r
+\r
+ /* MMU */\r
+ rga_write(RGA_CMD_ADDR, 0);\r
+\r
+ /* All CMD finish int */\r
+ rga_write(RGA_INT, 0x1<<10);\r
+\r
+ /* Start proc */\r
+ reg->session->done = 0;\r
+ rga_write(RGA_CMD_CTRL, (0x1<<3)|0x1); \r
+ } \r
+ }\r
+ spin_unlock_irqrestore(&rga_service.lock, flag);\r
+}\r
+\r
+\r
+\r
+static int rga_blit_async(rga_session *session, struct rga_req *req)\r
+{\r
+ int ret = -1;\r
+ struct rga_reg *reg0, *reg1;\r
+ struct rga_req *req2;\r
+\r
+ uint32_t saw, sah, daw, dah;\r
+ \r
+ saw = req->src.act_w;\r
+ sah = req->src.act_h;\r
+ daw = req->dst.act_w;\r
+ dah = req->dst.act_h;\r
+\r
+ if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) \r
+ {\r
+ /* generate 2 cmd for pre scale */\r
+ \r
+ req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL);\r
+ if(NULL == req2) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ RGA_gen_two_pro(req, req2);\r
+\r
+ reg0 = rga_reg_init(session, req2);\r
+ if(reg0 == NULL) {\r
+ return -EFAULT;\r
+ }\r
+\r
+ reg1 = rga_reg_init(session, req);\r
+ if(reg1 == NULL) {\r
+ return -EFAULT;\r
+ }\r
+\r
+ rga_try_set_reg();\r
+ rga_try_set_reg();\r
+\r
+ if(req2 != NULL)\r
+ {\r
+ kfree(req2);\r
+ }\r
+\r
+ }\r
+ else {\r
+ /* check value if legal */\r
+ ret = rga_check_param(req);\r
+ if(ret == -EINVAL) {\r
+ return -EINVAL;\r
+ }\r
+ \r
+ reg0 = rga_reg_init(session, req);\r
+ if(reg0 == NULL) {\r
+ return -EFAULT;\r
+ }\r
+ \r
+ rga_try_set_reg(); \r
+ }\r
+ \r
+ //printk("rga_blit_async done******************\n");\r
+\r
+#if 0 \r
+error_status:\r
+error_scale:\r
+ ret = -EINVAL;\r
+ rga_soft_reset();\r
+ rga_power_off();\r
+#endif \r
+ return ret; \r
+\r
+}\r
+\r
+static int rga_blit_sync(rga_session *session, struct rga_req *req)\r
+{\r
+ int ret = 0;\r
+ struct rga_reg *reg0, *reg1;\r
+ struct rga_req *req2;\r
+\r
+ uint32_t saw, sah, daw, dah;\r
+ \r
+ saw = req->src.act_w;\r
+ sah = req->src.act_h;\r
+ daw = req->dst.act_w;\r
+ dah = req->dst.act_h;\r
+\r
+ if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) \r
+ {\r
+ /* generate 2 cmd for pre scale */\r
+ \r
+ req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL);\r
+ if(NULL == req2) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ RGA_gen_two_pro(req, req2);\r
+\r
+ reg0 = rga_reg_init(session, req2);\r
+ if(reg0 == NULL) {\r
+ return -EFAULT;\r
+ }\r
+\r
+ reg1 = rga_reg_init(session, req);\r
+ if(reg1 == NULL) {\r
+ return -EFAULT;\r
+ }\r
+ atomic_set(®1->int_enable, 1);\r
+\r
+ rga_try_set_reg();\r
+ rga_try_set_reg(); \r
+\r
+ }\r
+ else {\r
+ /* check value if legal */\r
+ ret = rga_check_param(req);\r
+ if(ret == -EINVAL) {\r
+ return -EFAULT;\r
+ }\r
+ \r
+ reg0 = rga_reg_init(session, req);\r
+ if(reg0 == NULL) {\r
+ return -EFAULT;\r
+ }\r
+ atomic_set(®0->int_enable, 1);\r
+ \r
+ rga_try_set_reg();\r
+ } \r
+\r
+ ret = wait_event_interruptible_timeout(session->wait, session->done, RGA_TIMEOUT_DELAY);\r
+\r
+ if (unlikely(ret < 0)) \r
+ {\r
+ pr_err("pid %d wait task ret %d\n", session->pid, ret);\r
+ } \r
+ else if (0 == ret) \r
+ {\r
+ pr_err("pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
+ ret = -ETIMEDOUT;\r
+ }\r
+\r
+ return ret;\r
+ \r
+ //printk("rga_blit_sync done******************\n");\r
+}\r
+\r
+static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)\r
+{\r
+ struct rga_req *req;\r
+ int ret = 0;\r
+ rga_session *session = (rga_session *)file->private_data;\r
+ if (NULL == session) \r
+ {\r
+ printk("%s [%d] rga thread session is null\n",__FUNCTION__,__LINE__);\r
+ return -EINVAL;\r
+ }\r
+\r
+ req = (struct rga_req *)kmalloc(sizeof(struct rga_req), GFP_KERNEL);\r
+ if(req == NULL) \r
+ {\r
+ printk("%s [%d] get rga_req mem failed\n",__FUNCTION__,__LINE__);\r
+ ret = -EINVAL;\r
+ }\r
+ \r
+ if (unlikely(copy_from_user(&req, (struct rga_req*)arg, sizeof(struct rga_req)))) \r
+ {\r
+ ERR("copy_from_user failed\n");\r
+ ret = -EFAULT;\r
+ }\r
+ \r
+ switch (cmd)\r
+ {\r
+ case RGA_BLIT_SYNC:\r
+ ret = rga_blit_sync(session, req);\r
+ break;\r
+ case RGA_BLIT_ASYNC:\r
+ ret = rga_blit_async(session, req); \r
+ break;\r
+ case RGA_FLUSH:\r
+ ret = rga_flush(session, arg);\r
+ break;\r
+ default:\r
+ ERR("unknown ioctl cmd!\n");\r
+ ret = -EINVAL;\r
+ break;\r
+ }\r
+\r
+ if(req != NULL)\r
+ {\r
+ kfree(req);\r
+ }\r
+ \r
+ return ret;\r
+}\r
+\r
+static int rga_open(struct inode *inode, struct file *file)\r
+{\r
+ rga_session *session = (rga_session *)kmalloc(sizeof(rga_session), GFP_KERNEL);\r
+ if (NULL == session) {\r
+ pr_err("unable to allocate memory for rga_session.");\r
+ return -ENOMEM;\r
+ }\r
+\r
+ session->pid = current->pid;\r
+ INIT_LIST_HEAD(&session->waiting);\r
+ INIT_LIST_HEAD(&session->running);\r
+ INIT_LIST_HEAD(&session->list_session);\r
+ init_waitqueue_head(&session->wait);\r
+ /* no need to protect */\r
+ list_add_tail(&session->list_session, &rga_service.session);\r
+ atomic_set(&session->task_running, 0);\r
+ file->private_data = (void *)session;\r
+\r
+ DBG("*** rga dev opened *** \n");\r
+ return nonseekable_open(inode, file);\r
+ \r
+}\r
+\r
+static int rga_release(struct inode *inode, struct file *file)\r
+{\r
+ int task_running;\r
+ unsigned long flag;\r
+ rga_session *session = (rga_session *)file->private_data;\r
+ if (NULL == session)\r
+ return -EINVAL;\r
+\r
+ task_running = atomic_read(&session->task_running);\r
+ if (task_running) {\r
+ pr_err("rga_service session %d still has %d task running when closing\n", session->pid, task_running);\r
+ msleep(50);\r
+ }\r
+ wake_up_interruptible_sync(&session->wait);\r
+ spin_lock_irqsave(&rga_service.lock, flag);\r
+ list_del(&session->list_session);\r
+ rga_service_session_clear(session);\r
+ kfree(session);\r
+ spin_unlock_irqrestore(&rga_service.lock, flag);\r
+\r
+ pr_debug("dev closed\n");\r
+ return 0;\r
+}\r
+\r
+static irqreturn_t rga_irq(int irq, void *dev_id)\r
+{\r
+ struct rga_reg *reg;\r
+\r
+ DBG("rga_irq %d \n", irq);\r
+\r
+ /*clear INT */\r
+ rga_write(rga_read(RGA_INT) | (0x1<<6), RGA_INT);\r
+ if(((rga_read(RGA_STATUS) & 0x1) != 0))// idle\r
+ { \r
+ printk("RGA is not idle!\n");\r
+ rga_soft_reset();\r
+ }\r
+\r
+ spin_lock(&rga_service.lock);\r
+ do\r
+ {\r
+ reg = list_entry(rga_service.running.next, struct rga_reg, status_link);\r
+ if(reg->MMU_base != NULL)\r
+ {\r
+ kfree(reg->MMU_base);\r
+ }\r
+ \r
+ atomic_sub(1, ®->session->task_running);\r
+ atomic_sub(1, &rga_service.total_running);\r
+ \r
+ if(list_empty(®->session->waiting))\r
+ {\r
+ reg->session->done = 1;\r
+ wake_up_interruptible_sync(®->session->wait);\r
+ }\r
+ rga_reg_deinit(reg);\r
+ \r
+ }\r
+ while(!list_empty(&rga_service.running));\r
+\r
+\r
+ /* add cmd to cmd buf */\r
+ while(((!list_empty(&rga_service.waiting)) && (atomic_read(&rga_service.int_disable) == 0)))\r
+ {\r
+ rga_try_set_reg();\r
+ }\r
+\r
+ spin_lock(&rga_service.lock);\r
+ \r
+ return IRQ_HANDLED;\r
+}\r
+\r
+static int rga_suspend(struct platform_device *pdev, pm_message_t state)\r
+{\r
+ uint32_t enable;\r
+ \r
+ enable = drvdata->enable;\r
+ rga_power_off(NULL);\r
+ drvdata->enable = enable;\r
+\r
+ return 0;\r
+}\r
+\r
+static int rga_resume(struct platform_device *pdev)\r
+{\r
+ rga_power_on();\r
+ return 0;\r
+}\r
+\r
+static void rga_shutdown(struct platform_device *pdev)\r
+{\r
+ pr_cont("shutdown..."); \r
+ rga_power_off(NULL);\r
+ pr_cont("done\n");\r
+}\r
+\r
+\r
+\r
+struct file_operations rga_fops = {\r
+ .owner = THIS_MODULE,\r
+ .open = rga_open,\r
+ .release = rga_release,\r
+ .unlocked_ioctl = rga_ioctl,\r
+};\r
+\r
+static struct miscdevice rga_dev ={\r
+ .minor = RGA_MAJOR,\r
+ .name = "rga",\r
+ .fops = &rga_fops,\r
+};\r
+\r
+static int __devinit rga_drv_probe(struct platform_device *pdev)\r
+{\r
+ struct rga_drvdata *data;\r
+ int ret = 0;\r
+\r
+ data = kmalloc(sizeof(struct rga_drvdata), GFP_KERNEL);\r
+\r
+ INIT_LIST_HEAD(&rga_service.waiting);\r
+ INIT_LIST_HEAD(&rga_service.running);\r
+ INIT_LIST_HEAD(&rga_service.done);\r
+ INIT_LIST_HEAD(&rga_service.session);\r
+ spin_lock_init(&rga_service.lock);\r
+ atomic_set(&rga_service.total_running, 0);\r
+ rga_service.enabled = false; \r
+ \r
+ if(NULL == data)\r
+ {\r
+ ERR("failed to allocate driver data.\n");\r
+ return -ENOMEM;\r
+ }\r
+ \r
+ /* get the clock */\r
+ data->pd_display = clk_get(&pdev->dev, "pd_display");\r
+ if (IS_ERR(data->pd_display))\r
+ {\r
+ ERR("failed to find rga pd_display source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ data->aclk_lcdc = clk_get(&pdev->dev, "aclk_lcdc");\r
+ if (IS_ERR(data->aclk_lcdc))\r
+ {\r
+ ERR("failed to find rga aclk_lcdc source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+ \r
+ data->hclk_lcdc = clk_get(&pdev->dev, "hclk_lcdc");\r
+ if (IS_ERR(data->hclk_lcdc))\r
+ {\r
+ ERR("failed to find rga hclk_lcdc source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ data->aclk_ddr_lcdc = clk_get(&pdev->dev, "aclk_ddr_lcdc");\r
+ if (IS_ERR(data->aclk_ddr_lcdc))\r
+ {\r
+ ERR("failed to find rga aclk_ddr_lcdc source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ data->hclk_cpu_display = clk_get(&pdev->dev, "hclk_cpu_display");\r
+ if (IS_ERR(data->hclk_cpu_display))\r
+ {\r
+ ERR("failed to find rga hclk_cpu_display source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ data->aclk_disp_matrix = clk_get(&pdev->dev, "aclk_disp_matrix");\r
+ if (IS_ERR(data->aclk_disp_matrix))\r
+ {\r
+ ERR("failed to find rga aclk_disp_matrix source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ data->hclk_disp_matrix = clk_get(&pdev->dev, "hclk_disp_matrix");\r
+ if (IS_ERR(data->hclk_disp_matrix))\r
+ {\r
+ ERR("failed to find rga hclk_disp_matrix source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+ \r
+ data->axi_clk = clk_get(&pdev->dev, "aclk_rga");\r
+ if (IS_ERR(data->axi_clk))\r
+ {\r
+ ERR("failed to find rga axi clock source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ data->ahb_clk = clk_get(&pdev->dev, "hclk_rga");\r
+ if (IS_ERR(data->ahb_clk))\r
+ {\r
+ ERR("failed to find rga ahb clock source\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ /* map the memory */\r
+ if (!request_mem_region(RK30_RGA_PHYS, RK30_RGA_SIZE, "rga_io")) \r
+ {\r
+ pr_info("failed to reserve rga HW regs\n");\r
+ return -EBUSY;\r
+ }\r
+ data->rga_base = (void*)ioremap_nocache(RK30_RGA_PHYS, RK30_RGA_SIZE);\r
+ if (data->rga_base == NULL)\r
+ {\r
+ ERR("rga ioremap failed\n");\r
+ ret = -ENOENT;\r
+ goto err_ioremap;\r
+ }\r
+\r
+ /* get the IRQ */\r
+ data->irq0 = pdev->resource[1].start;\r
+ printk("rga irq %d\n", data->irq0);\r
+ if (data->irq0 <= 0)\r
+ {\r
+ ERR("failed to get rga irq resource (%d).\n", data->irq0);\r
+ ret = data->irq0;\r
+ goto err_irq;\r
+ }\r
+\r
+ /* request the IRQ */\r
+ ret = request_irq(data->irq0, rga_irq, 0/*IRQF_DISABLED*/, "rga", pdev);\r
+ if (ret)\r
+ {\r
+ ERR("rga request_irq failed (%d).\n", ret);\r
+ goto err_irq;\r
+ }\r
+\r
+ mutex_init(&data->mutex);\r
+ data->enable = false;\r
+ INIT_DELAYED_WORK(&data->power_off_work, rga_power_off);\r
+ data->rga_irq_callback = NULL;\r
+ \r
+ platform_set_drvdata(pdev, data);\r
+ drvdata = data;\r
+\r
+ ret = misc_register(&rga_dev);\r
+ if(ret)\r
+ {\r
+ ERR("cannot register miscdev (%d)\n", ret);\r
+ goto err_misc_register;\r
+ }\r
+ DBG("RGA Driver loaded succesfully\n");\r
+\r
+ return 0; \r
+\r
+err_misc_register:\r
+ free_irq(data->irq0, pdev);\r
+err_irq:\r
+ iounmap(data->rga_base);\r
+err_ioremap:\r
+err_clock:\r
+ kfree(data);\r
+\r
+ return ret;\r
+}\r
+\r
+static int rga_drv_remove(struct platform_device *pdev)\r
+{\r
+ struct rga_drvdata *data = platform_get_drvdata(pdev);\r
+ DBG("%s [%d]\n",__FUNCTION__,__LINE__);\r
+\r
+ misc_deregister(&(data->miscdev));\r
+ free_irq(data->irq0, &data->miscdev);\r
+ iounmap((void __iomem *)(data->rga_base));\r
+\r
+ if(data->axi_clk) {\r
+ clk_put(data->axi_clk);\r
+ }\r
+ \r
+ if(data->ahb_clk) {\r
+ clk_put(data->ahb_clk);\r
+ }\r
+ if(data->aclk_disp_matrix) {\r
+ clk_put(data->aclk_disp_matrix);\r
+ }\r
+\r
+ if(data->hclk_disp_matrix) {\r
+ clk_put(data->hclk_disp_matrix);\r
+ }\r
+ \r
+ if(data->aclk_ddr_lcdc) {\r
+ clk_put(data->aclk_ddr_lcdc);\r
+ }\r
+ \r
+ if(data->hclk_lcdc) {\r
+ clk_put(data->hclk_lcdc);\r
+ }\r
+\r
+ if(data->aclk_lcdc) {\r
+ clk_put(data->aclk_lcdc);\r
+ }\r
+ \r
+ if(data->hclk_cpu_display) {\r
+ clk_put(data->hclk_cpu_display);\r
+ }\r
+\r
+ if(data->pd_display){\r
+ clk_put(data->pd_display);\r
+ }\r
+\r
+ kfree(data);\r
+ return 0;\r
+}\r
+\r
+static struct platform_driver rga_driver = {\r
+ .probe = rga_drv_probe,\r
+ .remove = __devexit_p(rga_drv_remove),\r
+ .suspend = rga_suspend,\r
+ .resume = rga_resume,\r
+ .shutdown = rga_shutdown,\r
+ .driver = {\r
+ .owner = THIS_MODULE,\r
+ .name = "rga",\r
+ },\r
+};\r
+\r
+static int __init rga_init(void)\r
+{\r
+ int ret;\r
+ uint8_t *buf;\r
+\r
+ /* malloc pre scale mid buf */\r
+ buf = kmalloc(PRE_SCALE_BUF_SIZE, GFP_KERNEL);\r
+ if(buf == NULL) {\r
+ ERR("RGA get Pre Scale buff failed. \n");\r
+ return -1;\r
+ }\r
+ rga_service.pre_scale_buf = (uint32_t *)buf;\r
+\r
+ if ((ret = platform_driver_register(&rga_driver)) != 0)\r
+ {\r
+ ERR("Platform device register failed (%d).\n", ret);\r
+ return ret;\r
+ }\r
+ \r
+ INFO("Module initialized.\n");\r
+ \r
+ return 0;\r
+}\r
+\r
+static void __exit rga_exit(void)\r
+{\r
+ if(rga_service.pre_scale_buf != NULL) {\r
+ kfree((uint8_t *)rga_service.pre_scale_buf);\r
+ }\r
+ platform_driver_unregister(&rga_driver); \r
+}\r
+\r
+\r
+\r
+module_init(rga_init);\r
+module_exit(rga_exit);\r
+\r
+\r
+/* Module information */\r
+MODULE_AUTHOR("zsq@rock-chips.com");\r
+MODULE_DESCRIPTION("Driver for rga device");\r
+MODULE_LICENSE("GPL");\r
+\r
+\r
--- /dev/null
+\r
+\r
+#include <linux/version.h>\r
+#include <linux/init.h>\r
+#include <linux/module.h>\r
+#include <linux/fs.h>\r
+#include <linux/sched.h>\r
+#include <linux/signal.h>\r
+#include <linux/pagemap.h>\r
+#include <linux/seq_file.h>\r
+#include <linux/mm.h>\r
+#include <linux/mman.h>\r
+#include <linux/sched.h>\r
+#include <linux/slab.h>\r
+#include <asm/atomic.h>\r
+\r
+\r
+#include "rga_mmu_info.h"\r
+\r
+\r
+extern rga_service_info rga_service;\r
+\r
+#define KERNEL_SPACE_VALID 0xc0000000\r
+\r
+static int rga_mem_size_cal(uint32_t Mem, uint32_t MemSize, uint32_t *StartAddr) \r
+{\r
+ uint32_t start, end;\r
+ uint32_t pageCount;\r
+\r
+ end = (Mem + (MemSize + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = Mem >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ *StartAddr = start;\r
+ return pageCount; \r
+}\r
+\r
+static int rga_buf_size_cal(uint32_t yrgb_addr, uint32_t uv_addr, uint32_t v_addr, \r
+ int format, uint32_t w, uint32_t h, uint32_t *StartAddr ) \r
+{\r
+ uint32_t size_yrgb = 0;\r
+ uint32_t size_uv = 0;\r
+ uint32_t size_v = 0;\r
+ uint32_t stride = 0;\r
+ uint32_t start, end;\r
+ uint32_t pageCount;\r
+ \r
+ switch(format)\r
+ {\r
+ case RK_FORMAT_RGBA_8888 :\r
+ stride = (w * 4 + 3) & (~3);\r
+ size_yrgb = stride*h;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start; \r
+ break;\r
+ case RK_FORMAT_RGBX_8888 :\r
+ stride = (w * 4 + 3) & (~3);\r
+ size_yrgb = stride*h;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_RGB_888 :\r
+ stride = (w * 3 + 3) & (~3);\r
+ size_yrgb = stride*h;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_BGRA_8888 :\r
+ size_yrgb = w*h*4;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ *StartAddr = start;\r
+ break;\r
+ case RK_FORMAT_RGB_565 :\r
+ stride = (w*2 + 3) & (~3); \r
+ size_yrgb = stride * h;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_RGBA_5551 :\r
+ stride = (w*2 + 3) & (~3); \r
+ size_yrgb = stride * h;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_RGBA_4444 :\r
+ stride = (w*2 + 3) & (~3); \r
+ size_yrgb = stride * h;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_BGR_888 :\r
+ stride = (w*3 + 3) & (~3); \r
+ size_yrgb = stride * h;\r
+ end = (yrgb_addr + (size_yrgb + PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ start = yrgb_addr >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+\r
+ /* YUV FORMAT */\r
+ case RK_FORMAT_YCbCr_422_SP :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = stride * h;\r
+ start = MIN(yrgb_addr, uv_addr);\r
+ start >>= PAGE_SHIFT; \r
+ end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start; \r
+ break;\r
+ case RK_FORMAT_YCbCr_422_P :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = ((stride >> 1) * h);\r
+ size_v = ((stride >> 1) * h);\r
+ start = MIN(MIN(yrgb_addr, uv_addr), v_addr);\r
+ start = start >> PAGE_SHIFT; \r
+ end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start; \r
+ break;\r
+ case RK_FORMAT_YCbCr_420_SP :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = (stride * (h >> 1)); \r
+ start = MIN(yrgb_addr, uv_addr);\r
+ start >>= PAGE_SHIFT; \r
+ end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_P :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = ((stride >> 1) * (h >> 1));\r
+ size_v = ((stride >> 1) * (h >> 1));\r
+ start = MIN(MIN(yrgb_addr, uv_addr), v_addr);\r
+ start >>= PAGE_SHIFT; \r
+ end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start; \r
+ break;\r
+\r
+ case RK_FORMAT_YCrCb_422_SP :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = stride * h;\r
+ start = MIN(yrgb_addr, uv_addr);\r
+ start >>= PAGE_SHIFT; \r
+ end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_P :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = ((stride >> 1) * h);\r
+ size_v = ((stride >> 1) * h);\r
+ start = MIN(MIN(yrgb_addr, uv_addr), v_addr);\r
+ start >>= PAGE_SHIFT; \r
+ end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ \r
+ case RK_FORMAT_YCrCb_420_SP :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = (stride * (h >> 1)); \r
+ start = MIN(yrgb_addr, uv_addr);\r
+ start >>= PAGE_SHIFT; \r
+ end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_P :\r
+ stride = (w + 3) & (~3);\r
+ size_yrgb = stride * h;\r
+ size_uv = ((stride >> 1) * (h >> 1));\r
+ size_v = ((stride >> 1) * (h >> 1));\r
+ start = MIN(MIN(yrgb_addr, uv_addr), v_addr);\r
+ start >>= PAGE_SHIFT; \r
+ end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));\r
+ end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;\r
+ pageCount = end - start;\r
+ break;\r
+ #if 0 \r
+ case RK_FORMAT_BPP1 : \r
+ break;\r
+ case RK_FORMAT_BPP2 :\r
+ break;\r
+ case RK_FORMAT_BPP4 :\r
+ break;\r
+ case RK_FORMAT_BPP8 :\r
+ break;\r
+ #endif \r
+ default :\r
+ pageCount = 0;\r
+ start = 0;\r
+ break;\r
+ }\r
+\r
+ *StartAddr = start;\r
+ return pageCount; \r
+}\r
+\r
+static int rga_MapUserMemory(struct page **pages, \r
+ uint32_t *pageTable, \r
+ uint32_t Memory, \r
+ uint32_t pageCount)\r
+{\r
+ int32_t result;\r
+ uint32_t i;\r
+ \r
+ down_read(¤t->mm->mmap_sem);\r
+ result = get_user_pages(current,\r
+ current->mm,\r
+ Memory << PAGE_SHIFT,\r
+ pageCount,\r
+ 1,\r
+ 0,\r
+ pages,\r
+ NULL\r
+ );\r
+ up_read(¤t->mm->mmap_sem);\r
+ \r
+ if(result <= 0 || result < pageCount) \r
+ {\r
+ return -EINVAL; \r
+ }\r
+\r
+ for (i = 0; i < pageCount; i++)\r
+ {\r
+ /* Flush the data cache. */\r
+#ifdef ANDROID\r
+ dma_sync_single_for_device(\r
+ gcvNULL,\r
+ page_to_phys(pages[i]),\r
+ PAGE_SIZE,\r
+ DMA_TO_DEVICE);\r
+#else\r
+ flush_dcache_page(pages[i]);\r
+#endif\r
+ }\r
+\r
+ /* Fill the page table. */\r
+ for(i=0; i<pageCount; i++) {\r
+\r
+ /* Get the physical address from page struct. */\r
+ pageTable[i * (PAGE_SIZE/4096)] = page_to_phys(pages[i]);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)\r
+{ \r
+ int SrcMemSize, DstMemSize, CMDMemSize;\r
+ uint32_t SrcStart, DstStart, CMDStart; \r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base, *MMU_p;\r
+ int ret;\r
+\r
+ struct page **pages = NULL;\r
+\r
+ /* cal src buf mmu info */ \r
+ SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,\r
+ req->src.format, req->src.vir_w, req->src.vir_h,\r
+ &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal dst buf mmu info */ \r
+ DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal cmd buf mmu info */\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+ \r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = (uint32_t)virt_to_phys((uint32_t *)((CMDStart + i)<< PAGE_SHIFT));\r
+ }\r
+\r
+ if(req->src.yrgb_addr < KERNEL_SPACE_VALID)\r
+ {\r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed");\r
+ return -EINVAL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MMU_p = MMU_Base + CMDMemSize;\r
+ \r
+ for(i=0; i<SrcMemSize; i++)\r
+ {\r
+ MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));\r
+ }\r
+ }\r
+ \r
+ if(req->dst.yrgb_addr < KERNEL_SPACE_VALID)\r
+ {\r
+ ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map dst memory failed");\r
+ return -EINVAL;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MMU_p = MMU_Base + CMDMemSize + SrcMemSize;\r
+ \r
+ for(i=0; i<DstMemSize; i++)\r
+ {\r
+ MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((DstStart + i) << PAGE_SHIFT));\r
+ } \r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base);\r
+ \r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+\r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);\r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+static int rga_mmu_info_color_palette_mode(struct rga_reg *reg, struct rga_req *req)\r
+{\r
+ int SrcMemSize, DstMemSize, CMDMemSize;\r
+ uint32_t SrcStart, DstStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base;\r
+ int ret;\r
+ uint32_t stride;\r
+\r
+ uint8_t shift;\r
+ uint16_t sw, byte_num;\r
+ \r
+ shift = 3 - (req->palette_mode & 3);\r
+ sw = req->src.vir_w;\r
+ byte_num = sw >> shift;\r
+ stride = (byte_num + 3) & (~3);\r
+ \r
+ SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, stride, &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+ \r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i)<<PAGE_SHIFT));\r
+ }\r
+ \r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map dst memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base); \r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);\r
+\r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+static int rga_mmu_info_color_fill_mode(struct rga_reg *reg, struct rga_req *req)\r
+{\r
+ int DstMemSize, CMDMemSize;\r
+ uint32_t DstStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base;\r
+ int ret;\r
+ \r
+ DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+ \r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart+i)<<PAGE_SHIFT));\r
+ }\r
+ \r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], DstStart, DstMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map dst memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base); \r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize) << PAGE_SHIFT);\r
+ \r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+\r
+static int rga_mmu_info_line_point_drawing_mode(struct rga_reg *reg, struct rga_req *req)\r
+{\r
+ int DstMemSize, CMDMemSize;\r
+ uint32_t DstStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base;\r
+ int ret;\r
+\r
+ /* cal dst buf mmu info */ \r
+ DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+ \r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart+i)<<PAGE_SHIFT));\r
+ }\r
+ \r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], DstStart, DstMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map dst memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base); \r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize) << PAGE_SHIFT);\r
+ \r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+static int rga_mmu_info_blur_sharp_filter_mode(struct rga_reg *reg, struct rga_req *req)\r
+{\r
+ int SrcMemSize, DstMemSize, CMDMemSize;\r
+ uint32_t SrcStart, DstStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base;\r
+ int ret;\r
+\r
+ /* cal src buf mmu info */ \r
+ SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,\r
+ req->src.format, req->src.vir_w, req->src.vir_h,\r
+ &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal dst buf mmu info */ \r
+ DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal cmd buf mmu info */\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+ \r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i)<< PAGE_SHIFT));\r
+ }\r
+ \r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map dst memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base);\r
+ \r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+\r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);\r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+static int rga_mmu_info_pre_scale_mode(struct rga_reg *reg, struct rga_req *req)\r
+{\r
+ int SrcMemSize, DstMemSize, CMDMemSize;\r
+ uint32_t SrcStart, DstStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base, *MMU_p;\r
+ int ret;\r
+\r
+ /* cal src buf mmu info */ \r
+ SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,\r
+ req->src.format, req->src.vir_w, req->src.vir_h,\r
+ &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal dst buf mmu info */ \r
+ DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
+ req->dst.format, req->dst.vir_w, req->dst.vir_h,\r
+ &DstStart);\r
+ if(DstMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal cmd buf mmu info */\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* \r
+ * Allocate MMU Index mem\r
+ * This mem release in run_to_done fun \r
+ */\r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));\r
+ }\r
+\r
+\r
+ /* map src pages */\r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ \r
+ if(req->dst.yrgb_addr >= 0xc0000000) \r
+ { \r
+ /* kernel space */\r
+ MMU_p = MMU_Base + CMDMemSize + SrcMemSize;\r
+ for(i=0; i<DstMemSize; i++) \r
+ {\r
+ MMU_p[i] = virt_to_phys((uint32_t *)((DstStart + i)<< PAGE_SHIFT)); \r
+ }\r
+ }\r
+ else \r
+ {\r
+ /* user space */\r
+ ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);\r
+ if (ret < 0) \r
+ {\r
+ pr_err("rga map dst memory failed");\r
+ return -EINVAL;\r
+ } \r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base);\r
+ \r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+ req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
+\r
+ req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);\r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+\r
+static int rga_mmu_info_update_palette_table_mode(struct rga_reg *reg, struct rga_req *req)\r
+{\r
+ int SrcMemSize, DstMemSize, CMDMemSize;\r
+ uint32_t SrcStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base;\r
+ int ret;\r
+\r
+ /* cal src buf mmu info */ \r
+ SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, req->src.vir_w * req->src.vir_h, &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal cmd buf mmu info */\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+ \r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));\r
+ }\r
+ \r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base);\r
+ \r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT); \r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ } \r
+\r
+ return 0;\r
+}\r
+\r
+static int rga_mmu_info_update_patten_buff_mode(struct rga_reg *reg, struct rga_req *req)\r
+{\r
+ int SrcMemSize, DstMemSize, CMDMemSize;\r
+ uint32_t SrcStart, CMDStart;\r
+ struct page **pages = NULL;\r
+ uint32_t i;\r
+ uint32_t AllSize;\r
+ uint32_t *MMU_Base;\r
+ int ret;\r
+\r
+ /* cal src buf mmu info */ \r
+ SrcMemSize = rga_mem_size_cal(req->pat.yrgb_addr, req->pat.vir_w * req->pat.vir_h * 4, &SrcStart);\r
+ if(SrcMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ /* cal cmd buf mmu info */\r
+ CMDMemSize = rga_mem_size_cal((uint32_t)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);\r
+ if(CMDMemSize == 0) {\r
+ return -EINVAL; \r
+ }\r
+\r
+ AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
+ \r
+ pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc pages mem failed");\r
+ return -EINVAL; \r
+ }\r
+ \r
+ MMU_Base = (uint32_t *)kmalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);\r
+ if(pages == NULL) {\r
+ pr_err("RGA MMU malloc MMU_Base point failed");\r
+ return -EINVAL; \r
+ }\r
+\r
+ for(i=0; i<CMDMemSize; i++) {\r
+ MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));\r
+ }\r
+ \r
+ ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);\r
+ if (ret < 0) {\r
+ pr_err("rga map src memory failed");\r
+ return -EINVAL;\r
+ }\r
+\r
+ /* zsq \r
+ * change the buf address in req struct\r
+ * for the reason of lie to MMU \r
+ */\r
+ req->mmu_info.base_addr = virt_to_phys(MMU_Base);\r
+ \r
+ req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT); \r
+ \r
+ /*record the malloc buf for the cmd end to release*/\r
+ reg->MMU_base = MMU_Base;\r
+\r
+ if (pages != NULL) {\r
+ /* Free the page table */\r
+ kfree(pages);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req)\r
+{ \r
+ int ret;\r
+ \r
+ switch (req->render_mode) {\r
+ case bitblt_mode : \r
+ ret = rga_mmu_info_BitBlt_mode(reg, req);\r
+ break;\r
+ case color_palette_mode :\r
+ ret = rga_mmu_info_color_palette_mode(reg, req);\r
+ break;\r
+ case color_fill_mode :\r
+ ret = rga_mmu_info_color_fill_mode(reg, req);\r
+ break;\r
+ case line_point_drawing_mode :\r
+ ret = rga_mmu_info_line_point_drawing_mode(reg, req);\r
+ break;\r
+ case blur_sharp_filter_mode :\r
+ ret = rga_mmu_info_blur_sharp_filter_mode(reg, req);\r
+ break;\r
+ case pre_scaling_mode :\r
+ ret = rga_mmu_info_pre_scale_mode(reg, req);\r
+ break;\r
+ case update_palette_table_mode :\r
+ ret = rga_mmu_info_update_palette_table_mode(reg, req);\r
+ break;\r
+ case update_patten_buff_mode :\r
+ ret = rga_mmu_info_update_patten_buff_mode(reg, req);\r
+ break;\r
+ default :\r
+ ret = -1;\r
+ break;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
--- /dev/null
+#ifndef __RGA_MMU_INFO_H__\r
+#define __RGA_MMU_INFO_H__\r
+\r
+#include "rga.h"\r
+\r
+#ifndef MIN\r
+#define MIN(X, Y) ((X)<(Y)?(X):(Y))\r
+#endif\r
+\r
+#ifndef MAX\r
+#define MAX(X, Y) ((X)>(Y)?(X):(Y))\r
+#endif\r
+\r
+\r
+int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req);\r
+\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+\r
+//#include <linux/kernel.h>\r
+#include <linux/memory.h>\r
+#include "rga_reg_info.h"\r
+#include "rga_rop.h"\r
+#include "rga.h"\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_pixel_width_init \r
+Description: \r
+ select pixel_width form data format \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+unsigned char\r
+RGA_pixel_width_init(unsigned int format)\r
+{\r
+ unsigned char pixel_width;\r
+\r
+ pixel_width = 0;\r
+\r
+ switch(format)\r
+ {\r
+ /* RGB FORMAT */\r
+ case RK_FORMAT_RGBA_8888 : pixel_width = 4; break;\r
+ case RK_FORMAT_RGBX_8888 : pixel_width = 4; break;\r
+ case RK_FORMAT_RGB_888 : pixel_width = 3; break;\r
+ case RK_FORMAT_BGRA_8888 : pixel_width = 4; break;\r
+ case RK_FORMAT_RGB_565 : pixel_width = 2; break;\r
+ case RK_FORMAT_RGBA_5551 : pixel_width = 2; break;\r
+ case RK_FORMAT_RGBA_4444 : pixel_width = 2; break;\r
+ case RK_FORMAT_BGR_888 : pixel_width = 3; break;\r
+\r
+ /* YUV FORMAT */ \r
+ case RK_FORMAT_YCbCr_422_SP : pixel_width = 1; break;\r
+ case RK_FORMAT_YCbCr_422_P : pixel_width = 1; break;\r
+ case RK_FORMAT_YCbCr_420_SP : pixel_width = 1; break;\r
+ case RK_FORMAT_YCbCr_420_P : pixel_width = 1; break;\r
+ case RK_FORMAT_YCrCb_422_SP : pixel_width = 1; break;\r
+ case RK_FORMAT_YCrCb_422_P : pixel_width = 1; break;\r
+ case RK_FORMAT_YCrCb_420_SP : pixel_width = 1; break;\r
+ case RK_FORMAT_YCrCb_420_P : pixel_width = 1; break;\r
+ //case default : pixel_width = 0; break;\r
+ }\r
+\r
+ return pixel_width;\r
+}\r
+\r
+/************************************************************* \r
+Func: \r
+ dst_ctrl_cal \r
+Description: \r
+ calculate dst act window position / width / height \r
+ and set the tile struct \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+void\r
+dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile)\r
+{\r
+ u32 width = msg->dst.act_w;\r
+ u32 height = msg->dst.act_h;\r
+ s32 xoff = msg->dst.x_offset;\r
+ s32 yoff = msg->dst.y_offset;\r
+\r
+ s32 x0, y0, x1, y1, x2, y2;\r
+ s32 x00,y00,x10,y10,x20,y20;\r
+ s32 xx, xy, yx, yy;\r
+ s32 pos[8];\r
+\r
+ s32 xmax, xmin, ymax, ymin;\r
+\r
+ s32 sina = msg->sina; /* 16.16 */\r
+ s32 cosa = msg->cosa; /* 16.16 */\r
+\r
+ xmax = xmin = ymax = ymin = 0;\r
+\r
+ if((msg->rotate_mode == 0)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))\r
+ {\r
+ pos[0] = xoff;\r
+ pos[1] = yoff;\r
+ \r
+ pos[2] = xoff;\r
+ pos[3] = yoff + height - 1;\r
+ \r
+ pos[4] = xoff + width - 1;\r
+ pos[5] = yoff + height - 1;\r
+\r
+ pos[6] = xoff + width - 1;\r
+ pos[7] = yoff;\r
+\r
+ xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);\r
+ xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);\r
+ \r
+ ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);\r
+ ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin); \r
+ }\r
+ else if(msg->rotate_mode == 1)\r
+ {\r
+ if((sina == 0) || (cosa == 0))\r
+ { \r
+ if((sina == 0) && (cosa == -65536))\r
+ {\r
+ /* 180 */\r
+ pos[0] = xoff - width + 1;\r
+ pos[1] = yoff - height + 1;\r
+\r
+ pos[2] = xoff - width + 1;\r
+ pos[3] = yoff;\r
+\r
+ pos[4] = xoff;\r
+ pos[5] = yoff;\r
+\r
+ pos[6] = xoff;\r
+ pos[7] = yoff - height + 1;\r
+ }\r
+ else if((cosa == 0)&&(sina == 65536))\r
+ {\r
+ /* 90 */\r
+ pos[0] = xoff - height + 1;\r
+ pos[1] = yoff;\r
+\r
+ pos[2] = xoff - height + 1;\r
+ pos[3] = yoff + width - 1;\r
+\r
+ pos[4] = xoff;\r
+ pos[5] = yoff + width - 1;\r
+\r
+ pos[6] = xoff;\r
+ pos[7] = yoff;\r
+ }\r
+ else if((cosa == 0)&&(sina == -65536))\r
+ {\r
+ /* 270 */\r
+ pos[0] = xoff;\r
+ pos[1] = yoff - width + 1;\r
+\r
+ pos[2] = xoff;\r
+ pos[3] = yoff;\r
+\r
+ pos[4] = xoff + height - 1;\r
+ pos[5] = yoff;\r
+\r
+ pos[6] = xoff + height - 1;\r
+ pos[7] = yoff - width + 1; \r
+ }\r
+ else\r
+ {\r
+ /* 0 */\r
+ pos[0] = xoff;\r
+ pos[1] = yoff;\r
+\r
+ pos[2] = xoff;\r
+ pos[3] = yoff + height - 1;\r
+\r
+ pos[4] = xoff + width - 1;\r
+ pos[5] = yoff + height - 1;\r
+\r
+ pos[6] = xoff + width - 1;\r
+ pos[7] = yoff;\r
+ }\r
+\r
+ xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);\r
+ xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);\r
+ \r
+ ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);\r
+ ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);\r
+ } \r
+ else\r
+ {\r
+ xx = msg->cosa;\r
+ xy = msg->sina;\r
+ yx = xy;\r
+ yy = xx;\r
+\r
+ x0 = width + xoff;\r
+ y0 = yoff;\r
+\r
+ x1 = xoff;\r
+ y1 = height + yoff;\r
+\r
+ x2 = width + xoff;\r
+ y2 = height + yoff;\r
+ \r
+ pos[0] = xoff;\r
+ pos[1] = yoff;\r
+\r
+ pos[2] = x00 = (((x0 - xoff)*xx - (y0 - yoff)*xy)>>16) + xoff;\r
+ pos[3] = y00 = (((x0 - xoff)*yx + (y0 - yoff)*yy)>>16) + yoff;\r
+\r
+ pos[4] = x10 = (((x1 - xoff)*xx - (y1 - yoff)*xy)>>16) + xoff;\r
+ pos[5] = y10 = (((x1 - xoff)*yx + (y1 - yoff)*yy)>>16) + yoff;\r
+\r
+ pos[6] = x20 = (((x2 - xoff)*xx - (y2 - yoff)*xy)>>16) + xoff;\r
+ pos[7] = y20 = (((x2 - xoff)*yx + (y2 - yoff)*yy)>>16) + yoff;\r
+\r
+ xmax = MAX(MAX(MAX(x00, xoff), x10), x20) + 2;\r
+ xmin = MIN(MIN(MIN(x00, xoff), x10), x20) - 1;\r
+\r
+ ymax = MAX(MAX(MAX(y00, yoff), y10), y20) + 2;\r
+ ymin = MIN(MIN(MIN(y00, yoff), y10), y20) - 1;\r
+\r
+ xmax = MIN(xmax, msg->clip.xmax);\r
+ xmin = MAX(xmin, msg->clip.xmin);\r
+\r
+ ymax = MIN(ymax, msg->clip.ymax);\r
+ ymin = MAX(ymin, msg->clip.ymin);\r
+ }\r
+ } \r
+ \r
+ if ((xmax < xmin) || (ymax < ymin)) { \r
+ xmin = xmax;\r
+ ymin = ymax;\r
+ } \r
+ \r
+ if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) { \r
+ xmin = xmax = ymin = ymax = 0;\r
+ }\r
+ \r
+ tile->dst_ctrl.w = (xmax - xmin);\r
+ tile->dst_ctrl.h = (ymax - ymin);\r
+ tile->dst_ctrl.x_off = xmin;\r
+ tile->dst_ctrl.y_off = ymin;\r
+\r
+ tile->tile_x_num = (xmax - xmin + 1 + 7)>>3;\r
+ tile->tile_y_num = (ymax - ymin + 1 + 7)>>3;\r
+\r
+ tile->dst_x_tmp = xmin - msg->dst.x_offset;\r
+ tile->dst_y_tmp = ymin - msg->dst.y_offset;\r
+}\r
+\r
+/************************************************************* \r
+Func: \r
+ src_tile_info_cal \r
+Description: \r
+ calculate src remap window position / width / height \r
+ and set the tile struct \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+void\r
+src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile)\r
+{\r
+ s32 x0, x1, x2, x3, y0, y1, y2, y3; \r
+ \r
+ int64_t xx, xy, yx, yy;\r
+\r
+ int64_t pos[8];\r
+ int64_t epos[8];\r
+\r
+ int64_t x_dx, x_dy, y_dx, y_dy;\r
+ int64_t x_temp_start, y_temp_start;\r
+ int64_t xmax, xmin, ymax, ymin;\r
+\r
+ int64_t t_xoff, t_yoff;\r
+\r
+ xx = tile->matrix[0]; /* 32.32 */\r
+ xy = tile->matrix[1]; /* 32.32 */\r
+ yx = tile->matrix[2]; /* 32.32 */\r
+ yy = tile->matrix[3]; /* 32.32 */\r
+\r
+ if(msg->rotate_mode == 1)\r
+ { \r
+ x0 = tile->dst_x_tmp;\r
+ y0 = tile->dst_y_tmp;\r
+ \r
+ x1 = x0;\r
+ y1 = y0 + 8;\r
+\r
+ x2 = x0 + 8;\r
+ y2 = y0 + 8;\r
+\r
+ x3 = x0 + 8;\r
+ y3 = y0;\r
+ \r
+ pos[0] = (x0*xx + y0*yx); \r
+ pos[1] = (x0*xy + y0*yy);\r
+\r
+ pos[2] = (x1*xx + y1*yx);\r
+ pos[3] = (x1*xy + y1*yy);\r
+\r
+ pos[4] = (x2*xx + y2*yx);\r
+ pos[5] = (x2*xy + y2*yy);\r
+\r
+ pos[6] = (x3*xx + y3*yx);\r
+ pos[7] = (x3*xy + y3*yy);\r
+\r
+ y1 = y0 + 7;\r
+ x2 = x0 + 7;\r
+ y2 = y0 + 7;\r
+ x3 = x0 + 7;\r
+\r
+ epos[0] = pos[0];\r
+ epos[1] = pos[1];\r
+\r
+ epos[2] = (x1*xx + y1*yx);\r
+ epos[3] = (x1*xy + y1*yy);\r
+\r
+ epos[4] = (x2*xx + y2*yx);\r
+ epos[5] = (x2*xy + y2*yy);\r
+\r
+ epos[6] = (x3*xx + y3*yx);\r
+ epos[7] = (x3*xy + y3*yy);\r
+\r
+ x_dx = pos[6] - pos[0];\r
+ x_dy = pos[7] - pos[1];\r
+\r
+ y_dx = pos[2] - pos[0];\r
+ y_dy = pos[3] - pos[1];\r
+\r
+ tile->x_dx = (s32)(x_dx >> 22 ); \r
+ tile->x_dy = (s32)(x_dy >> 22 ); \r
+ tile->y_dx = (s32)(y_dx >> 22 ); \r
+ tile->y_dy = (s32)(y_dy >> 22 ); \r
+ \r
+ x_temp_start = x0*xx + y0*yx;\r
+ y_temp_start = x0*xy + y0*yy;\r
+ \r
+ xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6])); \r
+ xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6])); \r
+\r
+ ymax = (MAX(MAX(MAX(epos[1], epos[3]), epos[5]), epos[7]));\r
+ ymin = (MIN(MIN(MIN(epos[1], epos[3]), epos[5]), epos[7]));\r
+\r
+ t_xoff = (x_temp_start - xmin)>>18;\r
+ t_yoff = (y_temp_start - ymin)>>18;\r
+ \r
+ tile->tile_xoff = (s32)t_xoff;\r
+ tile->tile_yoff = (s32)t_yoff;\r
+ \r
+ tile->tile_w = (u16)((xmax - xmin)>>21); //.11\r
+ tile->tile_h = (u16)((ymax - ymin)>>21); //.11\r
+\r
+ tile->tile_start_x_coor = (s16)(xmin>>29); //.3\r
+ tile->tile_start_y_coor = (s16)(ymin>>29); //.3 \r
+ }\r
+ else if (msg->rotate_mode == 2)\r
+ {\r
+ tile->x_dx = (s32)((8*xx)>>22);\r
+ tile->x_dy = 0;\r
+ tile->y_dx = 0;\r
+ tile->y_dy = (s32)((8*yy)>>22);\r
+ \r
+ tile->tile_w = ABS((s32)((7*xx)>>21));\r
+ tile->tile_h = ABS((s32)((7*yy)>>21));\r
+\r
+ tile->tile_xoff = ABS((s32)((7*xx)>>18));\r
+ tile->tile_yoff = 0;\r
+\r
+ tile->tile_start_x_coor = (((msg->src.act_w - 1)<<11) - (tile->tile_w))>>8;\r
+ tile->tile_start_y_coor = 0; \r
+ }\r
+ else if (msg->rotate_mode == 3)\r
+ {\r
+ tile->x_dx = (s32)((8*xx)>>22);\r
+ tile->x_dy = 0;\r
+ tile->y_dx = 0;\r
+ tile->y_dy = (s32)((8*yy)>>22);\r
+ \r
+ tile->tile_w = ABS((s32)((7*xx)>>21));\r
+ tile->tile_h = ABS((s32)((7*yy)>>21));\r
+\r
+ tile->tile_xoff = 0;\r
+ tile->tile_yoff = ABS((s32)((7*yy)>>18));\r
+\r
+ tile->tile_start_x_coor = 0;\r
+ tile->tile_start_y_coor = (((msg->src.act_h - 1)<<11) - (tile->tile_h))>>8;\r
+ } \r
+\r
+ if ((msg->scale_mode == 2)||(msg->alpha_rop_flag >> 7))\r
+ {\r
+ tile->tile_start_x_coor -= (1<<3);\r
+ tile->tile_start_y_coor -= (1<<3);\r
+ tile->tile_w += (2 << 11);\r
+ tile->tile_h += (2 << 11);\r
+ tile->tile_xoff += (1<<14);\r
+ tile->tile_yoff += (1<<14);\r
+ }\r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_mode_ctrl \r
+Description: \r
+ fill mode ctrl reg info \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+void \r
+RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_MODE_CTL;\r
+ u32 reg = 0;\r
+ \r
+ u8 src_rgb_pack = 0;\r
+ u8 src_format = 0;\r
+ u8 src_rb_swp = 0;\r
+ u8 src_a_swp = 0;\r
+ u8 src_cbcr_swp = 0;\r
+\r
+ u8 dst_rgb_pack = 0;\r
+ u8 dst_format = 0;\r
+ u8 dst_rb_swp = 0;\r
+ u8 dst_a_swp = 0;\r
+ \r
+ bRGA_MODE_CTL = (u32 *)(base + RGA_MODE_CTRL_OFFSET);\r
+ \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode))); \r
+\r
+ /* src info set */\r
+ \r
+ if (msg->render_mode == color_palette_mode || msg->render_mode == update_palette_table_mode)\r
+ {\r
+ src_format = 0x10 | (msg->palette_mode & 3);\r
+ }\r
+ else\r
+ {\r
+ switch (msg->src.format)\r
+ {\r
+ case RK_FORMAT_RGBA_8888 : src_format = 0x0; break; \r
+ case RK_FORMAT_RGBA_4444 : src_format = 0x3; break; \r
+ case RK_FORMAT_RGBA_5551 : src_format = 0x2; break; \r
+ case RK_FORMAT_BGRA_8888 : src_format = 0x0; src_rb_swp = 0x1; break; \r
+ case RK_FORMAT_RGBX_8888 : src_format = 0x0; break; \r
+ case RK_FORMAT_RGB_565 : src_format = 0x1; break;\r
+ case RK_FORMAT_RGB_888 : src_format = 0x0; src_rgb_pack = 1; break;\r
+ case RK_FORMAT_BGR_888 : src_format = 0x0; src_rgb_pack = 1; src_rb_swp = 1; break;\r
+ \r
+ case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break; \r
+ case RK_FORMAT_YCbCr_422_P : src_format = 0x5; break; \r
+ case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break; \r
+ case RK_FORMAT_YCbCr_420_P : src_format = 0x7; break;\r
+\r
+ case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break; \r
+ case RK_FORMAT_YCrCb_422_P : src_format = 0x5; src_cbcr_swp = 1; break; \r
+ case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break; \r
+ case RK_FORMAT_YCrCb_420_P : src_format = 0x7; src_cbcr_swp = 1; break;\r
+ } \r
+ }\r
+\r
+ src_a_swp = msg->src.alpha_swap & 1;\r
+\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK)) | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack))); \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SRC_FORMAT)) | (s_RGA_MODE_CTRL_SRC_FORMAT(src_format)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RB_SWAP)) | (s_RGA_MODE_CTRL_SRC_RB_SWAP(src_rb_swp)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SRC_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(src_a_swp)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE )) | (s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE (src_cbcr_swp)));\r
+ \r
+ \r
+ /* YUV2RGB MODE */ \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_YUV2RGB_CON_MODE)) | (s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(msg->yuv2rgb_mode)));\r
+\r
+ /* ROTATE MODE */\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_ROTATE_MODE)) | (s_RGA_MODE_CTRL_ROTATE_MODE(msg->rotate_mode)));\r
+\r
+ /* SCALE MODE */\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SCALE_MODE)) | (s_RGA_MODE_CTRL_SCALE_MODE(msg->scale_mode)));\r
+\r
+ /* COLOR FILL MODE */\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_PAT_SEL)) | (s_RGA_MODE_CTRL_PAT_SEL(msg->color_fill_mode)));\r
+\r
+ \r
+ if ((msg->render_mode == update_palette_table_mode)||(msg->render_mode == update_patten_buff_mode))\r
+ {\r
+ dst_format = msg->pat.format;\r
+ }\r
+ else\r
+ {\r
+ dst_format = (u8)msg->dst.format;\r
+ }\r
+ \r
+ /* dst info set */ \r
+ switch (dst_format)\r
+ {\r
+ case RK_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; break;\r
+ case RK_FORMAT_RGBA_4444 : dst_format = 0x3; break;\r
+ case RK_FORMAT_RGBA_5551 : dst_format = 0x2; break;\r
+ case RK_FORMAT_RGBA_8888 : dst_format = 0x0; break;\r
+ case RK_FORMAT_RGB_565 : dst_format = 0x1; break;\r
+ case RK_FORMAT_RGB_888 : dst_format = 0x0; dst_rgb_pack = 0x1; break;\r
+ case RK_FORMAT_BGR_888 : dst_format = 0x0; dst_rgb_pack = 0x1; dst_rb_swp = 1; break;\r
+ case RK_FORMAT_RGBX_8888 : dst_format = 0x0; break;\r
+ }\r
+\r
+ dst_a_swp = msg->dst.alpha_swap & 1;\r
+ \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT)) | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format))); \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK)) | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP)) | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_CMD_INT_ENABLE)) | (s_RGA_MODE_CTRL_CMD_INT_ENABLE(msg->CMD_fin_int_enable))); \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE)) | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4)));\r
+ reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5)));\r
+\r
+ *bRGA_MODE_CTL = reg;\r
+ \r
+}\r
+\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_src \r
+Description: \r
+ fill src relate reg info \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+void\r
+RGA_set_src(u8 *base, const struct rga_req *msg)\r
+{ \r
+ u32 *bRGA_SRC_VIR_INFO;\r
+ u32 *bRGA_SRC_ACT_INFO;\r
+ u32 *bRGA_SRC_Y_MST;\r
+ u32 *bRGA_SRC_CB_MST;\r
+ u32 *bRGA_SRC_CR_MST;\r
+\r
+ s16 x_off, y_off, stride;\r
+ s16 uv_x_off, uv_y_off, uv_stride;\r
+ u32 pixel_width;\r
+\r
+ uv_x_off = uv_y_off = uv_stride = 0;\r
+ \r
+ bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);\r
+ bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);\r
+ bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);\r
+ bRGA_SRC_VIR_INFO = (u32 *)(base + RGA_SRC_VIR_INFO_OFFSET);\r
+ bRGA_SRC_ACT_INFO = (u32 *)(base + RGA_SRC_ACT_INFO_OFFSET);\r
+\r
+ x_off = msg->src.x_offset;\r
+ y_off = msg->src.y_offset;\r
+\r
+ pixel_width = RGA_pixel_width_init(msg->src.format);\r
+ \r
+ stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);\r
+\r
+ switch(msg->src.format)\r
+ {\r
+ case RK_FORMAT_YCbCr_422_SP : \r
+ uv_stride = stride; \r
+ uv_x_off = x_off; \r
+ uv_y_off = y_off; \r
+ break;\r
+ case RK_FORMAT_YCbCr_422_P :\r
+ uv_stride = stride >> 1;\r
+ uv_x_off = x_off >> 1;\r
+ uv_y_off = y_off;\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_SP :\r
+ uv_stride = stride;\r
+ uv_x_off = x_off;\r
+ uv_y_off = y_off >> 1;\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_P :\r
+ uv_stride = stride >> 1;\r
+ uv_x_off = x_off >> 1;\r
+ uv_y_off = y_off >> 1;\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_SP :\r
+ uv_stride = stride;\r
+ uv_x_off = x_off;\r
+ uv_y_off = y_off;\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_P :\r
+ uv_stride = stride >> 1;\r
+ uv_x_off = x_off >> 1;\r
+ uv_y_off = y_off;\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_SP :\r
+ uv_stride = stride;\r
+ uv_x_off = x_off;\r
+ uv_y_off = y_off >> 1;\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_P :\r
+ uv_stride = stride >> 1;\r
+ uv_x_off = x_off >> 1;\r
+ uv_y_off = y_off >> 1;\r
+ break; \r
+ } \r
+\r
+\r
+ /* src addr set */ \r
+ *bRGA_SRC_Y_MST = msg->src.yrgb_addr + (y_off * stride) + (x_off * pixel_width);\r
+ *bRGA_SRC_CB_MST = msg->src.uv_addr + uv_y_off * uv_stride + uv_x_off;\r
+ *bRGA_SRC_CR_MST = msg->src.v_addr + uv_y_off * uv_stride + uv_x_off;\r
+\r
+ if((msg->alpha_rop_flag >> 1) & 1)\r
+ *bRGA_SRC_CB_MST = (u32)msg->rop_mask_addr;\r
+\r
+ if (msg->render_mode == color_palette_mode)\r
+ {\r
+ u8 shift;\r
+ u16 sw, byte_num;\r
+ shift = 3 - (msg->palette_mode & 3);\r
+ sw = msg->src.vir_w;\r
+\r
+ byte_num = sw >> shift;\r
+ stride = (byte_num + 3) & (~3);\r
+ } \r
+\r
+ /* src act window / vir window set */ \r
+ *bRGA_SRC_VIR_INFO = ((stride >> 2) | (msg->src.vir_h)<<16);\r
+ *bRGA_SRC_ACT_INFO = ((msg->src.act_w-1) | (msg->src.act_h-1)<<16);\r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_dst \r
+Description: \r
+ fill dst relate reg info \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+s32 RGA_set_dst(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_DST_MST;\r
+ u32 *bRGA_DST_VIR_INFO;\r
+ u32 *bRGA_DST_CTR_INFO;\r
+ u32 *bRGA_PRESCL_CB_MST;\r
+ u32 *bRGA_PRESCL_CR_MST;\r
+ u32 reg = 0;\r
+\r
+ u8 pw;\r
+ s16 x_off = msg->dst.x_offset;\r
+ s16 y_off = msg->dst.y_offset;\r
+ u16 stride, rop_mask_stride;\r
+\r
+ bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);\r
+ bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);\r
+ bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);\r
+ bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET);\r
+ bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET);\r
+\r
+ pw = RGA_pixel_width_init(msg->dst.format);\r
+\r
+ stride = (msg->dst.vir_w * pw + 3) & (~3);\r
+\r
+ *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);\r
+\r
+ if (msg->render_mode == pre_scaling_mode)\r
+ {\r
+ switch(msg->dst.format)\r
+ {\r
+ case RK_FORMAT_YCbCr_422_SP : \r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
+ break;\r
+ case RK_FORMAT_YCbCr_422_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_SP :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_SP :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_SP :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_P :\r
+ *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);\r
+ break; \r
+ } \r
+ }\r
+\r
+ rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21\r
+ \r
+ reg = (stride >> 2) & 0xffff;\r
+ reg = reg | ((rop_mask_stride>>2) << 16); \r
+\r
+ if (msg->render_mode == line_point_drawing_mode)\r
+ {\r
+ reg &= 0xffff;\r
+ reg = reg | (msg->dst.vir_h << 16); \r
+ }\r
+\r
+ *bRGA_DST_VIR_INFO = reg;\r
+ *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);\r
+\r
+ return 0; \r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_alpha_rop \r
+Description: \r
+ fill alpha rop some relate reg bit \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+void\r
+RGA_set_alpha_rop(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_ALPHA_CON;\r
+ u32 *bRGA_ROP_CON0;\r
+ u32 *bRGA_ROP_CON1;\r
+ u32 reg = 0;\r
+ u32 rop_con0, rop_con1;\r
+ \r
+ u8 rop_mode = (msg->alpha_rop_mode) & 3;\r
+ u8 alpha_mode = msg->alpha_rop_mode & 3;\r
+\r
+ rop_con0 = rop_con1 = 0;\r
+ \r
+ bRGA_ALPHA_CON = (u32 *)(base + RGA_ALPHA_CON_OFFSET);\r
+\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_ENABLE) )| (s_RGA_ALPHA_CON_ENABLE(msg->alpha_rop_flag & 1)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_A_OR_R_SEL)) | (s_RGA_ALPHA_CON_A_OR_R_SEL((msg->alpha_rop_flag >> 1) & 1)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_ALPHA_MODE)) | (s_RGA_ALPHA_CON_ALPHA_MODE(alpha_mode)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_PD_MODE)) | (s_RGA_ALPHA_CON_PD_MODE(msg->PD_mode)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_SET_CONSTANT_VALUE)) | (s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(msg->alpha_global_value)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_PD_M_SEL)) | (s_RGA_ALPHA_CON_PD_M_SEL(msg->alpha_rop_flag >> 3)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_FADING_ENABLE)) | (s_RGA_ALPHA_CON_FADING_ENABLE(msg->alpha_rop_flag >> 2)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_ROP_MODE_SEL)) | (s_RGA_ALPHA_CON_ROP_MODE_SEL(rop_mode)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_CAL_MODE_SEL)) | (s_RGA_ALPHA_CON_CAL_MODE_SEL(msg->alpha_rop_flag >> 4)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_DITHER_ENABLE)) | (s_RGA_ALPHA_CON_DITHER_ENABLE(msg->alpha_rop_flag >> 5)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_GRADIENT_CAL_MODE)) | (s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(msg->alpha_rop_flag >> 6)));\r
+ reg = ((reg & (~m_RGA_ALPHA_CON_AA_SEL)) | (s_RGA_ALPHA_CON_AA_SEL(msg->alpha_rop_flag >> 7)));\r
+ \r
+ *bRGA_ALPHA_CON = reg;\r
+\r
+ if(rop_mode == 0) { \r
+ rop_con0 = ROP3_code[(msg->rop_code & 0xff)];\r
+ }\r
+ else if(rop_mode == 1) {\r
+ rop_con0 = ROP3_code[(msg->rop_code & 0xff)];\r
+ }\r
+ else if(rop_mode == 2) {\r
+ rop_con0 = ROP3_code[(msg->rop_code & 0xff)];\r
+ rop_con1 = ROP3_code[(msg->rop_code & 0xff00)>>8];\r
+ }\r
+ \r
+ bRGA_ROP_CON0 = (u32 *)(base + RGA_ROP_CON0_OFFSET);\r
+ bRGA_ROP_CON1 = (u32 *)(base + RGA_ROP_CON1_OFFSET);\r
+\r
+ *bRGA_ROP_CON0 = (u32)rop_con0;\r
+ *bRGA_ROP_CON1 = (u32)rop_con1; \r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_color \r
+Description: \r
+ fill color some relate reg bit\r
+ bg_color/fg_color\r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+void\r
+RGA_set_color(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_SRC_TR_COLOR0;\r
+ u32 *bRGA_SRC_TR_COLOR1;\r
+ u32 *bRGA_SRC_BG_COLOR;\r
+ u32 *bRGA_SRC_FG_COLOR;\r
+ \r
+ \r
+ bRGA_SRC_BG_COLOR = (u32 *)(base + RGA_SRC_BG_COLOR_OFFSET);\r
+ bRGA_SRC_FG_COLOR = (u32 *)(base + RGA_SRC_FG_COLOR_OFFSET);\r
+ \r
+ *bRGA_SRC_BG_COLOR = msg->bg_color; /* 1bpp 0 */\r
+ *bRGA_SRC_FG_COLOR = msg->fg_color; /* 1bpp 1 */\r
+ \r
+ bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET); \r
+ bRGA_SRC_TR_COLOR1 = (u32 *)(base + RGA_SRC_TR_COLOR1_OFFSET);\r
+\r
+ *bRGA_SRC_TR_COLOR0 = msg->color_key_min;\r
+ *bRGA_SRC_TR_COLOR1 = msg->color_key_max;\r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_fading \r
+Description: \r
+ fill fading some relate reg bit\r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+s32\r
+RGA_set_fading(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_FADING_CON;\r
+ u8 r, g, b;\r
+ u32 reg = 0;\r
+\r
+ bRGA_FADING_CON = (u32 *)(base + RGA_FADING_CON_OFFSET);\r
+\r
+ b = msg->fading.b;\r
+ g = msg->fading.g;\r
+ r = msg->fading.r;\r
+\r
+ reg = (r<<8) | (g<<16) | (b<<24) | reg;\r
+\r
+ *bRGA_FADING_CON = reg; \r
+ \r
+ return 0;\r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_pat \r
+Description: \r
+ fill patten some relate reg bit\r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+s32\r
+RGA_set_pat(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_PAT_CON;\r
+ u32 *bRGA_PAT_START_POINT;\r
+ u32 reg = 0;\r
+\r
+ bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);\r
+\r
+ bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);\r
+ \r
+ *bRGA_PAT_START_POINT = (msg->pat.act_w * msg->pat.y_offset) + msg->pat.x_offset;\r
+\r
+ reg = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);\r
+ *bRGA_PAT_CON = reg;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_bitblt_reg_info \r
+Description: \r
+ fill bitblt mode relate ren info\r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+void \r
+RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile)\r
+{\r
+ u32 *bRGA_SRC_Y_MST;\r
+ u32 *bRGA_SRC_CB_MST;\r
+ u32 *bRGA_SRC_CR_MST;\r
+ u32 *bRGA_SRC_X_PARA;\r
+ u32 *bRGA_SRC_Y_PARA;\r
+ u32 *bRGA_SRC_TILE_XINFO;\r
+ u32 *bRGA_SRC_TILE_YINFO;\r
+ u32 *bRGA_SRC_TILE_H_INCR;\r
+ u32 *bRGA_SRC_TILE_V_INCR;\r
+ u32 *bRGA_SRC_TILE_OFFSETX;\r
+ u32 *bRGA_SRC_TILE_OFFSETY;\r
+\r
+ u32 *bRGA_DST_MST;\r
+ u32 *bRGA_DST_CTR_INFO;\r
+\r
+ s32 m0, m1, m2, m3;\r
+ s32 pos[8];\r
+ //s32 x_dx, x_dy, y_dx, y_dy;\r
+ s32 xmin, xmax, ymin, ymax;\r
+ s32 xp, yp;\r
+ u32 y_addr, u_addr, v_addr;\r
+ u32 pixel_width, stride;\r
+\r
+ u_addr = v_addr = 0;\r
+\r
+ /* src info */\r
+\r
+ bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);\r
+ bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);\r
+ bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);\r
+\r
+ bRGA_SRC_X_PARA = (u32 *)(base + RGA_SRC_X_PARA_OFFSET);\r
+ bRGA_SRC_Y_PARA = (u32 *)(base + RGA_SRC_Y_PARA_OFFSET);\r
+ \r
+ bRGA_SRC_TILE_XINFO = (u32 *)(base + RGA_SRC_TILE_XINFO_OFFSET);\r
+ bRGA_SRC_TILE_YINFO = (u32 *)(base + RGA_SRC_TILE_YINFO_OFFSET);\r
+ bRGA_SRC_TILE_H_INCR = (u32 *)(base + RGA_SRC_TILE_H_INCR_OFFSET);\r
+ bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET); \r
+ bRGA_SRC_TILE_OFFSETX = (u32 *)(base + RGA_SRC_TILE_OFFSETX_OFFSET);\r
+ bRGA_SRC_TILE_OFFSETY = (u32 *)(base + RGA_SRC_TILE_OFFSETY_OFFSET);\r
+\r
+ bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);\r
+ bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);\r
+\r
+ /* Matrix reg fill */ \r
+ m0 = (s32)(tile->matrix[0]*(1<<14));\r
+ m1 = (s32)(tile->matrix[1]*(1<<14));\r
+ m2 = (s32)(tile->matrix[2]*(1<<14));\r
+ m3 = (s32)(tile->matrix[3]*(1<<14));\r
+\r
+ *bRGA_SRC_X_PARA = (m0 & 0xffff) | (m2 << 16);\r
+ *bRGA_SRC_Y_PARA = (m1 & 0xffff) | (m3 << 16);\r
+ \r
+ /* src tile information setting */ \r
+ if(msg->rotate_mode != 0)//add by hxx,2011.7.12,for rtl0707,when line scanning ,do not calc src tile info\r
+ {\r
+ *bRGA_SRC_TILE_XINFO = (tile->tile_start_x_coor & 0xffff) | (tile->tile_w << 16);\r
+ *bRGA_SRC_TILE_YINFO = (tile->tile_start_y_coor & 0xffff) | (tile->tile_h << 16);\r
+\r
+ *bRGA_SRC_TILE_H_INCR = ((tile->x_dx) & 0xffff) | ((tile->x_dy) << 16);\r
+ *bRGA_SRC_TILE_V_INCR = ((tile->y_dx) & 0xffff) | ((tile->y_dy) << 16);\r
+\r
+ *bRGA_SRC_TILE_OFFSETX = tile->tile_xoff;\r
+ *bRGA_SRC_TILE_OFFSETY = tile->tile_yoff;\r
+ }\r
+\r
+ pixel_width = RGA_pixel_width_init(msg->src.format);\r
+ \r
+ stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);\r
+\r
+ if ((msg->rotate_mode == 1)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))\r
+ {\r
+ pos[0] = tile->tile_start_x_coor<<8;\r
+ pos[1] = tile->tile_start_y_coor<<8;\r
+\r
+ pos[2] = pos[0];\r
+ pos[3] = pos[1] + tile->tile_h;\r
+\r
+ pos[4] = pos[0] + tile->tile_w;\r
+ pos[5] = pos[1] + tile->tile_h;\r
+\r
+ pos[6] = pos[0] + tile->tile_w;\r
+ pos[7] = pos[1];\r
+\r
+ pos[0] >>= 11;\r
+ pos[1] >>= 11;\r
+\r
+ pos[2] >>= 11;\r
+ pos[3] >>= 11;\r
+\r
+ pos[4] >>= 11;\r
+ pos[5] >>= 11;\r
+\r
+ pos[6] >>= 11;\r
+ pos[7] >>= 11;\r
+\r
+ xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1); \r
+ xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6])); \r
+\r
+ ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1); \r
+ ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7])); \r
+\r
+ xp = xmin + msg->src.x_offset;\r
+ yp = ymin + msg->src.y_offset;\r
+\r
+ if (!((xmax < 0)||(xmin > msg->src.act_w - 1)||(ymax < 0)||(ymin > msg->src.act_h - 1)))\r
+ {\r
+ xp = CLIP(xp, 0, msg->src.vir_w - 1);\r
+ yp = CLIP(yp, 0, msg->src.vir_h - 1);\r
+ }\r
+ \r
+ switch(msg->src.format)\r
+ { \r
+ case RK_FORMAT_YCbCr_420_P :\r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);\r
+ v_addr = msg->src.v_addr + (yp>>1)*(stride>>1) + (xp>>1);\r
+ break;\r
+ case RK_FORMAT_YCbCr_420_SP :\r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); \r
+ break;\r
+ case RK_FORMAT_YCbCr_422_P : \r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);\r
+ v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);\r
+ break;\r
+ case RK_FORMAT_YCbCr_422_SP:\r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1);\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_P :\r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);\r
+ v_addr = msg->src.v_addr + (yp>>1)*(stride>>1) + (xp>>1);\r
+ break;\r
+ case RK_FORMAT_YCrCb_420_SP :\r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1); \r
+ break;\r
+ case RK_FORMAT_YCrCb_422_P : \r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);\r
+ v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);\r
+ break;\r
+ case RK_FORMAT_YCrCb_422_SP:\r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp;\r
+ u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1);\r
+ break; \r
+ default :\r
+ y_addr = msg->src.yrgb_addr + yp*stride + xp*pixel_width;\r
+ break;\r
+ }\r
+\r
+ *bRGA_SRC_Y_MST = y_addr;\r
+ *bRGA_SRC_CB_MST = u_addr;\r
+ *bRGA_SRC_CR_MST = v_addr;\r
+ }\r
+ \r
+ /*dst info*/\r
+ pixel_width = RGA_pixel_width_init(msg->dst.format);\r
+ stride = (msg->dst.vir_w * pixel_width + 3) & (~3);\r
+ *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (tile->dst_ctrl.y_off * stride) + (tile->dst_ctrl.x_off * pixel_width);\r
+ *bRGA_DST_CTR_INFO = (tile->dst_ctrl.w) | ((tile->dst_ctrl.h) << 16);\r
+}\r
+\r
+\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_color_palette_reg_info \r
+Description: \r
+ fill color palette process some relate reg bit\r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+void\r
+RGA_set_color_palette_reg_info(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_SRC_Y_MST;\r
+ u32 p;\r
+ s16 x_off, y_off;\r
+ u16 src_stride;\r
+ u8 shift;\r
+ u16 sw, byte_num;\r
+\r
+ x_off = msg->src.x_offset;\r
+ y_off = msg->src.y_offset;\r
+\r
+ sw = msg->src.vir_w;\r
+ shift = 3 - (msg->palette_mode & 3); \r
+ byte_num = sw >> shift;\r
+ src_stride = (byte_num + 3) & (~3);\r
+ \r
+ p = msg->src.yrgb_addr; \r
+ p = p + (x_off>>shift) + y_off*src_stride;\r
+\r
+ bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET); \r
+ *bRGA_SRC_Y_MST = (u32)p; \r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_color_fill_reg_info \r
+Description: \r
+ fill color fill process some relate reg bit\r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+void\r
+RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg)\r
+{\r
+\r
+ u32 *bRGA_CP_GR_A;\r
+ u32 *bRGA_CP_GR_B;\r
+ u32 *bRGA_CP_GR_G;\r
+ u32 *bRGA_CP_GR_R;\r
+\r
+ u32 *bRGA_PAT_CON;\r
+\r
+ bRGA_CP_GR_A = (u32 *)(base + RGA_CP_GR_A_OFFSET);\r
+ bRGA_CP_GR_B = (u32 *)(base + RGA_CP_GR_B_OFFSET);\r
+ bRGA_CP_GR_G = (u32 *)(base + RGA_CP_GR_G_OFFSET);\r
+ bRGA_CP_GR_R = (u32 *)(base + RGA_CP_GR_R_OFFSET);\r
+\r
+ bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);\r
+\r
+ *bRGA_CP_GR_A = (msg->gr_color.gr_x_a & 0xffff) | (msg->gr_color.gr_y_a << 16);\r
+ *bRGA_CP_GR_B = (msg->gr_color.gr_x_b & 0xffff) | (msg->gr_color.gr_y_b << 16);\r
+ *bRGA_CP_GR_G = (msg->gr_color.gr_x_g & 0xffff) | (msg->gr_color.gr_y_g << 16);\r
+ *bRGA_CP_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);\r
+\r
+ *bRGA_PAT_CON = (msg->pat.vir_w-1) | ((msg->pat.vir_h-1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);\r
+ \r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_line_drawing_reg_info \r
+Description: \r
+ fill line drawing process some relate reg bit\r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_LINE_DRAW;\r
+ u32 *bRGA_DST_VIR_INFO;\r
+ u32 *bRGA_LINE_DRAW_XY_INFO;\r
+ u32 *bRGA_LINE_DRAW_WIDTH;\r
+ u32 *bRGA_LINE_DRAWING_COLOR; \r
+ u32 *bRGA_LINE_DRAWING_MST;\r
+ \r
+ u32 reg = 0;\r
+\r
+ s16 x_width, y_width;\r
+ u16 abs_x, abs_y, delta;\r
+ u16 stride;\r
+ u8 pw;\r
+ u32 start_addr;\r
+ u8 line_dir, dir_major, dir_semi_major;\r
+ u16 major_width;\r
+ \r
+ bRGA_LINE_DRAW = (u32 *)(base + RGA_LINE_DRAW_OFFSET);\r
+ bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);\r
+ bRGA_LINE_DRAW_XY_INFO = (u32 *)(base + RGA_LINE_DRAW_XY_INFO_OFFSET);\r
+ bRGA_LINE_DRAW_WIDTH = (u32 *)(base + RGA_LINE_DRAWING_WIDTH_OFFSET);\r
+ bRGA_LINE_DRAWING_COLOR = (u32 *)(base + RGA_LINE_DRAWING_COLOR_OFFSET);\r
+ bRGA_LINE_DRAWING_MST = (u32 *)(base + RGA_LINE_DRAWING_MST_OFFSET);\r
+\r
+ pw = RGA_pixel_width_init(msg->dst.format);\r
+\r
+ stride = (msg->dst.vir_w * pw + 3) & (~3);\r
+\r
+ start_addr = msg->dst.yrgb_addr \r
+ + (msg->line_draw_info.start_point.y * stride) \r
+ + (msg->line_draw_info.start_point.x * pw);\r
+\r
+ x_width = msg->line_draw_info.start_point.x - msg->line_draw_info.end_point.x;\r
+ y_width = msg->line_draw_info.start_point.y - msg->line_draw_info.end_point.y;\r
+\r
+ abs_x = abs(x_width);\r
+ abs_y = abs(y_width); \r
+ \r
+ if (abs_x >= abs_y)\r
+ {\r
+ if (y_width > 0)\r
+ dir_semi_major = 1;\r
+ else\r
+ dir_semi_major = 0;\r
+\r
+ if (x_width > 0) \r
+ dir_major = 1; \r
+ else\r
+ dir_major = 0;\r
+\r
+ if((abs_x == 0)||(abs_y == 0)) \r
+ delta = 0; \r
+ else \r
+ delta = (abs_y<<12)/abs_x;\r
+\r
+ if (delta >> 12)\r
+ delta -= 1;\r
+ \r
+ major_width = abs_x; \r
+ line_dir = 0;\r
+ }\r
+ else\r
+ {\r
+ if (x_width > 0)\r
+ dir_semi_major = 1;\r
+ else\r
+ dir_semi_major = 0;\r
+\r
+ if (y_width > 0)\r
+ dir_major = 1;\r
+ else\r
+ dir_major = 0;\r
+ \r
+ delta = (abs_x<<12)/abs_y; \r
+ major_width = abs_y;\r
+ line_dir = 1;\r
+ }\r
+ \r
+ reg = (reg & (~m_RGA_LINE_DRAW_MAJOR_WIDTH)) | (s_RGA_LINE_DRAW_MAJOR_WIDTH(major_width));\r
+ reg = (reg & (~m_RGA_LINE_DRAW_LINE_DIRECTION)) | (s_RGA_LINE_DRAW_LINE_DIRECTION(line_dir));\r
+ reg = (reg & (~m_RGA_LINE_DRAW_LINE_WIDTH)) | (s_RGA_LINE_DRAW_LINE_WIDTH(msg->line_draw_info.line_width - 1));\r
+ reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE)) | (s_RGA_LINE_DRAW_INCR_VALUE(delta)); \r
+ reg = (reg & (~m_RGA_LINE_DRAW_DIR_SEMI_MAJOR)) | (s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(dir_semi_major));\r
+ reg = (reg & (~m_RGA_LINE_DRAW_DIR_MAJOR)) | (s_RGA_LINE_DRAW_DIR_MAJOR(dir_major));\r
+ reg = (reg & (~m_RGA_LINE_DRAW_LAST_POINT)) | (s_RGA_LINE_DRAW_LAST_POINT(msg->line_draw_info.flag >> 1));\r
+ reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING)) | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag)); \r
+\r
+ *bRGA_LINE_DRAW = reg;\r
+ \r
+ reg = (msg->line_draw_info.start_point.x & 0xfff) | ((msg->line_draw_info.start_point.y & 0xfff) << 16);\r
+ *bRGA_LINE_DRAW_XY_INFO = reg;\r
+ \r
+ *bRGA_LINE_DRAW_WIDTH = msg->dst.vir_w;\r
+\r
+ *bRGA_LINE_DRAWING_COLOR = msg->line_draw_info.color;\r
+\r
+ *bRGA_LINE_DRAWING_MST = (u32)start_addr;\r
+ \r
+ return 0;\r
+}\r
+\r
+\r
+/*full*/\r
+s32\r
+RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)\r
+{ \r
+ u32 *bRGA_BLUR_SHARP_INFO;\r
+ u32 reg = 0;\r
+ \r
+ bRGA_BLUR_SHARP_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);\r
+\r
+ reg = *bRGA_BLUR_SHARP_INFO;\r
+\r
+ reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_TYPE)) | (s_RGA_BLUR_SHARP_FILTER_TYPE(msg->bsfilter_flag & 3)));\r
+ reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_MODE)) | (s_RGA_BLUR_SHARP_FILTER_MODE(msg->bsfilter_flag >>2)));\r
+\r
+ *bRGA_BLUR_SHARP_INFO = reg;\r
+ \r
+ return 0; \r
+}\r
+\r
+\r
+/*full*/\r
+s32\r
+RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_PRE_SCALE_INFO; \r
+ u32 reg = 0;\r
+ u32 h_ratio = 0;\r
+ u32 v_ratio = 0;\r
+ u32 ps_yuv_flag = 0;\r
+ u32 src_width, src_height;\r
+ u32 dst_width, dst_height;\r
+\r
+ src_width = msg->src.act_w;\r
+ src_height = msg->src.act_h;\r
+\r
+ dst_width = msg->dst.act_w;\r
+ dst_height = msg->dst.act_h;\r
+\r
+ h_ratio = (src_width )<<16 / dst_width;\r
+ v_ratio = (src_height)<<16 / dst_height;\r
+\r
+ if (h_ratio <= (1<<16)) \r
+ h_ratio = 0;\r
+ else if (h_ratio <= (2<<16))\r
+ h_ratio = 1;\r
+ else if (h_ratio <= (4<<16))\r
+ h_ratio = 2;\r
+ else if (h_ratio <= (8<<16))\r
+ h_ratio = 3;\r
+\r
+ if (v_ratio <= (1<<16)) \r
+ v_ratio = 0;\r
+ else if (v_ratio <= (2<<16))\r
+ v_ratio = 1;\r
+ else if (v_ratio <= (4<<16))\r
+ v_ratio = 2;\r
+ else if (v_ratio <= (8<<16))\r
+ v_ratio = 3;\r
+\r
+ if(msg->src.format == msg->dst.format)\r
+ ps_yuv_flag = 0; \r
+ else \r
+ ps_yuv_flag = 1; \r
+\r
+ bRGA_PRE_SCALE_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);\r
+ \r
+ reg = *bRGA_PRE_SCALE_INFO;\r
+ reg = ((reg & (~m_RGA_PRE_SCALE_HOR_RATIO)) | (s_RGA_PRE_SCALE_HOR_RATIO((u8)h_ratio)));\r
+ reg = ((reg & (~m_RGA_PRE_SCALE_VER_RATIO)) | (s_RGA_PRE_SCALE_VER_RATIO((u8)v_ratio)));\r
+ reg = ((reg & (~m_RGA_PRE_SCALE_OUTPUT_FORMAT)) | (s_RGA_PRE_SCALE_OUTPUT_FORMAT(ps_yuv_flag)));\r
+\r
+ *bRGA_PRE_SCALE_INFO = reg;\r
+ \r
+ return 0; \r
+}\r
+\r
+\r
+\r
+/*full*/\r
+int \r
+RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_LUT_MST;\r
+\r
+ if (!msg->LUT_addr) { \r
+ return -1;\r
+ } \r
+\r
+ bRGA_LUT_MST = (u32 *)(base + RGA_LUT_MST_OFFSET);\r
+ \r
+ *bRGA_LUT_MST = (u32)msg->LUT_addr; \r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
+/*full*/\r
+int\r
+RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *bRGA_PAT_MST;\r
+ u32 *bRGA_PAT_CON;\r
+ u32 *bRGA_PAT_START_POINT;\r
+ u32 reg = 0;\r
+ rga_img_info_t *pat;\r
+\r
+ pat = (rga_img_info_t *)&msg->pat;\r
+\r
+ bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);\r
+ bRGA_PAT_MST = (u32 *)(base + RGA_PAT_MST_OFFSET);\r
+ bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);\r
+\r
+ if ( !pat->yrgb_addr ) {\r
+ return -1;\r
+ } \r
+ *bRGA_PAT_MST = (u32)pat->yrgb_addr;\r
+\r
+ if ((pat->vir_w > 256)||(pat->x_offset > 256)||(pat->y_offset > 256)) {\r
+ return -1;\r
+ }\r
+ *bRGA_PAT_START_POINT = (pat->vir_w * pat->y_offset) + pat->x_offset;\r
+\r
+ reg = (pat->vir_w-1) | ((pat->vir_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);\r
+ *bRGA_PAT_CON = reg; \r
+ \r
+ return 0;\r
+}\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_set_mmu_ctrl_reg_info \r
+Description: \r
+ fill mmu relate some reg info \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+\r
+s32\r
+RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg)\r
+{\r
+ u32 *RGA_MMU_TLB, *RGA_MMU_CTRL_ADDR;\r
+ u32 mmu_addr;\r
+ u8 TLB_size, mmu_enable, src_flag, dst_flag, CMD_flag;\r
+ u32 reg = 0;\r
+\r
+ mmu_addr = (u32)msg->mmu_info.base_addr;\r
+ TLB_size = (msg->mmu_info.mmu_flag >> 4) & 0x3;\r
+ mmu_enable = msg->mmu_info.mmu_flag & 0x1;\r
+ \r
+ src_flag = (msg->mmu_info.mmu_flag >> 1) & 0x1;\r
+ dst_flag = (msg->mmu_info.mmu_flag >> 2) & 0x1;\r
+ CMD_flag = (msg->mmu_info.mmu_flag >> 3) & 0x1;\r
+\r
+ RGA_MMU_TLB = (u32 *)(base + RGA_MMU_TLB_OFFSET);\r
+ RGA_MMU_CTRL_ADDR = (u32 *)(base + RGA_FADING_CON_OFFSET);\r
+\r
+ reg = ((reg & (~m_RGA_MMU_CTRL_TLB_ADDR)) | s_RGA_MMU_CTRL_TLB_ADDR(mmu_addr));\r
+ *RGA_MMU_TLB = reg;\r
+\r
+ reg = *RGA_MMU_CTRL_ADDR; \r
+ reg = ((reg & (~m_RGA_MMU_CTRL_PAGE_TABLE_SIZE)) | s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(TLB_size));\r
+ reg = ((reg & (~m_RGA_MMU_CTRL_MMU_ENABLE)) | s_RGA_MMU_CTRL_MMU_ENABLE(mmu_enable));\r
+ reg = ((reg & (~m_RGA_MMU_CTRL_SRC_FLUSH)) | s_RGA_MMU_CTRL_SRC_FLUSH(src_flag));\r
+ reg = ((reg & (~m_RGA_MMU_CTRL_DST_FLUSH)) | s_RGA_MMU_CTRL_DST_FLUSH(dst_flag));\r
+ reg = ((reg & (~m_RGA_MMU_CTRL_CMD_CHAN_FLUSH)) | s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(CMD_flag));\r
+ *RGA_MMU_CTRL_ADDR = reg;\r
+ \r
+ return 0;\r
+}\r
+\r
+\r
+\r
+/************************************************************* \r
+Func: \r
+ RGA_gen_reg_info \r
+Description: \r
+ Generate RGA command reg list from rga_req struct. \r
+Author: \r
+ ZhangShengqin \r
+Date: \r
+ 20012-2-2 10:59:25 \r
+**************************************************************/\r
+unsigned int\r
+RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base)\r
+{\r
+ TILE_INFO tile;\r
+\r
+ memset(base, 0x0, 28*4); \r
+ RGA_set_mode_ctrl(base, msg);\r
+ \r
+ switch(msg->render_mode)\r
+ {\r
+ case bitblt_mode :\r
+ RGA_set_alpha_rop(base, msg);\r
+ RGA_set_src(base, msg);\r
+ RGA_set_dst(base, msg); \r
+ RGA_set_color(base, msg);\r
+ RGA_set_fading(base, msg);\r
+ RGA_set_pat(base, msg);\r
+ matrix_cal(msg, &tile);\r
+ dst_ctrl_cal(msg, &tile);\r
+ src_tile_info_cal(msg, &tile);\r
+ RGA_set_bitblt_reg_info(base, msg, &tile); \r
+ break;\r
+ case color_palette_mode :\r
+ RGA_set_src(base, msg);\r
+ RGA_set_dst(base, msg); \r
+ RGA_set_color(base, msg);\r
+ RGA_set_color_palette_reg_info(base, msg);\r
+ break;\r
+ case color_fill_mode :\r
+ RGA_set_dst(base, msg); \r
+ RGA_set_color(base, msg);\r
+ RGA_set_pat(base, msg);\r
+ RGA_set_color_fill_reg_info(base, msg);\r
+ break;\r
+ case line_point_drawing_mode :\r
+ RGA_set_alpha_rop(base, msg);\r
+ RGA_set_dst(base, msg);\r
+ RGA_set_color(base, msg);\r
+ RGA_set_line_drawing_reg_info(base, msg);\r
+ break;\r
+ case blur_sharp_filter_mode :\r
+ RGA_set_src(base, msg);\r
+ RGA_set_dst(base, msg);\r
+ RGA_set_filter_reg_info(base, msg);\r
+ break;\r
+ case pre_scaling_mode :\r
+ RGA_set_src(base, msg);\r
+ RGA_set_dst(base, msg); \r
+ RGA_set_pre_scale_reg_info(base, msg);\r
+ break;\r
+ case update_palette_table_mode :\r
+ if (RGA_set_update_palette_table_reg_info(base, msg)) {\r
+ return -1;\r
+ }\r
+ break;\r
+ case update_patten_buff_mode:\r
+ if (RGA_set_update_patten_buff_reg_info(base, msg)){ \r
+ return -1;\r
+ }\r
+ \r
+ break;\r
+ }\r
+\r
+ RGA_set_mmu_ctrl_reg_info(base, msg);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+#ifndef __REG_INFO_H__\r
+#define __REG_INFO_H__\r
+\r
+\r
+//#include "chip_register.h"\r
+\r
+//#include "rga_struct.h"\r
+#include "rga.h"\r
+\r
+#ifndef MIN\r
+#define MIN(X, Y) ((X)<(Y)?(X):(Y))\r
+#endif\r
+\r
+#ifndef MAX\r
+#define MAX(X, Y) ((X)>(Y)?(X):(Y))\r
+#endif\r
+\r
+#ifndef ABS\r
+#define ABS(X) (((X) < 0) ? (-(X)) : (X))\r
+#endif\r
+\r
+#ifndef CLIP\r
+#define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))\r
+#endif\r
+\r
+//RGA register map\r
+\r
+//General Registers\r
+#define rRGA_SYS_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_SYS_CTRL))\r
+#define rRGA_CMD_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_CMD_CTRL))\r
+#define rRGA_CMD_ADDR (*(volatile uint32 *)(RGA_BASE + RGA_CMD_ADDR))\r
+#define rRGA_STATUS (*(volatile uint32 *)(RGA_BASE + RGA_STATUS))\r
+#define rRGA_INT (*(volatile uint32 *)(RGA_BASE + RGA_INT))\r
+#define rRGA_AXI_ID (*(volatile uint32 *)(RGA_BASE + RGA_AXI_ID))\r
+#define rRGA_MMU_STA_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_MMU_STA_CTRL))\r
+#define rRGA_MMU_STA (*(volatile uint32 *)(RGA_BASE + RGA_MMU_STA))\r
+\r
+//Command code start\r
+#define rRGA_MODE_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_MODE_CTRL))\r
+\r
+//Source Image Registers\r
+#define rRGA_SRC_Y_MST (*(volatile uint32 *)(RGA_BASE + RGA_SRC_Y_MST))\r
+#define rRGA_SRC_CB_MST (*(volatile uint32 *)(RGA_BASE + RGA_SRC_CB_MST))\r
+#define rRGA_MASK_READ_MST (*(volatile uint32 *)(RGA_BASE + RGA_MASK_READ_MST)) //repeat\r
+#define rRGA_SRC_CR_MST (*(volatile uint32 *)(RGA_BASE + RGA_SRC_CR_MST))\r
+#define rRGA_SRC_VIR_INFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_VIR_INFO))\r
+#define rRGA_SRC_ACT_INFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_ACT_INFO))\r
+#define rRGA_SRC_X_PARA (*(volatile uint32 *)(RGA_BASE + RGA_SRC_X_PARA))\r
+#define rRGA_SRC_Y_PARA (*(volatile uint32 *)(RGA_BASE + RGA_SRC_Y_PARA))\r
+#define rRGA_SRC_TILE_XINFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_XINFO))\r
+#define rRGA_SRC_TILE_YINFO (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_YINFO))\r
+#define rRGA_SRC_TILE_H_INCR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_H_INCR))\r
+#define rRGA_SRC_TILE_V_INCR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_V_INCR))\r
+#define rRGA_SRC_TILE_OFFSETX (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_OFFSETX))\r
+#define rRGA_SRC_TILE_OFFSETY (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TILE_OFFSETY))\r
+#define rRGA_SRC_BG_COLOR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_BG_COLOR))\r
+#define rRGA_SRC_FG_COLOR (*(volatile uint32 *)(RGA_BASE + RGA_SRC_FG_COLOR))\r
+#define rRGA_LINE_DRAWING_COLOR (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAWING_COLOR)) //repeat\r
+#define rRGA_SRC_TR_COLOR0 (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TR_COLOR0))\r
+#define rRGA_CP_GR_A (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_A)) //repeat\r
+#define rRGA_SRC_TR_COLOR1 (*(volatile uint32 *)(RGA_BASE + RGA_SRC_TR_COLOR1))\r
+#define rRGA_CP_GR_B (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_B)) //repeat\r
+\r
+#define rRGA_LINE_DRAW (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAW))\r
+#define rRGA_PAT_START_POINT (*(volatile uint32 *)(RGA_BASE + RGA_PAT_START_POINT)) //repeat\r
+\r
+//Destination Image Registers\r
+#define rRGA_DST_MST (*(volatile uint32 *)(RGA_BASE + RGA_DST_MST))\r
+#define rRGA_LUT_MST (*(volatile uint32 *)(RGA_BASE + RGA_LUT_MST)) //repeat\r
+#define rRGA_PAT_MST (*(volatile uint32 *)(RGA_BASE + RGA_PAT_MST)) //repeat\r
+#define rRGA_LINE_DRAWING_MST (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAWING_MST)) //repeat\r
+\r
+#define rRGA_DST_VIR_INFO (*(volatile uint32 *)(RGA_BASE + RGA_DST_VIR_INFO))\r
+\r
+#define rRGA_DST_CTR_INFO (*(volatile uint32 *)(RGA_BASE + RGA_DST_CTR_INFO))\r
+#define rRGA_LINE_DRAW_XY_INFO (*(volatile uint32 *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO)) //repeat \r
+\r
+//Alpha/ROP Registers\r
+#define rRGA_ALPHA_CON (*(volatile uint32 *)(RGA_BASE + RGA_ALPHA_CON))\r
+#define rRGA_FADING_CON (*(volatile uint32 *)(RGA_BASE + RGA_FADING_CON))\r
+\r
+#define rRGA_PAT_CON (*(volatile uint32 *)(RGA_BASE + RGA_PAT_CON))\r
+#define rRGA_DST_VIR_WIDTH_PIX (*(volatile uint32 *)(RGA_BASE + RGA_DST_VIR_WIDTH_PIX)) //repeat\r
+\r
+#define rRGA_ROP_CON0 (*(volatile uint32 *)(RGA_BASE + RGA_ROP_CON0))\r
+#define rRGA_CP_GR_G (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_G)) //repeat\r
+#define rRGA_PRESCL_CB_MST (*(volatile uint32 *)(RGA_BASE + RGA_PRESCL_CB_MST)) //repeat\r
+\r
+#define rRGA_ROP_CON1 (*(volatile uint32 *)(RGA_BASE + RGA_ROP_CON1))\r
+#define rRGA_CP_GR_R (*(volatile uint32 *)(RGA_BASE + RGA_CP_GR_R)) //repeat\r
+#define rRGA_PRESCL_CR_MST (*(volatile uint32 *)(RGA_BASE + RGA_PRESCL_CR_MST)) //repeat\r
+\r
+//MMU Register\r
+#define rRGA_MMU_CTRL (*(volatile uint32 *)(RGA_BASE + RGA_MMU_CTRL))\r
+\r
+\r
+\r
+\r
+//-----------------------------------------------------------------\r
+//reg detail definition\r
+//-----------------------------------------------------------------\r
+/*RGA_SYS_CTRL*/\r
+#define m_RGA_SYS_CTRL_CMD_MODE ( 1<<2 )\r
+#define m_RGA_SYS_CTRL_OP_ST_SLV ( 1<<1 )\r
+#define m_RGA_sys_CTRL_SOFT_RESET ( 1<<0 )\r
+\r
+#define s_RGA_SYS_CTRL_CMD_MODE(x) ( (x&0x1)<<2 )\r
+#define s_RGA_SYS_CTRL_OP_ST_SLV(x) ( (x&0x1)<<1 )\r
+#define s_RGA_sys_CTRL_SOFT_RESET(x) ( (x&0x1)<<0 )\r
+\r
+\r
+/*RGA_CMD_CTRL*/\r
+#define m_RGA_CMD_CTRL_CMD_INCR_NUM ( 0x3ff<<3 )\r
+#define m_RGA_CMD_CTRL_CMD_STOP_MODE ( 1<<2 )\r
+#define m_RGA_CMD_CTRL_CMD_INCR_VALID ( 1<<1 )\r
+#define m_RGA_CMD_CTRL_CMD_LINE_FET_ST ( 1<<0 )\r
+\r
+#define s_RGA_CMD_CTRL_CMD_INCR_NUM(x) ( (x&0x3ff)<<3 )\r
+#define s_RGA_CMD_CTRL_CMD_STOP_MODE(x) ( (x&0x1)<<2 )\r
+#define s_RGA_CMD_CTRL_CMD_INCR_VALID(x) ( (x&0x1)<<1 )\r
+#define s_RGA_CMD_CTRL_CMD_LINE_FET_ST(x) ( (x*0x1)<<0 )\r
+\r
+\r
+/*RGA_STATUS*/\r
+#define m_RGA_CMD_STATUS_CMD_TOTAL_NUM ( 0xfff<<20 )\r
+#define m_RGA_CMD_STATUS_NOW_CMD_NUM ( 0xfff<<8 )\r
+#define m_RGA_CMD_STATUS_ENGINE_STATUS ( 1<<0 )\r
+\r
+\r
+/*RGA_INT*/\r
+#define m_RGA_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )\r
+#define m_RGA_INT_MMU_INT_EN ( 1<<9 )\r
+#define m_RGA_INT_ERROR_INT_EN ( 1<<8 )\r
+#define m_RGA_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )\r
+#define m_RGA_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )\r
+#define m_RGA_INT_MMU_INT_CLEAR ( 1<<5 )\r
+#define m_RGA_INT_ERROR_INT_CLEAR ( 1<<4 )\r
+#define m_RGA_INT_NOW_CMD_DONE_INT_FLAG ( 1<<3 )\r
+#define m_RGA_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )\r
+#define m_RGA_INT_MMU_INT_FLAG ( 1<<1 )\r
+#define m_RGA_INT_ERROR_INT_FLAG ( 1<<0 )\r
+\r
+#define s_RGA_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )\r
+#define s_RGA_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )\r
+#define s_RGA_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )\r
+#define s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )\r
+#define s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )\r
+#define s_RGA_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )\r
+#define s_RGA_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )\r
+\r
+\r
+/*RGA_AXI_ID*/\r
+#define m_RGA_AXI_ID_MMU_READ ( 3<<30 )\r
+#define m_RGA_AXI_ID_MMU_WRITE ( 3<<28 )\r
+#define m_RGA_AXI_ID_MASK_READ ( 0xf<<24 )\r
+#define m_RGA_AXI_ID_CMD_FET ( 0xf<<20 )\r
+#define m_RGA_AXI_ID_DST_WRITE ( 0xf<<16 )\r
+#define m_RGA_AXI_ID_DST_READ ( 0xf<<12 )\r
+#define m_RGA_AXI_ID_SRC_CR_READ ( 0xf<<8 )\r
+#define m_RGA_AXI_ID_SRC_CB_READ ( 0xf<<4 )\r
+#define m_RGA_AXI_ID_SRC_Y_READ ( 0xf<<0 )\r
+\r
+#define s_RGA_AXI_ID_MMU_READ(x) ( (x&0x3)<<30 )\r
+#define s_RGA_AXI_ID_MMU_WRITE(x) ( (x&0x3)<<28 )\r
+#define s_RGA_AXI_ID_MASK_READ(x) ( (x&0xf)<<24 )\r
+#define s_RGA_AXI_ID_CMD_FET(x) ( (x&0xf)<<20 )\r
+#define s_RGA_AXI_ID_DST_WRITE(x) ( (x&0xf)<<16 )\r
+#define s_RGA_AXI_ID_DST_READ(x) ( (x&0xf)<<12 )\r
+#define s_RGA_AXI_ID_SRC_CR_READ(x) ( (x&0xf)<<8 )\r
+#define s_RGA_AXI_ID_SRC_CB_READ(x) ( (x&0xf)<<4 )\r
+#define s_RGA_AXI_ID_SRC_Y_READ(x) ( (x&0xf)<<0 )\r
+\r
+\r
+/*RGA_MMU_STA_CTRL*/\r
+#define m_RGA_MMU_STA_CTRL_TLB_STA_CLEAR ( 1<<3 )\r
+#define m_RGA_MMU_STA_CTRL_TLB_STA_RESUME ( 1<<2 )\r
+#define m_RGA_MMU_STA_CTRL_TLB_STA_PAUSE ( 1<<1 )\r
+#define m_RGA_MMU_STA_CTRL_TLB_STA_EN ( 1<<0 )\r
+\r
+#define s_RGA_MMU_STA_CTRL_TLB_STA_CLEAR(x) ( (x&0x1)<<3 )\r
+#define s_RGA_MMU_STA_CTRL_TLB_STA_RESUME(x) ( (x&0x1)<<2 )\r
+#define s_RGA_MMU_STA_CTRL_TLB_STA_PAUSE(x) ( (x&0x1)<<1 )\r
+#define s_RGA_MMU_STA_CTRL_TLB_STA_EN(x) ( (x&0x1)<<0 )\r
+\r
+\r
+\r
+/* RGA_MODE_CTRL */\r
+#define m_RGA_MODE_CTRL_2D_RENDER_MODE ( 7<<0 )\r
+#define m_RGA_MODE_CTRL_SRC_RGB_PACK ( 1<<3 )\r
+#define m_RGA_MODE_CTRL_SRC_FORMAT ( 15<<4 )\r
+#define m_RGA_MODE_CTRL_SRC_RB_SWAP ( 1<<8 )\r
+#define m_RGA_MODE_CTRL_SRC_ALPHA_SWAP ( 1<<9 )\r
+#define m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE ( 1<<10 )\r
+#define m_RGA_MODE_CTRL_YUV2RGB_CON_MODE ( 3<<11 )\r
+#define m_RGA_MODE_CTRL_SRC_TRANS_MODE (0x1f<<13 )\r
+#define m_RGA_MODE_CTRL_SRC_TR_MODE ( 1<<13 )\r
+#define m_RGA_MODE_CTRL_SRC_TR_R_EN ( 1<<14 )\r
+#define m_RGA_MODE_CTRL_SRC_TR_G_EN ( 1<<15 )\r
+#define m_RGA_MODE_CTRL_SRC_TR_B_EN ( 1<<16 )\r
+#define m_RGA_MODE_CTRL_SRC_TR_A_EN ( 1<<17 )\r
+#define m_RGA_MODE_CTRL_ROTATE_MODE ( 3<<18 )\r
+#define m_RGA_MODE_CTRL_SCALE_MODE ( 3<<20 )\r
+#define m_RGA_MODE_CTRL_PAT_SEL ( 1<<22 )\r
+#define m_RGA_MODE_CTRL_DST_FORMAT ( 3<<23 )\r
+#define m_RGA_MODE_CTRL_DST_RGB_PACK ( 1<<25 )\r
+#define m_RGA_MODE_CTRL_DST_RB_SWAP ( 1<<26 )\r
+#define m_RGA_MODE_CTRL_DST_ALPHA_SWAP ( 1<<27 )\r
+#define m_RGA_MODE_CTRL_LUT_ENDIAN_MODE ( 1<<28 )\r
+#define m_RGA_MODE_CTRL_CMD_INT_ENABLE ( 1<<29 )\r
+#define m_RGA_MODE_CTRL_ZERO_MODE_ENABLE ( 1<<30 )\r
+#define m_RGA_MODE_CTRL_DST_ALPHA_ENABLE ( 1<<30 )\r
+\r
+\r
+\r
+#define s_RGA_MODE_CTRL_2D_RENDER_MODE(x) ( (x&0x7)<<0 )\r
+#define s_RGA_MODE_CTRL_SRC_RGB_PACK(x) ( (x&0x1)<<3 )\r
+#define s_RGA_MODE_CTRL_SRC_FORMAT(x) ( (x&0xf)<<4 )\r
+#define s_RGA_MODE_CTRL_SRC_RB_SWAP(x) ( (x&0x1)<<8 )\r
+#define s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(x) ( (x&0x1)<<9 )\r
+#define s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE(x) ( (x&0x1)<<10 )\r
+#define s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(x) ( (x&0x3)<<11 )\r
+#define s_RGA_MODE_CTRL_SRC_TRANS_MODE(x) ( (x&0x1f)<<13 )\r
+#define s_RGA_MODE_CTRL_SRC_TR_MODE(x) ( (x&0x1)<<13 )\r
+#define s_RGA_MODE_CTRL_SRC_TR_R_EN(x) ( (x&0x1)<<14 )\r
+#define s_RGA_MODE_CTRL_SRC_TR_G_EN(x) ( (x&0x1)<<15 )\r
+#define s_RGA_MODE_CTRL_SRC_TR_B_EN(x) ( (x&0x1)<<16 )\r
+#define s_RGA_MODE_CTRL_SRC_TR_A_EN(x) ( (x&0x1)<<17 )\r
+#define s_RGA_MODE_CTRL_ROTATE_MODE(x) ( (x&0x3)<<18 )\r
+#define s_RGA_MODE_CTRL_SCALE_MODE(x) ( (x&0x3)<<20 )\r
+#define s_RGA_MODE_CTRL_PAT_SEL(x) ( (x&0x1)<<22 )\r
+#define s_RGA_MODE_CTRL_DST_FORMAT(x) ( (x&0x3)<<23 )\r
+#define s_RGA_MODE_CTRL_DST_RGB_PACK(x) ( (x&0x1)<<25 )\r
+#define s_RGA_MODE_CTRL_DST_RB_SWAP(x) ( (x&0x1)<<26 )\r
+#define s_RGA_MODE_CTRL_DST_ALPHA_SWAP(x) ( (x&0x1)<<27 )\r
+#define s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(x) ( (x&0x1)<<28 )\r
+#define s_RGA_MODE_CTRL_CMD_INT_ENABLE(x) ( (x&0x1)<<29 )\r
+#define s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(x) ( (x&0x1)<<30 )\r
+#define s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(x) ( (x&0x1)<<31 )\r
+\r
+\r
+\r
+/* RGA_LINE_DRAW */\r
+#define m_RGA_LINE_DRAW_MAJOR_WIDTH ( 0x7ff<<0 )\r
+#define m_RGA_LINE_DRAW_LINE_DIRECTION ( 0x1<<11)\r
+#define m_RGA_LINE_DRAW_LINE_WIDTH ( 0xf<<12)\r
+#define m_RGA_LINE_DRAW_INCR_VALUE ( 0xfff<<16)\r
+#define m_RGA_LINE_DRAW_DIR_MAJOR ( 0x1<<28)\r
+#define m_RGA_LINE_DRAW_DIR_SEMI_MAJOR ( 0x1<<29)\r
+#define m_RGA_LINE_DRAW_LAST_POINT ( 0x1<<30)\r
+#define m_RGA_LINE_DRAW_ANTI_ALISING ( 0x1<<31)\r
+\r
+#define s_RGA_LINE_DRAW_MAJOR_WIDTH(x) (((x)&0x7ff)<<0 )\r
+#define s_RGA_LINE_DRAW_LINE_DIRECTION(x) ( ((x)&0x1)<<11)\r
+#define s_RGA_LINE_DRAW_LINE_WIDTH(x) ( ((x)&0xf)<<12)\r
+#define s_RGA_LINE_DRAW_INCR_VALUE(x) (((x)&0xfff)<<16)\r
+#define s_RGA_LINE_DRAW_DIR_MAJOR(x) ( ((x)&0x1)<<28)\r
+#define s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(x) ( ((x)&0x1)<<29)\r
+#define s_RGA_LINE_DRAW_LAST_POINT(x) ( ((x)&0x1)<<30)\r
+#define s_RGA_LINE_DRAW_ANTI_ALISING(x) ( ((x)&0x1)<<31)\r
+\r
+ \r
+/* RGA_ALPHA_CON */\r
+#define m_RGA_ALPHA_CON_ENABLE ( 0x1<<0 )\r
+#define m_RGA_ALPHA_CON_A_OR_R_SEL ( 0x1<<1 )\r
+#define m_RGA_ALPHA_CON_ALPHA_MODE ( 0x3<<2 )\r
+#define m_RGA_ALPHA_CON_PD_MODE ( 0xf<<4 )\r
+#define m_RGA_ALPHA_CON_SET_CONSTANT_VALUE (0xff<<8 )\r
+#define m_RGA_ALPHA_CON_PD_M_SEL ( 0x1<<16)\r
+#define m_RGA_ALPHA_CON_FADING_ENABLE ( 0x1<<17)\r
+#define m_RGA_ALPHA_CON_ROP_MODE_SEL ( 0x3<<18)\r
+#define m_RGA_ALPHA_CON_CAL_MODE_SEL ( 0x1<<28)\r
+#define m_RGA_ALPHA_CON_DITHER_ENABLE ( 0x1<<29)\r
+#define m_RGA_ALPHA_CON_GRADIENT_CAL_MODE ( 0x1<<30)\r
+#define m_RGA_ALPHA_CON_AA_SEL ( 0x1<<31)\r
+\r
+#define s_RGA_ALPHA_CON_ENABLE(x) ( (x&0x1)<<0 )\r
+#define s_RGA_ALPHA_CON_A_OR_R_SEL(x) ( (x&0x1)<<1 )\r
+#define s_RGA_ALPHA_CON_ALPHA_MODE(x) ( (x&0x3)<<2 )\r
+#define s_RGA_ALPHA_CON_PD_MODE(x) ( (x&0xf)<<4 )\r
+#define s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(x) ((x&0xff)<<8 )\r
+#define s_RGA_ALPHA_CON_PD_M_SEL(x) ( (x&0x1)<<16)\r
+#define s_RGA_ALPHA_CON_FADING_ENABLE(x) ( (x&0x1)<<17)\r
+#define s_RGA_ALPHA_CON_ROP_MODE_SEL(x) ( (x&0x3)<<18)\r
+#define s_RGA_ALPHA_CON_CAL_MODE_SEL(x) ( (x&0x1)<<28)\r
+#define s_RGA_ALPHA_CON_DITHER_ENABLE(x) ( (x&0x1)<<29)\r
+#define s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(x) ( (x&0x1)<<30)\r
+#define s_RGA_ALPHA_CON_AA_SEL(x) ( (x&0x1)<<31)\r
+\r
+\r
+/* blur sharp mode */\r
+#define m_RGA_BLUR_SHARP_FILTER_MODE ( 0x1<<25 )\r
+#define m_RGA_BLUR_SHARP_FILTER_TYPE ( 0x3<<26 )\r
+\r
+#define s_RGA_BLUR_SHARP_FILTER_MODE(x) ( (x&0x1)<<25 )\r
+#define s_RGA_BLUR_SHARP_FILTER_TYPE(x) ( (x&0x3)<<26 )\r
+\r
+\r
+/* pre scale mode */\r
+#define m_RGA_PRE_SCALE_HOR_RATIO ( 0x3 <<20 )\r
+#define m_RGA_PRE_SCALE_VER_RATIO ( 0x3 <<22 )\r
+#define m_RGA_PRE_SCALE_OUTPUT_FORMAT ( 0x1 <<24 )\r
+\r
+#define s_RGA_PRE_SCALE_HOR_RATIO(x) ( (x&0x3) <<20 )\r
+#define s_RGA_PRE_SCALE_VER_RATIO(x) ( (x&0x3) <<22 )\r
+#define s_RGA_PRE_SCALE_OUTPUT_FORMAT(x) ( (x&0x1) <<24 )\r
+\r
+\r
+\r
+/* RGA_MMU_CTRL*/\r
+#define m_RGA_MMU_CTRL_TLB_ADDR ( 0xffffffff<<0)\r
+#define m_RGA_MMU_CTRL_PAGE_TABLE_SIZE ( 0x3<<4 )\r
+#define m_RGA_MMU_CTRL_MMU_ENABLE ( 0x1<<0 )\r
+#define m_RGA_MMU_CTRL_SRC_FLUSH ( 0x1<<1 )\r
+#define m_RGA_MMU_CTRL_DST_FLUSH ( 0x1<<2 )\r
+#define m_RGA_MMU_CTRL_CMD_CHAN_FLUSH ( 0x1<<3 )\r
+\r
+#define s_RGA_MMU_CTRL_TLB_ADDR(x) ((x&0xffffffff))\r
+#define s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(x) ((x&0x3)<<4)\r
+#define s_RGA_MMU_CTRL_MMU_ENABLE(x) ((x&0x1)<<0)\r
+#define s_RGA_MMU_CTRL_SRC_FLUSH(x) ((x&0x1)<<1)\r
+#define s_RGA_MMU_CTRL_DST_FLUSH(x) ((x&0x1)<<2)\r
+#define s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(x) ((x&0x1)<<3)\r
+\r
+#endif\r
+\r
+/*\r
+#define RGA_MODE_CTRL_OFFSET 0x0\r
+#define RGA_SRC_Y_MST_OFFSET 0x4\r
+#define RGA_SRC_CB_MST_OFFSET 0x8\r
+#define RGA_SRC_CR_MST_OFFSET 0xc\r
+#define RGA_SRC_VIR_INFO_OFFSET 0x10\r
+#define RGA_SRC_ACT_INFO_OFFSET 0x14\r
+#define RGA_SRC_X_PARA_OFFSET 0x18\r
+#define RGA_SRC_Y_PARA_OFFSET 0x1c\r
+#define RGA_SRC_TILE_XINFO_OFFSET 0x20\r
+#define RGA_SRC_TILE_YINFO_OFFSET 0x24\r
+#define RGA_SRC_TILE_H_INCR_OFFSET 0x28\r
+#define RGA_SRC_TILE_V_INCR_OFFSET 0x2c\r
+#define RGA_SRC_TILE_OFFSETX_OFFSET 0x30\r
+#define RGA_SRC_TILE_OFFSETY_OFFSET 0x34\r
+#define RGA_SRC_BG_COLOR_OFFSET 0x38\r
+\r
+#define RGA_SRC_FG_COLOR_OFFSET 0x3c\r
+#define RGA_LINE_DRAWING_COLOR_OFFSET 0x3c\r
+\r
+#define RGA_SRC_TR_COLOR0_OFFSET 0x40\r
+#define RGA_CP_GR_A_OFFSET 0x40 //repeat\r
+\r
+#define RGA_SRC_TR_COLOR1_OFFSET 0x44\r
+#define RGA_CP_GR_B_OFFSET 0x44 //repeat\r
+\r
+#define RGA_LINE_DRAW_OFFSET 0x48\r
+#define RGA_PAT_START_POINT_OFFSET 0x48 //repeat\r
+\r
+#define RGA_DST_MST_OFFSET 0x4c\r
+#define RGA_LUT_MST_OFFSET 0x4c //repeat\r
+#define RGA_PAT_MST_OFFSET 0x4c //repeat\r
+#define RGA_LINE_DRAWING_MST_OFFSET 0x4c //repeat\r
+\r
+#define RGA_DST_VIR_INFO_OFFSET 0x50\r
+\r
+#define RGA_DST_CTR_INFO_OFFSET 0x54\r
+#define RGA_LINE_DRAW_XY_INFO_OFFSET 0x54 //repeat \r
+\r
+#define RGA_ALPHA_CON_OFFSET 0x58\r
+#define RGA_FADING_CON_OFFSET 0x5c\r
+\r
+#define RGA_PAT_CON_OFFSET 0x60\r
+#define RGA_LINE_DRAWING_WIDTH_OFFSET 0x60 //repeat\r
+\r
+#define RGA_ROP_CON0_OFFSET 0x64\r
+#define RGA_CP_GR_G_OFFSET 0x64 //repeat\r
+#define RGA_PRESCL_CB_MST_OFFSET 0x64 //repeat\r
+\r
+#define RGA_ROP_CON1_OFFSET 0x68\r
+#define RGA_CP_GR_R_OFFSET 0x68 //repeat\r
+#define RGA_PRESCL_CR_MST_OFFSET 0x68 //repeat\r
+\r
+#define RGA_MMU_CTRL_OFFSET 0x6c\r
+\r
+\r
+#define RGA_SYS_CTRL_OFFSET 0x000\r
+#define RGA_CMD_CTRL_OFFSET 0x004\r
+#define RGA_CMD_ADDR_OFFSET 0x008\r
+#define RGA_STATUS_OFFSET 0x00c\r
+#define RGA_INT_OFFSET 0x010\r
+#define RGA_AXI_ID_OFFSET 0x014\r
+#define RGA_MMU_STA_CTRL_OFFSET 0x018\r
+#define RGA_MMU_STA_OFFSET 0x01c\r
+*/\r
+//hxx\r
+\r
+#define RGA_SYS_CTRL_OFFSET (RGA_SYS_CTRL-0x100)\r
+#define RGA_CMD_CTRL_OFFSET (RGA_CMD_CTRL-0x100)\r
+#define RGA_CMD_ADDR_OFFSET (RGA_CMD_ADDR-0x100)\r
+#define RGA_STATUS_OFFSET (RGA_STATUS-0x100)\r
+#define RGA_INT_OFFSET (RGA_INT-0x100)\r
+#define RGA_AXI_ID_OFFSET (RGA_AXI_ID-0x100)\r
+#define RGA_MMU_STA_CTRL_OFFSET (RGA_MMU_STA_CTRL-0x100)\r
+#define RGA_MMU_STA_OFFSET (RGA_MMU_STA-0x100)\r
+\r
+#define RGA_MODE_CTRL_OFFSET (RGA_MODE_CTRL-0x100)\r
+#define RGA_SRC_Y_MST_OFFSET (RGA_SRC_Y_MST-0x100)\r
+#define RGA_SRC_CB_MST_OFFSET (RGA_SRC_CB_MST-0x100)\r
+#define RGA_SRC_CR_MST_OFFSET (RGA_SRC_CR_MST-0x100)\r
+#define RGA_SRC_VIR_INFO_OFFSET (RGA_SRC_VIR_INFO-0x100)\r
+#define RGA_SRC_ACT_INFO_OFFSET (RGA_SRC_ACT_INFO-0x100)\r
+#define RGA_SRC_X_PARA_OFFSET (RGA_SRC_X_PARA-0x100)\r
+#define RGA_SRC_Y_PARA_OFFSET (RGA_SRC_Y_PARA-0x100)\r
+#define RGA_SRC_TILE_XINFO_OFFSET (RGA_SRC_TILE_XINFO-0x100)\r
+#define RGA_SRC_TILE_YINFO_OFFSET (RGA_SRC_TILE_YINFO-0x100)\r
+#define RGA_SRC_TILE_H_INCR_OFFSET (RGA_SRC_TILE_H_INCR-0x100)\r
+#define RGA_SRC_TILE_V_INCR_OFFSET (RGA_SRC_TILE_V_INCR-0x100)\r
+#define RGA_SRC_TILE_OFFSETX_OFFSET (RGA_SRC_TILE_OFFSETX-0x100)\r
+#define RGA_SRC_TILE_OFFSETY_OFFSET (RGA_SRC_TILE_OFFSETY-0x100)\r
+#define RGA_SRC_BG_COLOR_OFFSET (RGA_SRC_BG_COLOR-0x100)\r
+\r
+#define RGA_SRC_FG_COLOR_OFFSET (RGA_SRC_FG_COLOR-0x100)\r
+#define RGA_LINE_DRAWING_COLOR_OFFSET (RGA_LINE_DRAWING_COLOR-0x100)\r
+\r
+#define RGA_SRC_TR_COLOR0_OFFSET (RGA_SRC_TR_COLOR0-0x100)\r
+#define RGA_CP_GR_A_OFFSET (RGA_CP_GR_A-0x100) //repeat\r
+\r
+#define RGA_SRC_TR_COLOR1_OFFSET (RGA_SRC_TR_COLOR1-0x100)\r
+#define RGA_CP_GR_B_OFFSET (RGA_CP_GR_B-0x100) //repeat\r
+\r
+#define RGA_LINE_DRAW_OFFSET (RGA_LINE_DRAW-0x100)\r
+#define RGA_PAT_START_POINT_OFFSET (RGA_PAT_START_POINT-0x100) //repeat\r
+\r
+#define RGA_DST_MST_OFFSET (RGA_DST_MST-0x100)\r
+#define RGA_LUT_MST_OFFSET (RGA_LUT_MST-0x100) //repeat\r
+#define RGA_PAT_MST_OFFSET (RGA_PAT_MST-0x100) //repeat\r
+#define RGA_LINE_DRAWING_MST_OFFSET (RGA_LINE_DRAWING_MST-0x100) //repeat\r
+\r
+#define RGA_DST_VIR_INFO_OFFSET (RGA_DST_VIR_INFO-0x100)\r
+\r
+#define RGA_DST_CTR_INFO_OFFSET (RGA_DST_CTR_INFO-0x100)\r
+#define RGA_LINE_DRAW_XY_INFO_OFFSET (RGA_LINE_DRAW_XY_INFO-0x100) //repeat \r
+\r
+#define RGA_ALPHA_CON_OFFSET (RGA_ALPHA_CON-0x100)\r
+\r
+#define RGA_PAT_CON_OFFSET (RGA_PAT_CON-0x100)\r
+#define RGA_LINE_DRAWING_WIDTH_OFFSET (RGA_DST_VIR_WIDTH_PIX-0x100) //repeat\r
+\r
+#define RGA_ROP_CON0_OFFSET (RGA_ROP_CON0-0x100)\r
+#define RGA_CP_GR_G_OFFSET (RGA_CP_GR_G-0x100) //repeat\r
+#define RGA_PRESCL_CB_MST_OFFSET (RGA_PRESCL_CB_MST-0x100) //repeat\r
+\r
+#define RGA_ROP_CON1_OFFSET (RGA_ROP_CON1-0x100)\r
+#define RGA_CP_GR_R_OFFSET (RGA_CP_GR_R-0x100) //repeat\r
+#define RGA_PRESCL_CR_MST_OFFSET (RGA_PRESCL_CR_MST-0x100) //repeat\r
+\r
+#define RGA_FADING_CON_OFFSET (RGA_FADING_CON-0x100)\r
+#define RGA_MMU_TLB_OFFSET (RGA_MMU_CTRL-0x100)\r
+\r
+\r
+void matrix_cal(const struct rga_req *msg, TILE_INFO *tile);\r
+\r
+\r
+unsigned int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base);\r
+uint8_t RGA_pixel_width_init(uint32_t format);\r
+\r
+\r
+\r
+/*\r
+u8 RGA_pixel_width_init(u32 format);\r
+void dst_ctrl_cal(msg_t *msg, TILE_INFO *tile);\r
+void src_tile_info_cal(msg_t *msg, TILE_INFO *tile);\r
+void RGA_set_mode_ctrl(u8 *base, msg_t *msg);\r
+void RGA_set_src(u8 *base, msg_t *msg, TILE_INFO *tile);\r
+s32 RGA_set_dst(u8 *base, msg_t *msg);\r
+void RGA_set_alpha_rop(u8 *base, msg_t *msg);\r
+void RGA_set_color(u8 *base, msg_t *msg);\r
+s32 RGA_set_fading(u8 *base, msg_t *msg);\r
+s32 RGA_set_pat(u8 *base, msg_t *msg);\r
+void RGA_set_bitblt_reg_info(u8 *base, msg_t * msg, TILE_INFO *tile);\r
+void RGA_set_color_palette_reg_info(u8 *base, msg_t *msg);\r
+void RGA_set_color_fill_reg_info(u8 *base, msg_t *msg);\r
+s32 RGA_set_line_drawing_reg_info(u8 *base, msg_t *msg);\r
+s32 RGA_set_filter_reg_info(u8 *base, msg_t *msg);\r
+s32 RGA_set_pre_scale_reg_info(u8 *base, msg_t *msg);\r
+s32 RGA_set_update_palette_table_reg_info(u8 *base, msg_t *msg);\r
+s32 RGA_set_update_patten_buff_reg_info(u8 *base, msg_t *msg);\r
+s32 RGA_set_mmu_ctrl_reg_info(u8 *base, msg_t *msg);\r
+*/\r
--- /dev/null
+#ifndef __RGA_ROP_H__\r
+#define __RGA_ROP_H__\r
+\r
+#include "rga_type.h"\r
+\r
+UWORD32 ROP3_code[256] = \r
+{\r
+ 0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0\r
+ 0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,\r
+\r
+ 0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1 \r
+ 0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,\r
+\r
+ 0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2\r
+ 0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,\r
+\r
+ 0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3\r
+ 0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,\r
+\r
+ 0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4\r
+ 0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,\r
+\r
+ 0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,\r
+ 0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5\r
+\r
+ 0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,\r
+ 0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6\r
+\r
+ 0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,\r
+ 0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7\r
+ \r
+ 0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0, \r
+ 0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8\r
+\r
+ 0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,\r
+ 0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9\r
+\r
+ 0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,\r
+ 0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a\r
+\r
+ 0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,\r
+ 0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b\r
+\r
+ 0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,\r
+ 0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c\r
+\r
+ 0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,\r
+ 0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d\r
+\r
+ 0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,\r
+ 0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e\r
+\r
+ 0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,\r
+ 0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f\r
+};\r
+\r
+#endif\r
--- /dev/null
+#ifndef __RGA_TYPE_H__\r
+#define __RGA_TYPE_H__\r
+\r
+\r
+#ifdef __cplusplus\r
+#if __cplusplus\r
+}\r
+#endif\r
+#endif /* __cplusplus */\r
+\r
+typedef unsigned int UWORD32;\r
+typedef unsigned int uint32;\r
+typedef unsigned int RK_U32;\r
+\r
+typedef unsigned short UWORD16;\r
+typedef unsigned short RK_U16;\r
+\r
+typedef unsigned char UBYTE;\r
+typedef unsigned char RK_U8;\r
+\r
+typedef int WORD32;\r
+typedef int RK_S32;\r
+\r
+typedef short WORD16;\r
+typedef short RK_S16;\r
+\r
+typedef char BYTE;\r
+typedef char RK_S8;\r
+\r
+\r
+#ifndef NULL\r
+#define NULL 0L\r
+#endif\r
+\r
+#ifndef TRUE\r
+#define TRUE 1L\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+#if __cplusplus\r
+}\r
+#endif\r
+#endif /* __cplusplus */\r
+\r
+\r
+#endif /* __RGA_TYPR_H__ */\r
+\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff