Pass i64 values correctly split in reg/mem to fastcc calls.

This fixes fourinarow with -enable-x86-fastcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22022 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 66bbe6f5aaf6e59e75424f52ae3efe27abf9e75c..4c77ff647cb4b35909c9411b024f5f612fd4a84e 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -750,8 +750,7 @@ X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
           SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
           PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
           Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                       Args[i].first, PtrOff,
-                                       DAG.getSrcValue(NULL)));
+                                       Hi, PtrOff, DAG.getSrcValue(NULL)));
           ArgOffset += 4;
         }
         break;