Rename SelectionDAGISel's FastISel to Fast, to begin to make

room for the new FastISel instruction selection code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54749 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 804ccf3e59077caec7e4a0639785ca82fa74cc59..7471039477041e037b71f2f7f80fbf5ef22dccd6 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -42,12 +42,12 @@ public:
   MachineBasicBlock *BB;
   AliasAnalysis *AA;
   CollectorMetadata *GCI;
-  bool FastISel;
+  bool Fast;
   std::vector<SDNode*> TopOrder;
   static char ID;
 
   explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) : 
-    FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), FastISel(fast), DAGSize(0) {}
+    FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), Fast(fast), DAGSize(0) {}
   
   TargetLowering &getTargetLowering() { return TLI; }
 

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index d1c49d00eed2529cf2789f38baf85ad93d27daf4..815fdb7cc748e4e173d730b44f27e10bd8880fe5 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5379,7 +5379,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
 
   if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
   
-  if (!FastISel && EnableValueProp)
+  if (!Fast && EnableValueProp)
     ComputeLiveOutVRegInfo(DAG);
 
   // Third, instruction select all of the operations to machine code, adding the
@@ -5448,7 +5448,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
     BasicBlock *LLVMBB = &*I;
     PHINodesToUpdate.clear();
 
-    if (!FastISel || !SISel.SelectBasicBlock(LLVMBB,  FuncInfo.MBBMap[LLVMBB]))
+    if (!Fast || !SISel.SelectBasicBlock(LLVMBB,  FuncInfo.MBBMap[LLVMBB]))
       SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
     FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
   }
@@ -5696,7 +5696,7 @@ ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
     RegisterScheduler::setDefault(Ctor);
   }
   
-  ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
+  ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast);
   Scheduler->Run();
 
   return Scheduler;