ARM: dts: zynq: Enable PL clocks for Parallella
authorAndreas Färber <afaerber@suse.de>
Thu, 6 Nov 2014 17:22:10 +0000 (18:22 +0100)
committerOlof Johansson <olof@lixom.net>
Sun, 9 Nov 2014 00:57:44 +0000 (16:57 -0800)
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.

Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.

Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.

Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
arch/arm/boot/dts/zynq-parallella.dts

index e1f51ca127fe835664f0609b19a1ef428de62ca8..0429bbd89fba78ab2da1fbc831b7fa0118acbf4d 100644 (file)
        };
 };
 
+&clkc {
+       fclk-enable = <0xf>;
+};
+
 &gem0 {
        status = "okay";
        phy-mode = "rgmii-id";