Handle lshr for i128 correctly on SPU also when

shiftamount > 7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120288 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 6e06e47c49631fecc9985106f716553d216674fb..4095951c24c39eda8a9e7b2d7145576593f3bc51 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -2727,6 +2727,8 @@ multiclass RotateMaskQuadByBitCount
   def v8i16: ROTQMBYBIVecInst<v8i16>;
   def v4i32: ROTQMBYBIVecInst<v4i32>;
   def v2i64: ROTQMBYBIVecInst<v2i64>;
+  def r128: ROTQMBYBIInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
+                           [/*no pattern*/]>;
 }
 
 defm ROTQMBYBI: RotateMaskQuadByBitCount;
@@ -2762,8 +2764,9 @@ multiclass RotateMaskQuadByBits
 defm ROTQMBI: RotateMaskQuadByBits;
 
 def : Pat<(srl GPRC:$rA, R32C:$rB),
-          (ROTQMBIr128  GPRC:$rA, 
-                        (SFIr32 R32C:$rB, 0))>;
+          (ROTQMBYBIr128 (ROTQMBIr128  GPRC:$rA, 
+                                       (SFIr32 R32C:$rB, 0)),
+                         (SFIr32 R32C:$rB, 0))>;
 
 
 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~

diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll
index 0264fc830ea845fcf5c8746c08a2fabd9f689214..9dffb98a2345aaf3caea5d0907f20129d31d8a76 100644 (file)
--- a/test/CodeGen/CellSPU/shift_ops.ll
+++ b/test/CodeGen/CellSPU/shift_ops.ll
@@ -10,11 +10,12 @@
 ; RUN: grep {rotqmbyi  }  %t1.s | count 1
 ; RUN: grep {rotqmbii  }  %t1.s | count 2
 ; RUN: grep {rotqmby   }  %t1.s | count 1
-; RUN: grep {rotqmbi   }  %t1.s | count 1
+; RUN: grep {rotqmbi   }  %t1.s | count 2
 ; RUN: grep {rotqbyi   }  %t1.s | count 1
 ; RUN: grep {rotqbii   }  %t1.s | count 2
 ; RUN: grep {rotqbybi  }  %t1.s | count 1
-; RUN: grep {sfi       }  %t1.s | count 3
+; RUN: grep {sfi       }  %t1.s | count 4
+; RUN: cat %t1.s | FileCheck %s
 
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
@@ -281,3 +282,14 @@ define i32 @hi32_i64(i64 %arg) {
        %2 = trunc i64 %1 to i32
        ret i32 %2
 }
+
+; some random tests
+define i128 @test_lshr_i128( i128 %val ) {
+       ;CHECK: test_lshr_i128
+       ;CHECK: sfi
+       ;CHECK: rotqmbi
+       ;CHECK: rotqmbybi
+       ;CHECK: bi $lr
+       %rv = lshr i128 %val, 64
+       ret i128 %rv
+}