Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this:

        vspltisw v2, -12
        vrlw v2, v2, v2

instead of:

        vspltisw v0, -12
        vrlw v2, v0, v0

when a function is returning a value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27771 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 4f56cf74e54ff0c90971854e79b78f323e5ff1bd..9cd21452268b4df662c5af19142026b7b9c1b67c 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -260,7 +260,7 @@ def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
   F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
 
 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
- [V0, V1, V2, V3, V4, V5,
+ [V2, V3, V4, V5, V0, V1, 
   V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V20, V21,
   V22, V23, V24, V25, V26, V27, V28, V29, V30, V31]>;