rk29: clock: default codec pll rate set to 445.5MHz, auto set dclk_lcdc rate

diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c
index d72089d2694d6efd7ba0cea7632aa3226e37ee18..de4bfb85b062c87ebb1d1f5c33ca23933aa46516 100755 (executable)
--- a/arch/arm/mach-rk29/clock.c
+++ b/arch/arm/mach-rk29/clock.c
@@ -551,26 +551,27 @@ struct codec_pll_set {
        u32 parent_con;
 };
 
-#define CODEC_PLL(_mhz, _parent, band, nr, nf, no) \
+#define CODEC_PLL(_khz, _parent, band, nr, nf, no) \
 { \
-       .rate           = _mhz * MHZ, \
+       .rate           = _khz * KHZ, \
        .pll_con        = PLL_##band##_BAND | PLL_CLKR(nr) | PLL_CLKF(nf) | PLL_NO_##no, \
        .parent_con     = CODEC_PLL_PARENT_XIN##_parent##M, \
 }
 
 static const struct codec_pll_set codec_pll[] = {
-       //      rate parent band NR NF NO
-       CODEC_PLL(108, 24,  LOW, 1, 18, 4),     // for TV
-       CODEC_PLL(648, 24, HIGH, 1, 27, 1),
-       CODEC_PLL(297, 27,  LOW, 1, 22, 2),     // for HDMI
-       CODEC_PLL(594, 27, HIGH, 1, 22, 1),
-       CODEC_PLL(300, 24,  LOW, 1, 25, 2),     // for GPU
-       CODEC_PLL(360, 24,  LOW, 1, 15, 1),
-       CODEC_PLL(408, 24,  LOW, 1, 17, 1),
-       CODEC_PLL(456, 24,  LOW, 1, 19, 1),
-       CODEC_PLL(504, 24,  LOW, 1, 21, 1),
-       CODEC_PLL(552, 24,  LOW, 1, 23, 1),
-       CODEC_PLL(600, 24, HIGH, 1, 25, 1),
+       //        rate parent band NR  NF NO
+       CODEC_PLL(108000, 24,  LOW, 1, 18, 4),  // for TV
+       CODEC_PLL(648000, 24, HIGH, 1, 27, 1),
+       CODEC_PLL(297000, 27,  LOW, 1, 22, 2),  // for HDMI
+       CODEC_PLL(445500, 27,  LOW, 2, 33, 1),
+       CODEC_PLL(594000, 27, HIGH, 1, 22, 1),
+       CODEC_PLL(300000, 24,  LOW, 1, 25, 2),  // for GPU
+       CODEC_PLL(360000, 24,  LOW, 1, 15, 1),
+       CODEC_PLL(408000, 24,  LOW, 1, 17, 1),
+       CODEC_PLL(456000, 24,  LOW, 1, 19, 1),
+       CODEC_PLL(504000, 24,  LOW, 1, 21, 1),
+       CODEC_PLL(552000, 24,  LOW, 1, 23, 1),
+       CODEC_PLL(600000, 24, HIGH, 1, 25, 1),
 };
 
 static int codec_pll_clk_set_rate(struct clk *clk, unsigned long rate)
@@ -1013,7 +1014,7 @@ static struct clk clk_spdif_frac_div = {
 
 static int i2s_set_rate(struct clk *clk, unsigned long rate)
 {
-       int ret;
+       int ret = 0;
        struct clk *parent;
 
        if (rate == 12 * MHZ) {
@@ -1025,7 +1026,7 @@ static int i2s_set_rate(struct clk *clk, unsigned long rate)
                        return ret;
        }
        if (clk->parent != parent)
-               clk_set_parent_nolock(clk, parent);
+               ret = clk_set_parent_nolock(clk, parent);
 
        return ret;
 }
@@ -1227,7 +1228,7 @@ static struct clk clk_ddr = {
 
 static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
 {
-       int ret;
+       int ret = 0;
        struct clk *parent;
        struct clk *clk_div = clk->parents[0];
 
@@ -1260,9 +1261,9 @@ static int clk_uart_set_rate(struct clk *clk, unsigned long rate)
        }
 
        if (clk->parent != parent)
-               clk_set_parent_nolock(clk, parent);
+               ret = clk_set_parent_nolock(clk, parent);
 
-       return 0;
+       return ret;
 }
 
 static int clk_uart_frac_div_set_rate(struct clk *clk, unsigned long rate)
@@ -1510,12 +1511,34 @@ static struct clk clk_hsadc_out = {
 };
 
 
+static int dclk_lcdc_div_set_rate(struct clk *clk, unsigned long rate)
+{
+       struct clk *parent;
+
+       switch (rate) {
+       case 27000 * KHZ:
+       case 74250 * KHZ:
+       case 148500 * KHZ:
+       case 297 * MHZ:
+       case 594 * MHZ:
+               parent = &codec_pll_clk;
+               break;
+       default:
+               parent = &general_pll_clk;
+               break;
+       }
+       if (clk->parent != parent)
+               clk_set_parent_nolock(clk, parent);
+
+       return clksel_set_rate_div(clk, rate);
+}
+
 static struct clk *dclk_lcdc_div_parents[4] = { &codec_pll_clk, &ddr_pll_clk, &general_pll_clk, &arm_pll_clk };
 
 static struct clk dclk_lcdc_div = {
        .name           = "dclk_lcdc_div",
        .recalc         = clksel_recalc_div,
-       .set_rate       = clksel_set_rate_div,
+       .set_rate       = dclk_lcdc_div_set_rate,
        .clksel_con     = CRU_CLKSEL16_CON,
        .clksel_mask    = 0xFF,
        .clksel_shift   = 2,
@@ -1524,11 +1547,31 @@ static struct clk dclk_lcdc_div = {
        .parents        = dclk_lcdc_div_parents,
 };
 
+static int dclk_lcdc_set_rate(struct clk *clk, unsigned long rate)
+{
+       int ret = 0;
+       struct clk *parent;
+
+       if (rate == 27 * MHZ && has_xin27m) {
+               parent = &xin27m;
+       } else {
+               parent = &dclk_lcdc_div;
+               ret = clk_set_rate_nolock(parent, rate);
+               if (ret)
+                       return ret;
+       }
+       if (clk->parent != parent)
+               ret = clk_set_parent_nolock(clk, parent);
+
+       return ret;
+}
+
 static struct clk *dclk_lcdc_parents[2] = { &dclk_lcdc_div, &xin27m };
 
 static struct clk dclk_lcdc = {
        .name           = "dclk_lcdc",
        .mode           = gate_mode,
+       .set_rate       = dclk_lcdc_set_rate,
        .gate_idx       = CLK_GATE_DCLK_LCDC,
        .clksel_con     = CRU_CLKSEL16_CON,
        .clksel_parent_mask     = 1,
@@ -2461,6 +2504,8 @@ static void __init rk29_clock_common_init(unsigned long ppll_rate, unsigned long
        clk_set_parent_nolock(&clk_i2s1_div, &general_pll_clk);
        clk_set_parent_nolock(&clk_spdif_div, &general_pll_clk);
        clk_set_parent_nolock(&clk_spi_src, &general_pll_clk);
+       clk_set_rate_nolock(&clk_spi0, 40 * MHZ);
+       clk_set_rate_nolock(&clk_spi1, 40 * MHZ);
        clk_set_parent_nolock(&clk_mmc_src, &general_pll_clk);
        clk_set_parent_nolock(&clk_uart01_src, &general_pll_clk);
        clk_set_parent_nolock(&clk_uart23_src, &general_pll_clk);
@@ -2561,14 +2606,14 @@ void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate
 
        rk29_clock_common_init(ppll_rate, cpll_rate);
 
-       printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz\n",
+       printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz (20110617)\n",
               arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
               aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
 }
 
 void __init rk29_clock_init(enum periph_pll ppll_rate)
 {
-       rk29_clock_init2(ppll_rate, codec_pll_594mhz, true);
+       rk29_clock_init2(ppll_rate, codec_pll_445mhz, true);
 }
 
 #ifdef CONFIG_PROC_FS

diff --git a/arch/arm/mach-rk29/include/mach/board.h b/arch/arm/mach-rk29/include/mach/board.h
index dd37bf2f45f48410f4a79e2a07aad1d6b3dd3fed..ea78e534ec017358b159b1398965dbdbddb85506 100755 (executable)
--- a/arch/arm/mach-rk29/include/mach/board.h
+++ b/arch/arm/mach-rk29/include/mach/board.h
@@ -274,12 +274,14 @@ enum periph_pll {
 enum codec_pll {
        codec_pll_297mhz = 297000000, /* for HDMI */
        codec_pll_300mhz = 300000000,
+       codec_pll_445mhz = 445500000, /* for HDMI */
+       codec_pll_504mhz = 504000000,
        codec_pll_552mhz = 552000000,
        codec_pll_594mhz = 594000000, /* for HDMI */
        codec_pll_600mhz = 600000000,
 };
 
-void __init rk29_clock_init(enum periph_pll ppll_rate);
+void __init rk29_clock_init(enum periph_pll ppll_rate); /* codec pll is 445.5MHz, has xin27m */
 void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate, bool has_xin27m);
 
 /* for USB detection */

diff --git a/drivers/video/rk29_fb.c b/drivers/video/rk29_fb.c
index b483e21999735d7a1790c5d29d5cdd632150913d..aa8b9e0c06e66285ea338172f9f0c347559126be 100755 (executable)
--- a/drivers/video/rk29_fb.c
+++ b/drivers/video/rk29_fb.c
@@ -188,8 +188,6 @@ struct rk29fb_inf {
 
     struct clk      *clk;
     struct clk      *dclk;            //lcdc dclk
-    struct clk      *dclk_parent;     //lcdc dclk divider frequency source
-    struct clk      *dclk_divider;    //lcdc demodulator divider frequency
     struct clk      *aclk;   //lcdc share memory frequency
     struct clk      *aclk_parent;     //lcdc aclk divider frequency source
     struct clk      *aclk_ddr_lcdc;   //DDR LCDC AXI clock disable.
@@ -599,24 +597,6 @@ void load_screen(struct fb_info *info, bool initscreen)
         printk(KERN_ERR "failed to get lcd dclock source\n");
         return ;
     }
-    inf->dclk_divider= clk_get(NULL, "dclk_lcdc_div");
-    if (IS_ERR(inf->dclk_divider))
-    {
-        printk(KERN_ERR "failed to get lcd clock lcdc_divider source \n");
-               return ;
-    }
-
-    if((inf->cur_screen->type == SCREEN_HDMI) || (inf->cur_screen->type == SCREEN_TVOUT)){
-        inf->dclk_parent = clk_get(NULL, "codec_pll");
-    }    else    {
-        inf->dclk_parent = clk_get(NULL, "general_pll");
-    }
-
-    if (IS_ERR(inf->dclk_parent))
-    {
-        printk(KERN_ERR "failed to get lcd dclock parent source\n");
-        return;
-    }
 
     inf->aclk = clk_get(NULL, "aclk_lcdc");
     if (IS_ERR(inf->aclk))
@@ -625,9 +605,9 @@ void load_screen(struct fb_info *info, bool initscreen)
         return;
     }
     inf->aclk_parent = clk_get(NULL, "ddr_pll");//general_pll //ddr_pll
-    if (IS_ERR(inf->dclk_parent))
+    if (IS_ERR(inf->aclk_parent))
     {
-        printk(KERN_ERR "failed to get lcd dclock parent source\n");
+        printk(KERN_ERR "failed to get lcd clock parent source\n");
         return ;
     }
 
@@ -645,16 +625,14 @@ void load_screen(struct fb_info *info, bool initscreen)
     clk_disable(inf->hclk_cpu_display);
 
     clk_disable(inf->clk);
-    clk_set_parent(inf->dclk_divider, inf->dclk_parent);
-    clk_set_parent(inf->dclk, inf->dclk_divider);
     ret = clk_set_parent(inf->aclk, inf->aclk_parent);
 
     fbprintk(">>>>>> set lcdc dclk need %d HZ, clk_parent = %d hz ret =%d\n ", screen->pixclock, screen->lcdc_aclk, ret);
 
-    ret = clk_set_rate(inf->dclk_divider, screen->pixclock);
+    ret = clk_set_rate(inf->dclk, screen->pixclock);
     if(ret)
     {
-        printk(KERN_ERR ">>>>>> set lcdc dclk_divider faild \n ");
+        printk(KERN_ERR ">>>>>> set lcdc dclk failed\n");
     }
 
     if(screen->lcdc_aclk){
@@ -662,7 +640,7 @@ void load_screen(struct fb_info *info, bool initscreen)
     }
     ret = clk_set_rate(inf->aclk, aclk_rate);
     if(ret){
-        printk(KERN_ERR ">>>>>> set lcdc dclk_divider faild \n ");
+        printk(KERN_ERR ">>>>>> set lcdc aclk failed\n");
     }
 
     clk_enable(inf->aclk_ddr_lcdc);
@@ -1793,7 +1771,7 @@ static int fb1_set_par(struct fb_info *info)
        CHK_SUSPEND(inf);
     if((var->rotate == 270)||(var->rotate == 90))
     {
-        #if CONFIG_FB_ROTATE_VIDEO
+        #ifdef CONFIG_FB_ROTATE_VIDEO
         xpos = (var->nonstd>>20) & 0xfff;      //visiable pos in panel
         ypos = (var->nonstd>>8) & 0xfff;
         xsize = (var->grayscale>>20) & 0xfff;  //visiable size in panel
@@ -1885,7 +1863,7 @@ static int fb1_set_par(struct fb_info *info)
     }
     wq_condition2 = 0;
 
-#if CONFIG_FB_ROTATE_VIDEO
+#ifdef CONFIG_FB_ROTATE_VIDEO
 //need refresh ,zyc add                
        if((has_set_rotate == true) && (last_yuv_phy[0] != 0) && (last_yuv_phy[1] != 0))
        {
@@ -1986,7 +1964,7 @@ int fb1_open(struct fb_info *info, int user)
     par->addr_seted = 0;
     inf->video_mode = 1;
     wq_condition2 = 1;
-#if CONFIG_FB_ROTATE_VIDEO
+#ifdef CONFIG_FB_ROTATE_VIDEO
    //reinitialize  the var when open,zyc
     last_yuv_phy[0] = 0;
     last_yuv_phy[1] = 0;