drm/nouveau/sec: separate from cipher (formerly crypt)
authorBen Skeggs <bskeggs@redhat.com>
Wed, 14 Jan 2015 00:46:55 +0000 (10:46 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Thu, 22 Jan 2015 02:17:44 +0000 (12:17 +1000)
Switch to NVIDIA's name for the device.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
26 files changed:
drivers/gpu/drm/nouveau/include/nvif/class.h
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h [deleted file]
drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c [deleted file]
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c [new file with mode: 0644]
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv84.c
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c

index 6ed8ecca8dbf01640556bbe13177081840ac9c78..d5da658d9d43afd63f3b242c3c3cba264ef51d53 100644 (file)
@@ -126,7 +126,7 @@ struct nv_device_v0 {
 #define NV_DEVICE_V0_DISABLE_MPEG                         0x0000000200000000ULL
 #define NV_DEVICE_V0_DISABLE_ME                           0x0000000400000000ULL
 #define NV_DEVICE_V0_DISABLE_VP                           0x0000000800000000ULL
-#define NV_DEVICE_V0_DISABLE_CRYPT                        0x0000001000000000ULL
+#define NV_DEVICE_V0_DISABLE_CIPHER                       0x0000001000000000ULL
 #define NV_DEVICE_V0_DISABLE_BSP                          0x0000002000000000ULL
 #define NV_DEVICE_V0_DISABLE_PPP                          0x0000004000000000ULL
 #define NV_DEVICE_V0_DISABLE_COPY0                        0x0000008000000000ULL
@@ -135,6 +135,7 @@ struct nv_device_v0 {
 #define NV_DEVICE_V0_DISABLE_VENC                         0x0000040000000000ULL
 #define NV_DEVICE_V0_DISABLE_COPY2                        0x0000080000000000ULL
 #define NV_DEVICE_V0_DISABLE_MSVLD                        0x0000100000000000ULL
+#define NV_DEVICE_V0_DISABLE_SEC                          0x0000200000000000ULL
        __u64 disable;  /* disable particular subsystems */
        __u64 debug0;   /* as above, but *internal* ids, and *NOT* ABI */
 };
index 7205d07f5cc95509b989ce1670c7a78969b514a1..cefa8774e11c0ef446af8968fec1b7869e07fdc1 100644 (file)
@@ -49,7 +49,7 @@ enum nv_subdev_type {
        NVDEV_ENGINE_MPEG,
        NVDEV_ENGINE_ME,
        NVDEV_ENGINE_VP,
-       NVDEV_ENGINE_CRYPT,
+       NVDEV_ENGINE_CIPHER,
        NVDEV_ENGINE_BSP,
        NVDEV_ENGINE_PPP,
        NVDEV_ENGINE_COPY0,
@@ -60,6 +60,7 @@ enum nv_subdev_type {
        NVDEV_ENGINE_DISP,
        NVDEV_ENGINE_PERFMON,
        NVDEV_ENGINE_MSVLD,
+       NVDEV_ENGINE_SEC,
 
        NVDEV_SUBDEV_NR,
 };
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/cipher.h
new file mode 100644 (file)
index 0000000..813bca3
--- /dev/null
@@ -0,0 +1,4 @@
+#ifndef __NVKM_CIPHER_H__
+#define __NVKM_CIPHER_H__
+extern struct nouveau_oclass nv84_cipher_oclass;
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/crypt.h
deleted file mode 100644 (file)
index db97561..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __NOUVEAU_CRYPT_H__
-#define __NOUVEAU_CRYPT_H__
-
-extern struct nouveau_oclass nv84_crypt_oclass;
-extern struct nouveau_oclass nv98_crypt_oclass;
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/sec.h
new file mode 100644 (file)
index 0000000..32cd4cb
--- /dev/null
@@ -0,0 +1,4 @@
+#ifndef __NVKM_SEC_H__
+#define __NVKM_SEC_H__
+extern struct nouveau_oclass nv98_sec_oclass;
+#endif
index b410eb1e2228785c2741026e7ab645aeb05e936f..aad171d3cbccf0324c4ce001f46069d1de0fd5c0 100644 (file)
@@ -2,8 +2,8 @@ nvkm-y += nvkm/engine/falcon.o
 nvkm-y += nvkm/engine/xtensa.o
 
 include $(src)/nvkm/engine/bsp/Kbuild
+include $(src)/nvkm/engine/cipher/Kbuild
 include $(src)/nvkm/engine/copy/Kbuild
-include $(src)/nvkm/engine/crypt/Kbuild
 include $(src)/nvkm/engine/device/Kbuild
 include $(src)/nvkm/engine/disp/Kbuild
 include $(src)/nvkm/engine/dmaobj/Kbuild
@@ -13,5 +13,6 @@ include $(src)/nvkm/engine/mpeg/Kbuild
 include $(src)/nvkm/engine/msvld/Kbuild
 include $(src)/nvkm/engine/perfmon/Kbuild
 include $(src)/nvkm/engine/ppp/Kbuild
+include $(src)/nvkm/engine/sec/Kbuild
 include $(src)/nvkm/engine/software/Kbuild
 include $(src)/nvkm/engine/vp/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/Kbuild
new file mode 100644 (file)
index 0000000..07cc215
--- /dev/null
@@ -0,0 +1 @@
+nvkm-y += nvkm/engine/cipher/nv84.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/nv84.c
new file mode 100644 (file)
index 0000000..d4ecd91
--- /dev/null
@@ -0,0 +1,188 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <core/client.h>
+#include <core/os.h>
+#include <core/enum.h>
+#include <core/engctx.h>
+#include <core/gpuobj.h>
+
+#include <subdev/fb.h>
+
+#include <engine/fifo.h>
+#include <engine/cipher.h>
+
+struct nv84_cipher_priv {
+       struct nouveau_engine base;
+};
+
+/*******************************************************************************
+ * Crypt object classes
+ ******************************************************************************/
+
+static int
+nv84_cipher_object_ctor(struct nouveau_object *parent,
+                      struct nouveau_object *engine,
+                      struct nouveau_oclass *oclass, void *data, u32 size,
+                      struct nouveau_object **pobject)
+{
+       struct nouveau_gpuobj *obj;
+       int ret;
+
+       ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
+                                   16, 16, 0, &obj);
+       *pobject = nv_object(obj);
+       if (ret)
+               return ret;
+
+       nv_wo32(obj, 0x00, nv_mclass(obj));
+       nv_wo32(obj, 0x04, 0x00000000);
+       nv_wo32(obj, 0x08, 0x00000000);
+       nv_wo32(obj, 0x0c, 0x00000000);
+       return 0;
+}
+
+static struct nouveau_ofuncs
+nv84_cipher_ofuncs = {
+       .ctor = nv84_cipher_object_ctor,
+       .dtor = _nouveau_gpuobj_dtor,
+       .init = _nouveau_gpuobj_init,
+       .fini = _nouveau_gpuobj_fini,
+       .rd32 = _nouveau_gpuobj_rd32,
+       .wr32 = _nouveau_gpuobj_wr32,
+};
+
+static struct nouveau_oclass
+nv84_cipher_sclass[] = {
+       { 0x74c1, &nv84_cipher_ofuncs },
+       {}
+};
+
+/*******************************************************************************
+ * PCIPHER context
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv84_cipher_cclass = {
+       .handle = NV_ENGCTX(CIPHER, 0x84),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = _nouveau_engctx_ctor,
+               .dtor = _nouveau_engctx_dtor,
+               .init = _nouveau_engctx_init,
+               .fini = _nouveau_engctx_fini,
+               .rd32 = _nouveau_engctx_rd32,
+               .wr32 = _nouveau_engctx_wr32,
+       },
+};
+
+/*******************************************************************************
+ * PCIPHER engine/subdev functions
+ ******************************************************************************/
+
+static const struct nouveau_bitfield nv84_cipher_intr_mask[] = {
+       { 0x00000001, "INVALID_STATE" },
+       { 0x00000002, "ILLEGAL_MTHD" },
+       { 0x00000004, "ILLEGAL_CLASS" },
+       { 0x00000080, "QUERY" },
+       { 0x00000100, "FAULT" },
+       {}
+};
+
+static void
+nv84_cipher_intr(struct nouveau_subdev *subdev)
+{
+       struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
+       struct nouveau_engine *engine = nv_engine(subdev);
+       struct nouveau_object *engctx;
+       struct nv84_cipher_priv *priv = (void *)subdev;
+       u32 stat = nv_rd32(priv, 0x102130);
+       u32 mthd = nv_rd32(priv, 0x102190);
+       u32 data = nv_rd32(priv, 0x102194);
+       u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff;
+       int chid;
+
+       engctx = nouveau_engctx_get(engine, inst);
+       chid   = pfifo->chid(pfifo, engctx);
+
+       if (stat) {
+               nv_error(priv, "%s", "");
+               nouveau_bitfield_print(nv84_cipher_intr_mask, stat);
+               pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
+                      chid, (u64)inst << 12, nouveau_client_name(engctx),
+                      mthd, data);
+       }
+
+       nv_wr32(priv, 0x102130, stat);
+       nv_wr32(priv, 0x10200c, 0x10);
+
+       nouveau_engctx_put(engctx);
+}
+
+static int
+nv84_cipher_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+              struct nouveau_oclass *oclass, void *data, u32 size,
+              struct nouveau_object **pobject)
+{
+       struct nv84_cipher_priv *priv;
+       int ret;
+
+       ret = nouveau_engine_create(parent, engine, oclass, true,
+                                   "PCIPHER", "cipher", &priv);
+       *pobject = nv_object(priv);
+       if (ret)
+               return ret;
+
+       nv_subdev(priv)->unit = 0x00004000;
+       nv_subdev(priv)->intr = nv84_cipher_intr;
+       nv_engine(priv)->cclass = &nv84_cipher_cclass;
+       nv_engine(priv)->sclass = nv84_cipher_sclass;
+       return 0;
+}
+
+static int
+nv84_cipher_init(struct nouveau_object *object)
+{
+       struct nv84_cipher_priv *priv = (void *)object;
+       int ret;
+
+       ret = nouveau_engine_init(&priv->base);
+       if (ret)
+               return ret;
+
+       nv_wr32(priv, 0x102130, 0xffffffff);
+       nv_wr32(priv, 0x102140, 0xffffffbf);
+       nv_wr32(priv, 0x10200c, 0x00000010);
+       return 0;
+}
+
+struct nouveau_oclass
+nv84_cipher_oclass = {
+       .handle = NV_ENGINE(CIPHER, 0x84),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = nv84_cipher_ctor,
+               .dtor = _nouveau_engine_dtor,
+               .init = nv84_cipher_init,
+               .fini = _nouveau_engine_fini,
+       },
+};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/Kbuild
deleted file mode 100644 (file)
index eaeafdf..0000000
+++ /dev/null
@@ -1,2 +0,0 @@
-nvkm-y += nvkm/engine/crypt/nv84.o
-nvkm-y += nvkm/engine/crypt/nv98.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s
deleted file mode 100644 (file)
index 629da02..0000000
+++ /dev/null
@@ -1,698 +0,0 @@
-/*
- *  fuc microcode for nv98 pcrypt engine
- *  Copyright (C) 2010  Marcin KoÅ›cielnicki
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-.section #nv98_pcrypt_data
-
-ctx_dma:
-ctx_dma_query:         .b32 0
-ctx_dma_src:           .b32 0
-ctx_dma_dst:           .b32 0
-.equ #dma_count 3
-ctx_query_address_high:        .b32 0
-ctx_query_address_low: .b32 0
-ctx_query_counter:     .b32 0
-ctx_cond_address_high: .b32 0
-ctx_cond_address_low:  .b32 0
-ctx_cond_off:          .b32 0
-ctx_src_address_high:  .b32 0
-ctx_src_address_low:   .b32 0
-ctx_dst_address_high:  .b32 0
-ctx_dst_address_low:   .b32 0
-ctx_mode:              .b32 0
-.align 16
-ctx_key:               .skip 16
-ctx_iv:                        .skip 16
-
-.align 0x80
-swap:
-.skip 32
-
-.align 8
-common_cmd_dtable:
-.b32 #ctx_query_address_high + 0x20000 ~0xff
-.b32 #ctx_query_address_low + 0x20000 ~0xfffffff0
-.b32 #ctx_query_counter + 0x20000 ~0xffffffff
-.b32 #cmd_query_get + 0x00000 ~1
-.b32 #ctx_cond_address_high + 0x20000 ~0xff
-.b32 #ctx_cond_address_low + 0x20000 ~0xfffffff0
-.b32 #cmd_cond_mode + 0x00000 ~7
-.b32 #cmd_wrcache_flush + 0x00000 ~0
-.equ #common_cmd_max 0x88
-
-
-.align 8
-engine_cmd_dtable:
-.b32 #ctx_key + 0x0 + 0x20000 ~0xffffffff
-.b32 #ctx_key + 0x4 + 0x20000 ~0xffffffff
-.b32 #ctx_key + 0x8 + 0x20000 ~0xffffffff
-.b32 #ctx_key + 0xc + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0x0 + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0x4 + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0x8 + 0x20000 ~0xffffffff
-.b32 #ctx_iv + 0xc + 0x20000 ~0xffffffff
-.b32 #ctx_src_address_high + 0x20000 ~0xff
-.b32 #ctx_src_address_low + 0x20000 ~0xfffffff0
-.b32 #ctx_dst_address_high + 0x20000 ~0xff
-.b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0
-.b32 #crypt_cmd_mode + 0x00000 ~0xf
-.b32 #crypt_cmd_length + 0x10000 ~0x0ffffff0
-.equ #engine_cmd_max 0xce
-
-.align 4
-crypt_dtable:
-.b16 #crypt_copy_prep #crypt_do_inout
-.b16 #crypt_store_prep #crypt_do_out
-.b16 #crypt_ecb_e_prep #crypt_do_inout
-.b16 #crypt_ecb_d_prep #crypt_do_inout
-.b16 #crypt_cbc_e_prep #crypt_do_inout
-.b16 #crypt_cbc_d_prep #crypt_do_inout
-.b16 #crypt_pcbc_e_prep #crypt_do_inout
-.b16 #crypt_pcbc_d_prep #crypt_do_inout
-.b16 #crypt_cfb_e_prep #crypt_do_inout
-.b16 #crypt_cfb_d_prep #crypt_do_inout
-.b16 #crypt_ofb_prep #crypt_do_inout
-.b16 #crypt_ctr_prep #crypt_do_inout
-.b16 #crypt_cbc_mac_prep #crypt_do_in
-.b16 #crypt_cmac_finish_complete_prep #crypt_do_in
-.b16 #crypt_cmac_finish_partial_prep #crypt_do_in
-
-.align 0x100
-
-.section #nv98_pcrypt_code
-
-       // $r0 is always set to 0 in our code - this allows some space savings.
-       clear b32 $r0
-
-       // set up the interrupt handler
-       mov $r1 #ih
-       mov $iv0 $r1
-
-       // init stack pointer
-       mov $sp $r0
-
-       // set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host
-       movw $r1 0xfff0
-       sethi $r1 0
-       mov $r2 0x400
-       iowr I[$r2 + 0x300] $r1
-
-       // enable the interrupts
-       or $r1 0xc
-       iowr I[$r2] $r1
-
-       // enable fifo access and context switching
-       mov $r1 3
-       mov $r2 0x1200
-       iowr I[$r2] $r1
-
-       // enable i0 delivery
-       bset $flags ie0
-
-       // sleep forver, waking only for interrupts.
-       bset $flags $p0
-       spin:
-       sleep $p0
-       bra #spin
-
-// i0 handler
-ih:
-       // see which interrupts we got
-       iord $r1 I[$r0 + 0x200]
-
-       and $r2 $r1 0x8
-       cmpu b32 $r2 0
-       bra e #noctx
-
-               // context switch... prepare the regs for xfer
-               mov $r2 0x7700
-               mov $xtargets $r2
-               mov $xdbase $r0
-               // 128-byte context.
-               mov $r2 0
-               sethi $r2 0x50000
-
-               // read current channel
-               mov $r3 0x1400
-               iord $r4 I[$r3]
-               // if bit 30 set, it's active, so we have to unload it first.
-               shl b32 $r5 $r4 1
-               cmps b32 $r5 0
-               bra nc #ctxload
-
-                       // unload the current channel - save the context
-                       xdst $r0 $r2
-                       xdwait
-                       // and clear bit 30, then write back
-                       bclr $r4 0x1e
-                       iowr I[$r3] $r4
-                       // tell PFIFO we unloaded
-                       mov $r4 1
-                       iowr I[$r3 + 0x200] $r4
-
-               bra #noctx
-
-               ctxload:
-                       // no channel loaded - perhaps we're requested to load one
-                       iord $r4 I[$r3 + 0x100]
-                       shl b32 $r15 $r4 1
-                       cmps b32 $r15 0
-                       // if bit 30 of next channel not set, probably PFIFO is just
-                       // killing a context. do a faux load, without the active bit.
-                       bra nc #dummyload
-
-                               // ok, do a real context load.
-                               xdld $r0 $r2
-                               xdwait
-                               mov $r5 #ctx_dma
-                               mov $r6 #dma_count - 1
-                               ctxload_dma_loop:
-                                       ld b32 $r7 D[$r5 + $r6 * 4]
-                                       add b32 $r8 $r6 0x180
-                                       shl b32 $r8 8
-                                       iowr I[$r8] $r7
-                                       sub b32 $r6 1
-                               bra nc #ctxload_dma_loop
-
-                       dummyload:
-                       // tell PFIFO we're done
-                       mov $r5 2
-                       iowr I[$r3 + 0x200] $r5
-
-       noctx:
-       and $r2 $r1 0x4
-       cmpu b32 $r2 0
-       bra e #nocmd
-
-               // incoming fifo command.
-               mov $r3 0x1900
-               iord $r2 I[$r3 + 0x100]
-               iord $r3 I[$r3]
-               // extract the method
-               and $r4 $r2 0x7ff
-               // shift the addr to proper position if we need to interrupt later
-               shl b32 $r2 0x10
-
-               // mthd 0 and 0x100 [NAME, NOP]: ignore
-               and $r5 $r4 0x7bf
-               cmpu b32 $r5 0
-               bra e #cmddone
-
-               mov $r5 #engine_cmd_dtable - 0xc0 * 8
-               mov $r6 #engine_cmd_max
-               cmpu b32 $r4 0xc0
-               bra nc #dtable_cmd
-               mov $r5 #common_cmd_dtable - 0x80 * 8
-               mov $r6 #common_cmd_max
-               cmpu b32 $r4 0x80
-               bra nc #dtable_cmd
-               cmpu b32 $r4 0x60
-               bra nc #dma_cmd
-               cmpu b32 $r4 0x50
-               bra ne #illegal_mthd
-
-                       // mthd 0x140: PM_TRIGGER
-                       mov $r2 0x2200
-                       clear b32 $r3
-                       sethi $r3 0x20000
-                       iowr I[$r2] $r3
-                       bra #cmddone
-
-               dma_cmd:
-                       // mthd 0x180...: DMA_*
-                       cmpu b32 $r4 0x60+#dma_count
-                       bra nc #illegal_mthd
-                       shl b32 $r5 $r4 2
-                       add b32 $r5 ((#ctx_dma - 0x60 * 4) & 0xffff)
-                       bset $r3 0x1e
-                       st b32 D[$r5] $r3
-                       add b32 $r4 0x180 - 0x60
-                       shl b32 $r4 8
-                       iowr I[$r4] $r3
-                       bra #cmddone
-
-               dtable_cmd:
-                       cmpu b32 $r4 $r6
-                       bra nc #illegal_mthd
-                       shl b32 $r4 3
-                       add b32 $r4 $r5
-                       ld b32 $r5 D[$r4 + 4]
-                       and $r5 $r3
-                       cmpu b32 $r5 0
-                       bra ne #invalid_bitfield
-                       ld b16 $r5 D[$r4]
-                       ld b16 $r6 D[$r4 + 2]
-                       cmpu b32 $r6 2
-                       bra e #cmd_setctx
-                       ld b32 $r7 D[$r0 + #ctx_cond_off]
-                       and $r6 $r7
-                       cmpu b32 $r6 1
-                       bra e #cmddone
-                       call $r5
-                       bra $p1 #dispatch_error
-                       bra #cmddone
-
-               cmd_setctx:
-                       st b32 D[$r5] $r3
-                       bra #cmddone
-
-
-               invalid_bitfield:
-                       or $r2 1
-               dispatch_error:
-               illegal_mthd:
-                       mov $r4 0x1000
-                       iowr I[$r4] $r2
-                       iowr I[$r4 + 0x100] $r3
-                       mov $r4 0x40
-                       iowr I[$r0] $r4
-
-                       im_loop:
-                               iord $r4 I[$r0 + 0x200]
-                               and $r4 0x40
-                               cmpu b32 $r4 0
-                       bra ne #im_loop
-
-               cmddone:
-               // remove the command from FIFO
-               mov $r3 0x1d00
-               mov $r4 1
-               iowr I[$r3] $r4
-
-       nocmd:
-       // ack the processed interrupts
-       and $r1 $r1 0xc
-       iowr I[$r0 + 0x100] $r1
-iret
-
-cmd_query_get:
-       // if bit 0 of param set, trigger interrupt afterwards.
-       setp $p1 $r3
-       or $r2 3
-
-       // read PTIMER, beware of races...
-       mov $r4 0xb00
-       ptimer_retry:
-               iord $r6 I[$r4 + 0x100]
-               iord $r5 I[$r4]
-               iord $r7 I[$r4 + 0x100]
-               cmpu b32 $r6 $r7
-       bra ne #ptimer_retry
-
-       // prepare the query structure
-       ld b32 $r4 D[$r0 + #ctx_query_counter]
-       st b32 D[$r0 + #swap + 0x0] $r4
-       st b32 D[$r0 + #swap + 0x4] $r0
-       st b32 D[$r0 + #swap + 0x8] $r5
-       st b32 D[$r0 + #swap + 0xc] $r6
-
-       // will use target 0, DMA_QUERY.
-       mov $xtargets $r0
-
-       ld b32 $r4 D[$r0 + #ctx_query_address_high]
-       shl b32 $r4 0x18
-       mov $xdbase $r4
-
-       ld b32 $r4 D[$r0 + #ctx_query_address_low]
-       mov $r5 #swap
-       sethi $r5 0x20000
-       xdst $r4 $r5
-       xdwait
-
-       ret
-
-cmd_cond_mode:
-       // if >= 5, INVALID_ENUM
-       bset $flags $p1
-       or $r2 2
-       cmpu b32 $r3 5
-       bra nc #return
-
-       // otherwise, no error.
-       bclr $flags $p1
-
-       // if < 2, no QUERY object is involved
-       cmpu b32 $r3 2
-       bra nc #cmd_cond_mode_queryful
-
-               xor $r3 1
-               st b32 D[$r0 + #ctx_cond_off] $r3
-       return:
-               ret
-
-       cmd_cond_mode_queryful:
-       // ok, will need to pull a QUERY object, prepare offsets
-       ld b32 $r4 D[$r0 + #ctx_cond_address_high]
-       ld b32 $r5 D[$r0 + #ctx_cond_address_low]
-       and $r6 $r5 0xff
-       shr b32 $r5 8
-       shl b32 $r4 0x18
-       or $r4 $r5
-       mov $xdbase $r4
-       mov $xtargets $r0
-
-       // pull the first one
-       mov $r5 #swap
-       sethi $r5 0x20000
-       xdld $r6 $r5
-
-       // if == 2, only a single QUERY is involved...
-       cmpu b32 $r3 2
-       bra ne #cmd_cond_mode_double
-
-               xdwait
-               ld b32 $r4 D[$r0 + #swap + 4]
-               cmpu b32 $r4 0
-               xbit $r4 $flags z
-               st b32 D[$r0 + #ctx_cond_off] $r4
-               ret
-
-       // ok, we'll need to pull second one too
-       cmd_cond_mode_double:
-       add b32 $r6 0x10
-       add b32 $r5 0x10
-       xdld $r6 $r5
-       xdwait
-
-       // compare COUNTERs
-       ld b32 $r5 D[$r0 + #swap + 0x00]
-       ld b32 $r6 D[$r0 + #swap + 0x10]
-       cmpu b32 $r5 $r6
-       xbit $r4 $flags z
-
-       // compare RESen
-       ld b32 $r5 D[$r0 + #swap + 0x04]
-       ld b32 $r6 D[$r0 + #swap + 0x14]
-       cmpu b32 $r5 $r6
-       xbit $r5 $flags z
-       and $r4 $r5
-
-       // and negate or not, depending on mode
-       cmpu b32 $r3 3
-       xbit $r5 $flags z
-       xor $r4 $r5
-       st b32 D[$r0 + #ctx_cond_off] $r4
-       ret
-
-cmd_wrcache_flush:
-       bclr $flags $p1
-       mov $r2 0x2200
-       clear b32 $r3
-       sethi $r3 0x10000
-       iowr I[$r2] $r3
-       ret
-
-crypt_cmd_mode:
-       // if >= 0xf, INVALID_ENUM
-       bset $flags $p1
-       or $r2 2
-       cmpu b32 $r3 0xf
-       bra nc #crypt_cmd_mode_return
-
-               bclr $flags $p1
-               st b32 D[$r0 + #ctx_mode] $r3
-
-       crypt_cmd_mode_return:
-       ret
-
-crypt_cmd_length:
-       // nop if length == 0
-       cmpu b32 $r3 0
-       bra e #crypt_cmd_mode_return
-
-       // init key, IV
-       cxset 3
-       mov $r4 #ctx_key
-       sethi $r4 0x70000
-       xdst $r0 $r4
-       mov $r4 #ctx_iv
-       sethi $r4 0x60000
-       xdst $r0 $r4
-       xdwait
-       ckeyreg $c7
-
-       // prepare the targets
-       mov $r4 0x2100
-       mov $xtargets $r4
-
-       // prepare src address
-       ld b32 $r4 D[$r0 + #ctx_src_address_high]
-       ld b32 $r5 D[$r0 + #ctx_src_address_low]
-       shr b32 $r8 $r5 8
-       shl b32 $r4 0x18
-       or $r4 $r8
-       and $r5 $r5 0xff
-
-       // prepare dst address
-       ld b32 $r6 D[$r0 + #ctx_dst_address_high]
-       ld b32 $r7 D[$r0 + #ctx_dst_address_low]
-       shr b32 $r8 $r7 8
-       shl b32 $r6 0x18
-       or $r6 $r8
-       and $r7 $r7 0xff
-
-       // find the proper prep & do functions
-       ld b32 $r8 D[$r0 + #ctx_mode]
-       shl b32 $r8 2
-
-       // run prep
-       ld b16 $r9 D[$r8 + #crypt_dtable]
-       call $r9
-
-       // do it
-       ld b16 $r9 D[$r8 + #crypt_dtable + 2]
-       call $r9
-       cxset 1
-       xdwait
-       cxset 0x61
-       xdwait
-       xdwait
-
-       // update src address
-       shr b32 $r8 $r4 0x18
-       shl b32 $r9 $r4 8
-       add b32 $r9 $r5
-       adc b32 $r8 0
-       st b32 D[$r0 + #ctx_src_address_high] $r8
-       st b32 D[$r0 + #ctx_src_address_low] $r9
-
-       // update dst address
-       shr b32 $r8 $r6 0x18
-       shl b32 $r9 $r6 8
-       add b32 $r9 $r7
-       adc b32 $r8 0
-       st b32 D[$r0 + #ctx_dst_address_high] $r8
-       st b32 D[$r0 + #ctx_dst_address_low] $r9
-
-       // pull updated IV
-       cxset 2
-       mov $r4 #ctx_iv
-       sethi $r4 0x60000
-       xdld $r0 $r4
-       xdwait
-
-       ret
-
-
-crypt_copy_prep:
-       cs0begin 2
-               cxsin $c0
-               cxsout $c0
-       ret
-
-crypt_store_prep:
-       cs0begin 1
-               cxsout $c6
-       ret
-
-crypt_ecb_e_prep:
-       cs0begin 3
-               cxsin $c0
-               cenc $c0 $c0
-               cxsout $c0
-       ret
-
-crypt_ecb_d_prep:
-       ckexp $c7 $c7
-       cs0begin 3
-               cxsin $c0
-               cdec $c0 $c0
-               cxsout $c0
-       ret
-
-crypt_cbc_e_prep:
-       cs0begin 4
-               cxsin $c0
-               cxor $c6 $c0
-               cenc $c6 $c6
-               cxsout $c6
-       ret
-
-crypt_cbc_d_prep:
-       ckexp $c7 $c7
-       cs0begin 5
-               cmov $c2 $c6
-               cxsin $c6
-               cdec $c0 $c6
-               cxor $c0 $c2
-               cxsout $c0
-       ret
-
-crypt_pcbc_e_prep:
-       cs0begin 5
-               cxsin $c0
-               cxor $c6 $c0
-               cenc $c6 $c6
-               cxsout $c6
-               cxor $c6 $c0
-       ret
-
-crypt_pcbc_d_prep:
-       ckexp $c7 $c7
-       cs0begin 5
-               cxsin $c0
-               cdec $c1 $c0
-               cxor $c6 $c1
-               cxsout $c6
-               cxor $c6 $c0
-       ret
-
-crypt_cfb_e_prep:
-       cs0begin 4
-               cenc $c6 $c6
-               cxsin $c0
-               cxor $c6 $c0
-               cxsout $c6
-       ret
-
-crypt_cfb_d_prep:
-       cs0begin 4
-               cenc $c0 $c6
-               cxsin $c6
-               cxor $c0 $c6
-               cxsout $c0
-       ret
-
-crypt_ofb_prep:
-       cs0begin 4
-               cenc $c6 $c6
-               cxsin $c0
-               cxor $c0 $c6
-               cxsout $c0
-       ret
-
-crypt_ctr_prep:
-       cs0begin 5
-               cenc $c1 $c6
-               cadd $c6 1
-               cxsin $c0
-               cxor $c0 $c1
-               cxsout $c0
-       ret
-
-crypt_cbc_mac_prep:
-       cs0begin 3
-               cxsin $c0
-               cxor $c6 $c0
-               cenc $c6 $c6
-       ret
-
-crypt_cmac_finish_complete_prep:
-       cs0begin 7
-               cxsin $c0
-               cxor $c6 $c0
-               cxor $c0 $c0
-               cenc $c0 $c0
-               cprecmac $c0 $c0
-               cxor $c6 $c0
-               cenc $c6 $c6
-       ret
-
-crypt_cmac_finish_partial_prep:
-       cs0begin 8
-               cxsin $c0
-               cxor $c6 $c0
-               cxor $c0 $c0
-               cenc $c0 $c0
-               cprecmac $c0 $c0
-               cprecmac $c0 $c0
-               cxor $c6 $c0
-               cenc $c6 $c6
-       ret
-
-// TODO
-crypt_do_in:
-       add b32 $r3 $r5
-       mov $xdbase $r4
-       mov $r9 #swap
-       sethi $r9 0x20000
-       crypt_do_in_loop:
-               xdld $r5 $r9
-               xdwait
-               cxset 0x22
-               xdst $r0 $r9
-               cs0exec 1
-               xdwait
-               add b32 $r5 0x10
-               cmpu b32 $r5 $r3
-       bra ne #crypt_do_in_loop
-       cxset 1
-       xdwait
-       ret
-
-crypt_do_out:
-       add b32 $r3 $r7
-       mov $xdbase $r6
-       mov $r9 #swap
-       sethi $r9 0x20000
-       crypt_do_out_loop:
-               cs0exec 1
-               cxset 0x61
-               xdld $r7 $r9
-               xdst $r7 $r9
-               cxset 1
-               xdwait
-               add b32 $r7 0x10
-               cmpu b32 $r7 $r3
-       bra ne #crypt_do_out_loop
-       ret
-
-crypt_do_inout:
-       add b32 $r3 $r5
-       mov $r9 #swap
-       sethi $r9 0x20000
-       crypt_do_inout_loop:
-               mov $xdbase $r4
-               xdld $r5 $r9
-               xdwait
-               cxset 0x21
-               xdst $r0 $r9
-               cs0exec 1
-               cxset 0x61
-               mov $xdbase $r6
-               xdld $r7 $r9
-               xdst $r7 $r9
-               cxset 1
-               xdwait
-               add b32 $r5 0x10
-               add b32 $r7 0x10
-               cmpu b32 $r5 $r3
-       bra ne #crypt_do_inout_loop
-       ret
-
-.align 0x100
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/fuc/nv98.fuc0s.h
deleted file mode 100644 (file)
index 38676c7..0000000
+++ /dev/null
@@ -1,584 +0,0 @@
-uint32_t nv98_pcrypt_data[] = {
-/* 0x0000: ctx_dma */
-/* 0x0000: ctx_dma_query */
-       0x00000000,
-/* 0x0004: ctx_dma_src */
-       0x00000000,
-/* 0x0008: ctx_dma_dst */
-       0x00000000,
-/* 0x000c: ctx_query_address_high */
-       0x00000000,
-/* 0x0010: ctx_query_address_low */
-       0x00000000,
-/* 0x0014: ctx_query_counter */
-       0x00000000,
-/* 0x0018: ctx_cond_address_high */
-       0x00000000,
-/* 0x001c: ctx_cond_address_low */
-       0x00000000,
-/* 0x0020: ctx_cond_off */
-       0x00000000,
-/* 0x0024: ctx_src_address_high */
-       0x00000000,
-/* 0x0028: ctx_src_address_low */
-       0x00000000,
-/* 0x002c: ctx_dst_address_high */
-       0x00000000,
-/* 0x0030: ctx_dst_address_low */
-       0x00000000,
-/* 0x0034: ctx_mode */
-       0x00000000,
-       0x00000000,
-       0x00000000,
-/* 0x0040: ctx_key */
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-/* 0x0050: ctx_iv */
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-/* 0x0080: swap */
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-/* 0x00a0: common_cmd_dtable */
-       0x0002000c,
-       0xffffff00,
-       0x00020010,
-       0x0000000f,
-       0x00020014,
-       0x00000000,
-       0x00000192,
-       0xfffffffe,
-       0x00020018,
-       0xffffff00,
-       0x0002001c,
-       0x0000000f,
-       0x000001d7,
-       0xfffffff8,
-       0x00000260,
-       0xffffffff,
-/* 0x00e0: engine_cmd_dtable */
-       0x00020040,
-       0x00000000,
-       0x00020044,
-       0x00000000,
-       0x00020048,
-       0x00000000,
-       0x0002004c,
-       0x00000000,
-       0x00020050,
-       0x00000000,
-       0x00020054,
-       0x00000000,
-       0x00020058,
-       0x00000000,
-       0x0002005c,
-       0x00000000,
-       0x00020024,
-       0xffffff00,
-       0x00020028,
-       0x0000000f,
-       0x0002002c,
-       0xffffff00,
-       0x00020030,
-       0x0000000f,
-       0x00000271,
-       0xfffffff0,
-       0x00010285,
-       0xf000000f,
-/* 0x0150: crypt_dtable */
-       0x04db0321,
-       0x04b1032f,
-       0x04db0339,
-       0x04db034b,
-       0x04db0361,
-       0x04db0377,
-       0x04db0395,
-       0x04db03af,
-       0x04db03cd,
-       0x04db03e3,
-       0x04db03f9,
-       0x04db040f,
-       0x04830429,
-       0x0483043b,
-       0x0483045d,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-};
-
-uint32_t nv98_pcrypt_code[] = {
-       0x17f004bd,
-       0x0010fe35,
-       0xf10004fe,
-       0xf0fff017,
-       0x27f10013,
-       0x21d00400,
-       0x0c15f0c0,
-       0xf00021d0,
-       0x27f10317,
-       0x21d01200,
-       0x1031f400,
-/* 0x002f: spin */
-       0xf40031f4,
-       0x0ef40028,
-/* 0x0035: ih */
-       0x8001cffd,
-       0xb00812c4,
-       0x0bf40024,
-       0x0027f167,
-       0x002bfe77,
-       0xf00007fe,
-       0x23f00027,
-       0x0037f105,
-       0x0034cf14,
-       0xb0014594,
-       0x18f40055,
-       0x0602fa17,
-       0x4af003f8,
-       0x0034d01e,
-       0xd00147f0,
-       0x0ef48034,
-/* 0x0075: ctxload */
-       0x4034cf33,
-       0xb0014f94,
-       0x18f400f5,
-       0x0502fa21,
-       0x57f003f8,
-       0x0267f000,
-/* 0x008c: ctxload_dma_loop */
-       0xa07856bc,
-       0xb6018068,
-       0x87d00884,
-       0x0162b600,
-/* 0x009f: dummyload */
-       0xf0f018f4,
-       0x35d00257,
-/* 0x00a5: noctx */
-       0x0412c480,
-       0xf50024b0,
-       0xf100df0b,
-       0xcf190037,
-       0x33cf4032,
-       0xff24e400,
-       0x1024b607,
-       0x07bf45e4,
-       0xf50054b0,
-       0xf100b90b,
-       0xf1fae057,
-       0xb000ce67,
-       0x18f4c044,
-       0xa057f14d,
-       0x8867f1fc,
-       0x8044b000,
-       0xb03f18f4,
-       0x18f46044,
-       0x5044b019,
-       0xf1741bf4,
-       0xbd220027,
-       0x0233f034,
-       0xf50023d0,
-/* 0x0103: dma_cmd */
-       0xb000810e,
-       0x18f46344,
-       0x0245945e,
-       0xfe8050b7,
-       0x801e39f0,
-       0x40b70053,
-       0x44b60120,
-       0x0043d008,
-/* 0x0123: dtable_cmd */
-       0xb8600ef4,
-       0x18f40446,
-       0x0344b63e,
-       0x980045bb,
-       0x53fd0145,
-       0x0054b004,
-       0x58291bf4,
-       0x46580045,
-       0x0264b001,
-       0x98170bf4,
-       0x67fd0807,
-       0x0164b004,
-       0xf9300bf4,
-       0x0f01f455,
-/* 0x015b: cmd_setctx */
-       0x80280ef4,
-       0x0ef40053,
-/* 0x0161: invalid_bitfield */
-       0x0125f022,
-/* 0x0164: dispatch_error */
-/* 0x0164: illegal_mthd */
-       0x100047f1,
-       0xd00042d0,
-       0x47f04043,
-       0x0004d040,
-/* 0x0174: im_loop */
-       0xf08004cf,
-       0x44b04044,
-       0xf71bf400,
-/* 0x0180: cmddone */
-       0x1d0037f1,
-       0xd00147f0,
-/* 0x018a: nocmd */
-       0x11c40034,
-       0x4001d00c,
-/* 0x0192: cmd_query_get */
-       0x38f201f8,
-       0x0325f001,
-       0x0b0047f1,
-/* 0x019c: ptimer_retry */
-       0xcf4046cf,
-       0x47cf0045,
-       0x0467b840,
-       0x98f41bf4,
-       0x04800504,
-       0x21008020,
-       0x80220580,
-       0x0bfe2306,
-       0x03049800,
-       0xfe1844b6,
-       0x04980047,
-       0x8057f104,
-       0x0253f000,
-       0xf80645fa,
-/* 0x01d7: cmd_cond_mode */
-       0xf400f803,
-       0x25f00131,
-       0x0534b002,
-       0xf41218f4,
-       0x34b00132,
-       0x0b18f402,
-       0x800136f0,
-/* 0x01f2: return */
-       0x00f80803,
-/* 0x01f4: cmd_cond_mode_queryful */
-       0x98060498,
-       0x56c40705,
-       0x0855b6ff,
-       0xfd1844b6,
-       0x47fe0545,
-       0x000bfe00,
-       0x008057f1,
-       0xfa0253f0,
-       0x34b00565,
-       0x131bf402,
-       0x049803f8,
-       0x0044b021,
-       0x800b4cf0,
-       0x00f80804,
-/* 0x022c: cmd_cond_mode_double */
-       0xb61060b6,
-       0x65fa1050,
-       0x9803f805,
-       0x06982005,
-       0x0456b824,
-       0x980b4cf0,
-       0x06982105,
-       0x0456b825,
-       0xfd0b5cf0,
-       0x34b00445,
-       0x0b5cf003,
-       0x800645fd,
-       0x00f80804,
-/* 0x0260: cmd_wrcache_flush */
-       0xf10132f4,
-       0xbd220027,
-       0x0133f034,
-       0xf80023d0,
-/* 0x0271: crypt_cmd_mode */
-       0x0131f400,
-       0xb00225f0,
-       0x18f40f34,
-       0x0132f409,
-/* 0x0283: crypt_cmd_mode_return */
-       0xf80d0380,
-/* 0x0285: crypt_cmd_length */
-       0x0034b000,
-       0xf4fb0bf4,
-       0x47f0033c,
-       0x0743f040,
-       0xf00604fa,
-       0x43f05047,
-       0x0604fa06,
-       0x3cf503f8,
-       0x47f1c407,
-       0x4bfe2100,
-       0x09049800,
-       0x950a0598,
-       0x44b60858,
-       0x0548fd18,
-       0x98ff55c4,
-       0x07980b06,
-       0x0878950c,
-       0xfd1864b6,
-       0x77c40568,
-       0x0d0898ff,
-       0x580284b6,
-       0x95f9a889,
-       0xf9a98958,
-       0x013cf495,
-       0x3cf403f8,
-       0xf803f861,
-       0x18489503,
-       0xbb084994,
-       0x81b60095,
-       0x09088000,
-       0x950a0980,
-       0x69941868,
-       0x0097bb08,
-       0x800081b6,
-       0x09800b08,
-       0x023cf40c,
-       0xf05047f0,
-       0x04fa0643,
-       0xf803f805,
-/* 0x0321: crypt_copy_prep */
-       0x203cf500,
-       0x003cf594,
-       0x003cf588,
-/* 0x032f: crypt_store_prep */
-       0xf500f88c,
-       0xf594103c,
-       0xf88c063c,
-/* 0x0339: crypt_ecb_e_prep */
-       0x303cf500,
-       0x003cf594,
-       0x003cf588,
-       0x003cf5d0,
-/* 0x034b: crypt_ecb_d_prep */
-       0xf500f88c,
-       0xf5c8773c,
-       0xf594303c,
-       0xf588003c,
-       0xf5d4003c,
-       0xf88c003c,
-/* 0x0361: crypt_cbc_e_prep */
-       0x403cf500,
-       0x003cf594,
-       0x063cf588,
-       0x663cf5ac,
-       0x063cf5d0,
-/* 0x0377: crypt_cbc_d_prep */
-       0xf500f88c,
-       0xf5c8773c,
-       0xf594503c,
-       0xf584623c,
-       0xf588063c,
-       0xf5d4603c,
-       0xf5ac203c,
-       0xf88c003c,
-/* 0x0395: crypt_pcbc_e_prep */
-       0x503cf500,
-       0x003cf594,
-       0x063cf588,
-       0x663cf5ac,
-       0x063cf5d0,
-       0x063cf58c,
-/* 0x03af: crypt_pcbc_d_prep */
-       0xf500f8ac,
-       0xf5c8773c,
-       0xf594503c,
-       0xf588003c,
-       0xf5d4013c,
-       0xf5ac163c,
-       0xf58c063c,
-       0xf8ac063c,
-/* 0x03cd: crypt_cfb_e_prep */
-       0x403cf500,
-       0x663cf594,
-       0x003cf5d0,
-       0x063cf588,
-       0x063cf5ac,
-/* 0x03e3: crypt_cfb_d_prep */
-       0xf500f88c,
-       0xf594403c,
-       0xf5d0603c,
-       0xf588063c,
-       0xf5ac603c,
-       0xf88c003c,
-/* 0x03f9: crypt_ofb_prep */
-       0x403cf500,
-       0x663cf594,
-       0x003cf5d0,
-       0x603cf588,
-       0x003cf5ac,
-/* 0x040f: crypt_ctr_prep */
-       0xf500f88c,
-       0xf594503c,
-       0xf5d0613c,
-       0xf5b0163c,
-       0xf588003c,
-       0xf5ac103c,
-       0xf88c003c,
-/* 0x0429: crypt_cbc_mac_prep */
-       0x303cf500,
-       0x003cf594,
-       0x063cf588,
-       0x663cf5ac,
-/* 0x043b: crypt_cmac_finish_complete_prep */
-       0xf500f8d0,
-       0xf594703c,
-       0xf588003c,
-       0xf5ac063c,
-       0xf5ac003c,
-       0xf5d0003c,
-       0xf5bc003c,
-       0xf5ac063c,
-       0xf8d0663c,
-/* 0x045d: crypt_cmac_finish_partial_prep */
-       0x803cf500,
-       0x003cf594,
-       0x063cf588,
-       0x003cf5ac,
-       0x003cf5ac,
-       0x003cf5d0,
-       0x003cf5bc,
-       0x063cf5bc,
-       0x663cf5ac,
-/* 0x0483: crypt_do_in */
-       0xbb00f8d0,
-       0x47fe0035,
-       0x8097f100,
-       0x0293f000,
-/* 0x0490: crypt_do_in_loop */
-       0xf80559fa,
-       0x223cf403,
-       0xf50609fa,
-       0xf898103c,
-       0x1050b603,
-       0xf40453b8,
-       0x3cf4e91b,
-       0xf803f801,
-/* 0x04b1: crypt_do_out */
-       0x0037bb00,
-       0xf10067fe,
-       0xf0008097,
-/* 0x04be: crypt_do_out_loop */
-       0x3cf50293,
-       0x3cf49810,
-       0x0579fa61,
-       0xf40679fa,
-       0x03f8013c,
-       0xb81070b6,
-       0x1bf40473,
-/* 0x04db: crypt_do_inout */
-       0xbb00f8e8,
-       0x97f10035,
-       0x93f00080,
-/* 0x04e5: crypt_do_inout_loop */
-       0x0047fe02,
-       0xf80559fa,
-       0x213cf403,
-       0xf50609fa,
-       0xf498103c,
-       0x67fe613c,
-       0x0579fa00,
-       0xf40679fa,
-       0x03f8013c,
-       0xb61050b6,
-       0x53b81070,
-       0xd41bf404,
-       0x000000f8,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-       0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv84.c
deleted file mode 100644 (file)
index ea5c42f..0000000
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/enum.h>
-#include <core/engctx.h>
-#include <core/gpuobj.h>
-
-#include <subdev/fb.h>
-
-#include <engine/fifo.h>
-#include <engine/crypt.h>
-
-struct nv84_crypt_priv {
-       struct nouveau_engine base;
-};
-
-/*******************************************************************************
- * Crypt object classes
- ******************************************************************************/
-
-static int
-nv84_crypt_object_ctor(struct nouveau_object *parent,
-                      struct nouveau_object *engine,
-                      struct nouveau_oclass *oclass, void *data, u32 size,
-                      struct nouveau_object **pobject)
-{
-       struct nouveau_gpuobj *obj;
-       int ret;
-
-       ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
-                                   16, 16, 0, &obj);
-       *pobject = nv_object(obj);
-       if (ret)
-               return ret;
-
-       nv_wo32(obj, 0x00, nv_mclass(obj));
-       nv_wo32(obj, 0x04, 0x00000000);
-       nv_wo32(obj, 0x08, 0x00000000);
-       nv_wo32(obj, 0x0c, 0x00000000);
-       return 0;
-}
-
-static struct nouveau_ofuncs
-nv84_crypt_ofuncs = {
-       .ctor = nv84_crypt_object_ctor,
-       .dtor = _nouveau_gpuobj_dtor,
-       .init = _nouveau_gpuobj_init,
-       .fini = _nouveau_gpuobj_fini,
-       .rd32 = _nouveau_gpuobj_rd32,
-       .wr32 = _nouveau_gpuobj_wr32,
-};
-
-static struct nouveau_oclass
-nv84_crypt_sclass[] = {
-       { 0x74c1, &nv84_crypt_ofuncs },
-       {}
-};
-
-/*******************************************************************************
- * PCRYPT context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv84_crypt_cclass = {
-       .handle = NV_ENGCTX(CRYPT, 0x84),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = _nouveau_engctx_ctor,
-               .dtor = _nouveau_engctx_dtor,
-               .init = _nouveau_engctx_init,
-               .fini = _nouveau_engctx_fini,
-               .rd32 = _nouveau_engctx_rd32,
-               .wr32 = _nouveau_engctx_wr32,
-       },
-};
-
-/*******************************************************************************
- * PCRYPT engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_bitfield nv84_crypt_intr_mask[] = {
-       { 0x00000001, "INVALID_STATE" },
-       { 0x00000002, "ILLEGAL_MTHD" },
-       { 0x00000004, "ILLEGAL_CLASS" },
-       { 0x00000080, "QUERY" },
-       { 0x00000100, "FAULT" },
-       {}
-};
-
-static void
-nv84_crypt_intr(struct nouveau_subdev *subdev)
-{
-       struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-       struct nouveau_engine *engine = nv_engine(subdev);
-       struct nouveau_object *engctx;
-       struct nv84_crypt_priv *priv = (void *)subdev;
-       u32 stat = nv_rd32(priv, 0x102130);
-       u32 mthd = nv_rd32(priv, 0x102190);
-       u32 data = nv_rd32(priv, 0x102194);
-       u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff;
-       int chid;
-
-       engctx = nouveau_engctx_get(engine, inst);
-       chid   = pfifo->chid(pfifo, engctx);
-
-       if (stat) {
-               nv_error(priv, "%s", "");
-               nouveau_bitfield_print(nv84_crypt_intr_mask, stat);
-               pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n",
-                      chid, (u64)inst << 12, nouveau_client_name(engctx),
-                      mthd, data);
-       }
-
-       nv_wr32(priv, 0x102130, stat);
-       nv_wr32(priv, 0x10200c, 0x10);
-
-       nouveau_engctx_put(engctx);
-}
-
-static int
-nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-              struct nouveau_oclass *oclass, void *data, u32 size,
-              struct nouveau_object **pobject)
-{
-       struct nv84_crypt_priv *priv;
-       int ret;
-
-       ret = nouveau_engine_create(parent, engine, oclass, true,
-                                   "PCRYPT", "crypt", &priv);
-       *pobject = nv_object(priv);
-       if (ret)
-               return ret;
-
-       nv_subdev(priv)->unit = 0x00004000;
-       nv_subdev(priv)->intr = nv84_crypt_intr;
-       nv_engine(priv)->cclass = &nv84_crypt_cclass;
-       nv_engine(priv)->sclass = nv84_crypt_sclass;
-       return 0;
-}
-
-static int
-nv84_crypt_init(struct nouveau_object *object)
-{
-       struct nv84_crypt_priv *priv = (void *)object;
-       int ret;
-
-       ret = nouveau_engine_init(&priv->base);
-       if (ret)
-               return ret;
-
-       nv_wr32(priv, 0x102130, 0xffffffff);
-       nv_wr32(priv, 0x102140, 0xffffffbf);
-       nv_wr32(priv, 0x10200c, 0x00000010);
-       return 0;
-}
-
-struct nouveau_oclass
-nv84_crypt_oclass = {
-       .handle = NV_ENGINE(CRYPT, 0x84),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = nv84_crypt_ctor,
-               .dtor = _nouveau_engine_dtor,
-               .init = nv84_crypt_init,
-               .fini = _nouveau_engine_fini,
-       },
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/crypt/nv98.c
deleted file mode 100644 (file)
index e0838c4..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/enum.h>
-#include <core/engctx.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/falcon.h>
-#include <engine/fifo.h>
-#include <engine/crypt.h>
-
-#include "fuc/nv98.fuc0s.h"
-
-struct nv98_crypt_priv {
-       struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * Crypt object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_crypt_sclass[] = {
-       { 0x88b4, &nouveau_object_ofuncs },
-       {},
-};
-
-/*******************************************************************************
- * PCRYPT context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_crypt_cclass = {
-       .handle = NV_ENGCTX(CRYPT, 0x98),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = _nouveau_falcon_context_ctor,
-               .dtor = _nouveau_falcon_context_dtor,
-               .init = _nouveau_falcon_context_init,
-               .fini = _nouveau_falcon_context_fini,
-               .rd32 = _nouveau_falcon_context_rd32,
-               .wr32 = _nouveau_falcon_context_wr32,
-       },
-};
-
-/*******************************************************************************
- * PCRYPT engine/subdev functions
- ******************************************************************************/
-
-static const struct nouveau_enum nv98_crypt_isr_error_name[] = {
-       { 0x0000, "ILLEGAL_MTHD" },
-       { 0x0001, "INVALID_BITFIELD" },
-       { 0x0002, "INVALID_ENUM" },
-       { 0x0003, "QUERY" },
-       {}
-};
-
-static void
-nv98_crypt_intr(struct nouveau_subdev *subdev)
-{
-       struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-       struct nouveau_engine *engine = nv_engine(subdev);
-       struct nouveau_object *engctx;
-       struct nv98_crypt_priv *priv = (void *)subdev;
-       u32 disp = nv_rd32(priv, 0x08701c);
-       u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
-       u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
-       u32 ssta = nv_rd32(priv, 0x087040) & 0x0000ffff;
-       u32 addr = nv_rd32(priv, 0x087040) >> 16;
-       u32 mthd = (addr & 0x07ff) << 2;
-       u32 subc = (addr & 0x3800) >> 11;
-       u32 data = nv_rd32(priv, 0x087044);
-       int chid;
-
-       engctx = nouveau_engctx_get(engine, inst);
-       chid   = pfifo->chid(pfifo, engctx);
-
-       if (stat & 0x00000040) {
-               nv_error(priv, "DISPATCH_ERROR [");
-               nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
-               pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
-                      chid, (u64)inst << 12, nouveau_client_name(engctx),
-                      subc, mthd, data);
-               nv_wr32(priv, 0x087004, 0x00000040);
-               stat &= ~0x00000040;
-       }
-
-       if (stat) {
-               nv_error(priv, "unhandled intr 0x%08x\n", stat);
-               nv_wr32(priv, 0x087004, stat);
-       }
-
-       nouveau_engctx_put(engctx);
-}
-
-static int
-nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-              struct nouveau_oclass *oclass, void *data, u32 size,
-              struct nouveau_object **pobject)
-{
-       struct nv98_crypt_priv *priv;
-       int ret;
-
-       ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true,
-                                   "PCRYPT", "crypt", &priv);
-       *pobject = nv_object(priv);
-       if (ret)
-               return ret;
-
-       nv_subdev(priv)->unit = 0x00004000;
-       nv_subdev(priv)->intr = nv98_crypt_intr;
-       nv_engine(priv)->cclass = &nv98_crypt_cclass;
-       nv_engine(priv)->sclass = nv98_crypt_sclass;
-       nv_falcon(priv)->code.data = nv98_pcrypt_code;
-       nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code);
-       nv_falcon(priv)->data.data = nv98_pcrypt_data;
-       nv_falcon(priv)->data.size = sizeof(nv98_pcrypt_data);
-       return 0;
-}
-
-struct nouveau_oclass
-nv98_crypt_oclass = {
-       .handle = NV_ENGINE(CRYPT, 0x98),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = nv98_crypt_ctor,
-               .dtor = _nouveau_falcon_dtor,
-               .init = _nouveau_falcon_init,
-               .fini = _nouveau_falcon_fini,
-               .rd32 = _nouveau_falcon_rd32,
-               .wr32 = _nouveau_falcon_wr32,
-       },
-};
index 7945bba5e79483988979ccba7085a35fcdcc0c18..fe269ef0035583f6b2130eda55b25f4b198827db 100644 (file)
@@ -232,7 +232,7 @@ static const u64 disable_map[] = {
        [NVDEV_ENGINE_MPEG]     = NV_DEVICE_V0_DISABLE_MPEG,
        [NVDEV_ENGINE_ME]       = NV_DEVICE_V0_DISABLE_ME,
        [NVDEV_ENGINE_VP]       = NV_DEVICE_V0_DISABLE_VP,
-       [NVDEV_ENGINE_CRYPT]    = NV_DEVICE_V0_DISABLE_CRYPT,
+       [NVDEV_ENGINE_CIPHER]   = NV_DEVICE_V0_DISABLE_CIPHER,
        [NVDEV_ENGINE_BSP]      = NV_DEVICE_V0_DISABLE_BSP,
        [NVDEV_ENGINE_PPP]      = NV_DEVICE_V0_DISABLE_PPP,
        [NVDEV_ENGINE_COPY0]    = NV_DEVICE_V0_DISABLE_COPY0,
@@ -242,6 +242,7 @@ static const u64 disable_map[] = {
        [NVDEV_ENGINE_VENC]     = NV_DEVICE_V0_DISABLE_VENC,
        [NVDEV_ENGINE_DISP]     = NV_DEVICE_V0_DISABLE_DISP,
        [NVDEV_ENGINE_MSVLD]    = NV_DEVICE_V0_DISABLE_MSVLD,
+       [NVDEV_ENGINE_SEC]      = NV_DEVICE_V0_DISABLE_SEC,
        [NVDEV_SUBDEV_NR]       = 0,
 };
 
index 90f0e23f582e4804faf75eab0eef066cd66b32c8..2fb06eb451f36f416392ee0a18138488f3826ba8 100644 (file)
@@ -47,7 +47,8 @@
 #include <engine/graph.h>
 #include <engine/mpeg.h>
 #include <engine/vp.h>
-#include <engine/crypt.h>
+#include <engine/cipher.h>
+#include <engine/sec.h>
 #include <engine/bsp.h>
 #include <engine/msvld.h>
 #include <engine/ppp.h>
@@ -109,7 +110,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
                device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
@@ -138,7 +139,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
                device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
@@ -167,7 +168,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
                device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
@@ -196,7 +197,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
                device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
@@ -225,7 +226,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
                device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
@@ -253,7 +254,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
                device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
@@ -283,7 +284,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv84_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_CIPHER ] = &nv84_cipher_oclass;
                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva0_disp_oclass;
                device->oclass[NVDEV_ENGINE_PERFMON] =  nv84_perfmon_oclass;
@@ -311,7 +312,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
                device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
@@ -340,7 +341,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_software_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
-               device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
+               device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
                device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
index 7183bf1d7f5b15419dbe59fce5b1bdbfad1663a2..3928439916635e7774d38a9b1b7ed310109b12f7 100644 (file)
@@ -55,15 +55,16 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
        u32 addr;
 
        switch (nv_engidx(object->engine)) {
-       case NVDEV_ENGINE_SW   : return 0;
-       case NVDEV_ENGINE_GR   : addr = 0x0020; break;
-       case NVDEV_ENGINE_VP   : addr = 0x0040; break;
-       case NVDEV_ENGINE_PPP  :
-       case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
-       case NVDEV_ENGINE_BSP  :
-       case NVDEV_ENGINE_MSVLD: addr = 0x0080; break;
-       case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
-       case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
+       case NVDEV_ENGINE_SW    : return 0;
+       case NVDEV_ENGINE_GR    : addr = 0x0020; break;
+       case NVDEV_ENGINE_VP    : addr = 0x0040; break;
+       case NVDEV_ENGINE_PPP   :
+       case NVDEV_ENGINE_MPEG  : addr = 0x0060; break;
+       case NVDEV_ENGINE_BSP   :
+       case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
+       case NVDEV_ENGINE_CIPHER:
+       case NVDEV_ENGINE_SEC   : addr = 0x00a0; break;
+       case NVDEV_ENGINE_COPY0 : addr = 0x00c0; break;
        default:
                return -EINVAL;
        }
@@ -92,15 +93,16 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
        bool done;
 
        switch (nv_engidx(object->engine)) {
-       case NVDEV_ENGINE_SW   : return 0;
-       case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;
-       case NVDEV_ENGINE_VP   : engn = 3; addr = 0x0040; break;
-       case NVDEV_ENGINE_PPP  :
-       case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
-       case NVDEV_ENGINE_BSP  :
-       case NVDEV_ENGINE_MSVLD: engn = 5; addr = 0x0080; break;
-       case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
-       case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
+       case NVDEV_ENGINE_SW    : return 0;
+       case NVDEV_ENGINE_GR    : engn = 0; addr = 0x0020; break;
+       case NVDEV_ENGINE_VP    : engn = 3; addr = 0x0040; break;
+       case NVDEV_ENGINE_PPP   :
+       case NVDEV_ENGINE_MPEG  : engn = 1; addr = 0x0060; break;
+       case NVDEV_ENGINE_BSP   :
+       case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
+       case NVDEV_ENGINE_CIPHER:
+       case NVDEV_ENGINE_SEC   : engn = 4; addr = 0x00a0; break;
+       case NVDEV_ENGINE_COPY0 : engn = 2; addr = 0x00c0; break;
        default:
                return -EINVAL;
        }
@@ -147,7 +149,8 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
        case NVDEV_ENGINE_ME    :
        case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
        case NVDEV_ENGINE_VP    : context |= 0x00400000; break;
-       case NVDEV_ENGINE_CRYPT :
+       case NVDEV_ENGINE_CIPHER:
+       case NVDEV_ENGINE_SEC   :
        case NVDEV_ENGINE_VIC   : context |= 0x00500000; break;
        case NVDEV_ENGINE_BSP   :
        case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break;
@@ -188,7 +191,8 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
                                          (1ULL << NVDEV_ENGINE_MPEG) |
                                          (1ULL << NVDEV_ENGINE_ME) |
                                          (1ULL << NVDEV_ENGINE_VP) |
-                                         (1ULL << NVDEV_ENGINE_CRYPT) |
+                                         (1ULL << NVDEV_ENGINE_CIPHER) |
+                                         (1ULL << NVDEV_ENGINE_SEC) |
                                          (1ULL << NVDEV_ENGINE_BSP) |
                                          (1ULL << NVDEV_ENGINE_MSVLD) |
                                          (1ULL << NVDEV_ENGINE_PPP) |
@@ -262,7 +266,8 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
                                          (1ULL << NVDEV_ENGINE_MPEG) |
                                          (1ULL << NVDEV_ENGINE_ME) |
                                          (1ULL << NVDEV_ENGINE_VP) |
-                                         (1ULL << NVDEV_ENGINE_CRYPT) |
+                                         (1ULL << NVDEV_ENGINE_CIPHER) |
+                                         (1ULL << NVDEV_ENGINE_SEC) |
                                          (1ULL << NVDEV_ENGINE_BSP) |
                                          (1ULL << NVDEV_ENGINE_MSVLD) |
                                          (1ULL << NVDEV_ENGINE_PPP) |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/sec/Kbuild
new file mode 100644 (file)
index 0000000..5ce7a50
--- /dev/null
@@ -0,0 +1 @@
+nvkm-y += nvkm/engine/sec/nv98.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s
new file mode 100644 (file)
index 0000000..0b9e777
--- /dev/null
@@ -0,0 +1,698 @@
+/*
+ *  fuc microcode for nv98 psec engine
+ *  Copyright (C) 2010  Marcin KoÅ›cielnicki
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+.section #nv98_psec_data
+
+ctx_dma:
+ctx_dma_query:         .b32 0
+ctx_dma_src:           .b32 0
+ctx_dma_dst:           .b32 0
+.equ #dma_count 3
+ctx_query_address_high:        .b32 0
+ctx_query_address_low: .b32 0
+ctx_query_counter:     .b32 0
+ctx_cond_address_high: .b32 0
+ctx_cond_address_low:  .b32 0
+ctx_cond_off:          .b32 0
+ctx_src_address_high:  .b32 0
+ctx_src_address_low:   .b32 0
+ctx_dst_address_high:  .b32 0
+ctx_dst_address_low:   .b32 0
+ctx_mode:              .b32 0
+.align 16
+ctx_key:               .skip 16
+ctx_iv:                        .skip 16
+
+.align 0x80
+swap:
+.skip 32
+
+.align 8
+common_cmd_dtable:
+.b32 #ctx_query_address_high + 0x20000 ~0xff
+.b32 #ctx_query_address_low + 0x20000 ~0xfffffff0
+.b32 #ctx_query_counter + 0x20000 ~0xffffffff
+.b32 #cmd_query_get + 0x00000 ~1
+.b32 #ctx_cond_address_high + 0x20000 ~0xff
+.b32 #ctx_cond_address_low + 0x20000 ~0xfffffff0
+.b32 #cmd_cond_mode + 0x00000 ~7
+.b32 #cmd_wrcache_flush + 0x00000 ~0
+.equ #common_cmd_max 0x88
+
+
+.align 8
+engine_cmd_dtable:
+.b32 #ctx_key + 0x0 + 0x20000 ~0xffffffff
+.b32 #ctx_key + 0x4 + 0x20000 ~0xffffffff
+.b32 #ctx_key + 0x8 + 0x20000 ~0xffffffff
+.b32 #ctx_key + 0xc + 0x20000 ~0xffffffff
+.b32 #ctx_iv + 0x0 + 0x20000 ~0xffffffff
+.b32 #ctx_iv + 0x4 + 0x20000 ~0xffffffff
+.b32 #ctx_iv + 0x8 + 0x20000 ~0xffffffff
+.b32 #ctx_iv + 0xc + 0x20000 ~0xffffffff
+.b32 #ctx_src_address_high + 0x20000 ~0xff
+.b32 #ctx_src_address_low + 0x20000 ~0xfffffff0
+.b32 #ctx_dst_address_high + 0x20000 ~0xff
+.b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0
+.b32 #sec_cmd_mode + 0x00000 ~0xf
+.b32 #sec_cmd_length + 0x10000 ~0x0ffffff0
+.equ #engine_cmd_max 0xce
+
+.align 4
+sec_dtable:
+.b16 #sec_copy_prep #sec_do_inout
+.b16 #sec_store_prep #sec_do_out
+.b16 #sec_ecb_e_prep #sec_do_inout
+.b16 #sec_ecb_d_prep #sec_do_inout
+.b16 #sec_cbc_e_prep #sec_do_inout
+.b16 #sec_cbc_d_prep #sec_do_inout
+.b16 #sec_pcbc_e_prep #sec_do_inout
+.b16 #sec_pcbc_d_prep #sec_do_inout
+.b16 #sec_cfb_e_prep #sec_do_inout
+.b16 #sec_cfb_d_prep #sec_do_inout
+.b16 #sec_ofb_prep #sec_do_inout
+.b16 #sec_ctr_prep #sec_do_inout
+.b16 #sec_cbc_mac_prep #sec_do_in
+.b16 #sec_cmac_finish_complete_prep #sec_do_in
+.b16 #sec_cmac_finish_partial_prep #sec_do_in
+
+.align 0x100
+
+.section #nv98_psec_code
+
+       // $r0 is always set to 0 in our code - this allows some space savings.
+       clear b32 $r0
+
+       // set up the interrupt handler
+       mov $r1 #ih
+       mov $iv0 $r1
+
+       // init stack pointer
+       mov $sp $r0
+
+       // set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host
+       movw $r1 0xfff0
+       sethi $r1 0
+       mov $r2 0x400
+       iowr I[$r2 + 0x300] $r1
+
+       // enable the interrupts
+       or $r1 0xc
+       iowr I[$r2] $r1
+
+       // enable fifo access and context switching
+       mov $r1 3
+       mov $r2 0x1200
+       iowr I[$r2] $r1
+
+       // enable i0 delivery
+       bset $flags ie0
+
+       // sleep forver, waking only for interrupts.
+       bset $flags $p0
+       spin:
+       sleep $p0
+       bra #spin
+
+// i0 handler
+ih:
+       // see which interrupts we got
+       iord $r1 I[$r0 + 0x200]
+
+       and $r2 $r1 0x8
+       cmpu b32 $r2 0
+       bra e #noctx
+
+               // context switch... prepare the regs for xfer
+               mov $r2 0x7700
+               mov $xtargets $r2
+               mov $xdbase $r0
+               // 128-byte context.
+               mov $r2 0
+               sethi $r2 0x50000
+
+               // read current channel
+               mov $r3 0x1400
+               iord $r4 I[$r3]
+               // if bit 30 set, it's active, so we have to unload it first.
+               shl b32 $r5 $r4 1
+               cmps b32 $r5 0
+               bra nc #ctxload
+
+                       // unload the current channel - save the context
+                       xdst $r0 $r2
+                       xdwait
+                       // and clear bit 30, then write back
+                       bclr $r4 0x1e
+                       iowr I[$r3] $r4
+                       // tell PFIFO we unloaded
+                       mov $r4 1
+                       iowr I[$r3 + 0x200] $r4
+
+               bra #noctx
+
+               ctxload:
+                       // no channel loaded - perhaps we're requested to load one
+                       iord $r4 I[$r3 + 0x100]
+                       shl b32 $r15 $r4 1
+                       cmps b32 $r15 0
+                       // if bit 30 of next channel not set, probably PFIFO is just
+                       // killing a context. do a faux load, without the active bit.
+                       bra nc #dummyload
+
+                               // ok, do a real context load.
+                               xdld $r0 $r2
+                               xdwait
+                               mov $r5 #ctx_dma
+                               mov $r6 #dma_count - 1
+                               ctxload_dma_loop:
+                                       ld b32 $r7 D[$r5 + $r6 * 4]
+                                       add b32 $r8 $r6 0x180
+                                       shl b32 $r8 8
+                                       iowr I[$r8] $r7
+                                       sub b32 $r6 1
+                               bra nc #ctxload_dma_loop
+
+                       dummyload:
+                       // tell PFIFO we're done
+                       mov $r5 2
+                       iowr I[$r3 + 0x200] $r5
+
+       noctx:
+       and $r2 $r1 0x4
+       cmpu b32 $r2 0
+       bra e #nocmd
+
+               // incoming fifo command.
+               mov $r3 0x1900
+               iord $r2 I[$r3 + 0x100]
+               iord $r3 I[$r3]
+               // extract the method
+               and $r4 $r2 0x7ff
+               // shift the addr to proper position if we need to interrupt later
+               shl b32 $r2 0x10
+
+               // mthd 0 and 0x100 [NAME, NOP]: ignore
+               and $r5 $r4 0x7bf
+               cmpu b32 $r5 0
+               bra e #cmddone
+
+               mov $r5 #engine_cmd_dtable - 0xc0 * 8
+               mov $r6 #engine_cmd_max
+               cmpu b32 $r4 0xc0
+               bra nc #dtable_cmd
+               mov $r5 #common_cmd_dtable - 0x80 * 8
+               mov $r6 #common_cmd_max
+               cmpu b32 $r4 0x80
+               bra nc #dtable_cmd
+               cmpu b32 $r4 0x60
+               bra nc #dma_cmd
+               cmpu b32 $r4 0x50
+               bra ne #illegal_mthd
+
+                       // mthd 0x140: PM_TRIGGER
+                       mov $r2 0x2200
+                       clear b32 $r3
+                       sethi $r3 0x20000
+                       iowr I[$r2] $r3
+                       bra #cmddone
+
+               dma_cmd:
+                       // mthd 0x180...: DMA_*
+                       cmpu b32 $r4 0x60+#dma_count
+                       bra nc #illegal_mthd
+                       shl b32 $r5 $r4 2
+                       add b32 $r5 ((#ctx_dma - 0x60 * 4) & 0xffff)
+                       bset $r3 0x1e
+                       st b32 D[$r5] $r3
+                       add b32 $r4 0x180 - 0x60
+                       shl b32 $r4 8
+                       iowr I[$r4] $r3
+                       bra #cmddone
+
+               dtable_cmd:
+                       cmpu b32 $r4 $r6
+                       bra nc #illegal_mthd
+                       shl b32 $r4 3
+                       add b32 $r4 $r5
+                       ld b32 $r5 D[$r4 + 4]
+                       and $r5 $r3
+                       cmpu b32 $r5 0
+                       bra ne #invalid_bitfield
+                       ld b16 $r5 D[$r4]
+                       ld b16 $r6 D[$r4 + 2]
+                       cmpu b32 $r6 2
+                       bra e #cmd_setctx
+                       ld b32 $r7 D[$r0 + #ctx_cond_off]
+                       and $r6 $r7
+                       cmpu b32 $r6 1
+                       bra e #cmddone
+                       call $r5
+                       bra $p1 #dispatch_error
+                       bra #cmddone
+
+               cmd_setctx:
+                       st b32 D[$r5] $r3
+                       bra #cmddone
+
+
+               invalid_bitfield:
+                       or $r2 1
+               dispatch_error:
+               illegal_mthd:
+                       mov $r4 0x1000
+                       iowr I[$r4] $r2
+                       iowr I[$r4 + 0x100] $r3
+                       mov $r4 0x40
+                       iowr I[$r0] $r4
+
+                       im_loop:
+                               iord $r4 I[$r0 + 0x200]
+                               and $r4 0x40
+                               cmpu b32 $r4 0
+                       bra ne #im_loop
+
+               cmddone:
+               // remove the command from FIFO
+               mov $r3 0x1d00
+               mov $r4 1
+               iowr I[$r3] $r4
+
+       nocmd:
+       // ack the processed interrupts
+       and $r1 $r1 0xc
+       iowr I[$r0 + 0x100] $r1
+iret
+
+cmd_query_get:
+       // if bit 0 of param set, trigger interrupt afterwards.
+       setp $p1 $r3
+       or $r2 3
+
+       // read PTIMER, beware of races...
+       mov $r4 0xb00
+       ptimer_retry:
+               iord $r6 I[$r4 + 0x100]
+               iord $r5 I[$r4]
+               iord $r7 I[$r4 + 0x100]
+               cmpu b32 $r6 $r7
+       bra ne #ptimer_retry
+
+       // prepare the query structure
+       ld b32 $r4 D[$r0 + #ctx_query_counter]
+       st b32 D[$r0 + #swap + 0x0] $r4
+       st b32 D[$r0 + #swap + 0x4] $r0
+       st b32 D[$r0 + #swap + 0x8] $r5
+       st b32 D[$r0 + #swap + 0xc] $r6
+
+       // will use target 0, DMA_QUERY.
+       mov $xtargets $r0
+
+       ld b32 $r4 D[$r0 + #ctx_query_address_high]
+       shl b32 $r4 0x18
+       mov $xdbase $r4
+
+       ld b32 $r4 D[$r0 + #ctx_query_address_low]
+       mov $r5 #swap
+       sethi $r5 0x20000
+       xdst $r4 $r5
+       xdwait
+
+       ret
+
+cmd_cond_mode:
+       // if >= 5, INVALID_ENUM
+       bset $flags $p1
+       or $r2 2
+       cmpu b32 $r3 5
+       bra nc #return
+
+       // otherwise, no error.
+       bclr $flags $p1
+
+       // if < 2, no QUERY object is involved
+       cmpu b32 $r3 2
+       bra nc #cmd_cond_mode_queryful
+
+               xor $r3 1
+               st b32 D[$r0 + #ctx_cond_off] $r3
+       return:
+               ret
+
+       cmd_cond_mode_queryful:
+       // ok, will need to pull a QUERY object, prepare offsets
+       ld b32 $r4 D[$r0 + #ctx_cond_address_high]
+       ld b32 $r5 D[$r0 + #ctx_cond_address_low]
+       and $r6 $r5 0xff
+       shr b32 $r5 8
+       shl b32 $r4 0x18
+       or $r4 $r5
+       mov $xdbase $r4
+       mov $xtargets $r0
+
+       // pull the first one
+       mov $r5 #swap
+       sethi $r5 0x20000
+       xdld $r6 $r5
+
+       // if == 2, only a single QUERY is involved...
+       cmpu b32 $r3 2
+       bra ne #cmd_cond_mode_double
+
+               xdwait
+               ld b32 $r4 D[$r0 + #swap + 4]
+               cmpu b32 $r4 0
+               xbit $r4 $flags z
+               st b32 D[$r0 + #ctx_cond_off] $r4
+               ret
+
+       // ok, we'll need to pull second one too
+       cmd_cond_mode_double:
+       add b32 $r6 0x10
+       add b32 $r5 0x10
+       xdld $r6 $r5
+       xdwait
+
+       // compare COUNTERs
+       ld b32 $r5 D[$r0 + #swap + 0x00]
+       ld b32 $r6 D[$r0 + #swap + 0x10]
+       cmpu b32 $r5 $r6
+       xbit $r4 $flags z
+
+       // compare RESen
+       ld b32 $r5 D[$r0 + #swap + 0x04]
+       ld b32 $r6 D[$r0 + #swap + 0x14]
+       cmpu b32 $r5 $r6
+       xbit $r5 $flags z
+       and $r4 $r5
+
+       // and negate or not, depending on mode
+       cmpu b32 $r3 3
+       xbit $r5 $flags z
+       xor $r4 $r5
+       st b32 D[$r0 + #ctx_cond_off] $r4
+       ret
+
+cmd_wrcache_flush:
+       bclr $flags $p1
+       mov $r2 0x2200
+       clear b32 $r3
+       sethi $r3 0x10000
+       iowr I[$r2] $r3
+       ret
+
+sec_cmd_mode:
+       // if >= 0xf, INVALID_ENUM
+       bset $flags $p1
+       or $r2 2
+       cmpu b32 $r3 0xf
+       bra nc #sec_cmd_mode_return
+
+               bclr $flags $p1
+               st b32 D[$r0 + #ctx_mode] $r3
+
+       sec_cmd_mode_return:
+       ret
+
+sec_cmd_length:
+       // nop if length == 0
+       cmpu b32 $r3 0
+       bra e #sec_cmd_mode_return
+
+       // init key, IV
+       cxset 3
+       mov $r4 #ctx_key
+       sethi $r4 0x70000
+       xdst $r0 $r4
+       mov $r4 #ctx_iv
+       sethi $r4 0x60000
+       xdst $r0 $r4
+       xdwait
+       ckeyreg $c7
+
+       // prepare the targets
+       mov $r4 0x2100
+       mov $xtargets $r4
+
+       // prepare src address
+       ld b32 $r4 D[$r0 + #ctx_src_address_high]
+       ld b32 $r5 D[$r0 + #ctx_src_address_low]
+       shr b32 $r8 $r5 8
+       shl b32 $r4 0x18
+       or $r4 $r8
+       and $r5 $r5 0xff
+
+       // prepare dst address
+       ld b32 $r6 D[$r0 + #ctx_dst_address_high]
+       ld b32 $r7 D[$r0 + #ctx_dst_address_low]
+       shr b32 $r8 $r7 8
+       shl b32 $r6 0x18
+       or $r6 $r8
+       and $r7 $r7 0xff
+
+       // find the proper prep & do functions
+       ld b32 $r8 D[$r0 + #ctx_mode]
+       shl b32 $r8 2
+
+       // run prep
+       ld b16 $r9 D[$r8 + #sec_dtable]
+       call $r9
+
+       // do it
+       ld b16 $r9 D[$r8 + #sec_dtable + 2]
+       call $r9
+       cxset 1
+       xdwait
+       cxset 0x61
+       xdwait
+       xdwait
+
+       // update src address
+       shr b32 $r8 $r4 0x18
+       shl b32 $r9 $r4 8
+       add b32 $r9 $r5
+       adc b32 $r8 0
+       st b32 D[$r0 + #ctx_src_address_high] $r8
+       st b32 D[$r0 + #ctx_src_address_low] $r9
+
+       // update dst address
+       shr b32 $r8 $r6 0x18
+       shl b32 $r9 $r6 8
+       add b32 $r9 $r7
+       adc b32 $r8 0
+       st b32 D[$r0 + #ctx_dst_address_high] $r8
+       st b32 D[$r0 + #ctx_dst_address_low] $r9
+
+       // pull updated IV
+       cxset 2
+       mov $r4 #ctx_iv
+       sethi $r4 0x60000
+       xdld $r0 $r4
+       xdwait
+
+       ret
+
+
+sec_copy_prep:
+       cs0begin 2
+               cxsin $c0
+               cxsout $c0
+       ret
+
+sec_store_prep:
+       cs0begin 1
+               cxsout $c6
+       ret
+
+sec_ecb_e_prep:
+       cs0begin 3
+               cxsin $c0
+               cenc $c0 $c0
+               cxsout $c0
+       ret
+
+sec_ecb_d_prep:
+       ckexp $c7 $c7
+       cs0begin 3
+               cxsin $c0
+               cdec $c0 $c0
+               cxsout $c0
+       ret
+
+sec_cbc_e_prep:
+       cs0begin 4
+               cxsin $c0
+               cxor $c6 $c0
+               cenc $c6 $c6
+               cxsout $c6
+       ret
+
+sec_cbc_d_prep:
+       ckexp $c7 $c7
+       cs0begin 5
+               cmov $c2 $c6
+               cxsin $c6
+               cdec $c0 $c6
+               cxor $c0 $c2
+               cxsout $c0
+       ret
+
+sec_pcbc_e_prep:
+       cs0begin 5
+               cxsin $c0
+               cxor $c6 $c0
+               cenc $c6 $c6
+               cxsout $c6
+               cxor $c6 $c0
+       ret
+
+sec_pcbc_d_prep:
+       ckexp $c7 $c7
+       cs0begin 5
+               cxsin $c0
+               cdec $c1 $c0
+               cxor $c6 $c1
+               cxsout $c6
+               cxor $c6 $c0
+       ret
+
+sec_cfb_e_prep:
+       cs0begin 4
+               cenc $c6 $c6
+               cxsin $c0
+               cxor $c6 $c0
+               cxsout $c6
+       ret
+
+sec_cfb_d_prep:
+       cs0begin 4
+               cenc $c0 $c6
+               cxsin $c6
+               cxor $c0 $c6
+               cxsout $c0
+       ret
+
+sec_ofb_prep:
+       cs0begin 4
+               cenc $c6 $c6
+               cxsin $c0
+               cxor $c0 $c6
+               cxsout $c0
+       ret
+
+sec_ctr_prep:
+       cs0begin 5
+               cenc $c1 $c6
+               cadd $c6 1
+               cxsin $c0
+               cxor $c0 $c1
+               cxsout $c0
+       ret
+
+sec_cbc_mac_prep:
+       cs0begin 3
+               cxsin $c0
+               cxor $c6 $c0
+               cenc $c6 $c6
+       ret
+
+sec_cmac_finish_complete_prep:
+       cs0begin 7
+               cxsin $c0
+               cxor $c6 $c0
+               cxor $c0 $c0
+               cenc $c0 $c0
+               cprecmac $c0 $c0
+               cxor $c6 $c0
+               cenc $c6 $c6
+       ret
+
+sec_cmac_finish_partial_prep:
+       cs0begin 8
+               cxsin $c0
+               cxor $c6 $c0
+               cxor $c0 $c0
+               cenc $c0 $c0
+               cprecmac $c0 $c0
+               cprecmac $c0 $c0
+               cxor $c6 $c0
+               cenc $c6 $c6
+       ret
+
+// TODO
+sec_do_in:
+       add b32 $r3 $r5
+       mov $xdbase $r4
+       mov $r9 #swap
+       sethi $r9 0x20000
+       sec_do_in_loop:
+               xdld $r5 $r9
+               xdwait
+               cxset 0x22
+               xdst $r0 $r9
+               cs0exec 1
+               xdwait
+               add b32 $r5 0x10
+               cmpu b32 $r5 $r3
+       bra ne #sec_do_in_loop
+       cxset 1
+       xdwait
+       ret
+
+sec_do_out:
+       add b32 $r3 $r7
+       mov $xdbase $r6
+       mov $r9 #swap
+       sethi $r9 0x20000
+       sec_do_out_loop:
+               cs0exec 1
+               cxset 0x61
+               xdld $r7 $r9
+               xdst $r7 $r9
+               cxset 1
+               xdwait
+               add b32 $r7 0x10
+               cmpu b32 $r7 $r3
+       bra ne #sec_do_out_loop
+       ret
+
+sec_do_inout:
+       add b32 $r3 $r5
+       mov $r9 #swap
+       sethi $r9 0x20000
+       sec_do_inout_loop:
+               mov $xdbase $r4
+               xdld $r5 $r9
+               xdwait
+               cxset 0x21
+               xdst $r0 $r9
+               cs0exec 1
+               cxset 0x61
+               mov $xdbase $r6
+               xdld $r7 $r9
+               xdst $r7 $r9
+               cxset 1
+               xdwait
+               add b32 $r5 0x10
+               add b32 $r7 0x10
+               cmpu b32 $r5 $r3
+       bra ne #sec_do_inout_loop
+       ret
+
+.align 0x100
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/nv98.fuc0s.h
new file mode 100644 (file)
index 0000000..f7e1e13
--- /dev/null
@@ -0,0 +1,584 @@
+uint32_t nv98_psec_data[] = {
+/* 0x0000: ctx_dma */
+/* 0x0000: ctx_dma_query */
+       0x00000000,
+/* 0x0004: ctx_dma_src */
+       0x00000000,
+/* 0x0008: ctx_dma_dst */
+       0x00000000,
+/* 0x000c: ctx_query_address_high */
+       0x00000000,
+/* 0x0010: ctx_query_address_low */
+       0x00000000,
+/* 0x0014: ctx_query_counter */
+       0x00000000,
+/* 0x0018: ctx_cond_address_high */
+       0x00000000,
+/* 0x001c: ctx_cond_address_low */
+       0x00000000,
+/* 0x0020: ctx_cond_off */
+       0x00000000,
+/* 0x0024: ctx_src_address_high */
+       0x00000000,
+/* 0x0028: ctx_src_address_low */
+       0x00000000,
+/* 0x002c: ctx_dst_address_high */
+       0x00000000,
+/* 0x0030: ctx_dst_address_low */
+       0x00000000,
+/* 0x0034: ctx_mode */
+       0x00000000,
+       0x00000000,
+       0x00000000,
+/* 0x0040: ctx_key */
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+/* 0x0050: ctx_iv */
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+/* 0x0080: swap */
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+/* 0x00a0: common_cmd_dtable */
+       0x0002000c,
+       0xffffff00,
+       0x00020010,
+       0x0000000f,
+       0x00020014,
+       0x00000000,
+       0x00000192,
+       0xfffffffe,
+       0x00020018,
+       0xffffff00,
+       0x0002001c,
+       0x0000000f,
+       0x000001d7,
+       0xfffffff8,
+       0x00000260,
+       0xffffffff,
+/* 0x00e0: engine_cmd_dtable */
+       0x00020040,
+       0x00000000,
+       0x00020044,
+       0x00000000,
+       0x00020048,
+       0x00000000,
+       0x0002004c,
+       0x00000000,
+       0x00020050,
+       0x00000000,
+       0x00020054,
+       0x00000000,
+       0x00020058,
+       0x00000000,
+       0x0002005c,
+       0x00000000,
+       0x00020024,
+       0xffffff00,
+       0x00020028,
+       0x0000000f,
+       0x0002002c,
+       0xffffff00,
+       0x00020030,
+       0x0000000f,
+       0x00000271,
+       0xfffffff0,
+       0x00010285,
+       0xf000000f,
+/* 0x0150: sec_dtable */
+       0x04db0321,
+       0x04b1032f,
+       0x04db0339,
+       0x04db034b,
+       0x04db0361,
+       0x04db0377,
+       0x04db0395,
+       0x04db03af,
+       0x04db03cd,
+       0x04db03e3,
+       0x04db03f9,
+       0x04db040f,
+       0x04830429,
+       0x0483043b,
+       0x0483045d,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+};
+
+uint32_t nv98_psec_code[] = {
+       0x17f004bd,
+       0x0010fe35,
+       0xf10004fe,
+       0xf0fff017,
+       0x27f10013,
+       0x21d00400,
+       0x0c15f0c0,
+       0xf00021d0,
+       0x27f10317,
+       0x21d01200,
+       0x1031f400,
+/* 0x002f: spin */
+       0xf40031f4,
+       0x0ef40028,
+/* 0x0035: ih */
+       0x8001cffd,
+       0xb00812c4,
+       0x0bf40024,
+       0x0027f167,
+       0x002bfe77,
+       0xf00007fe,
+       0x23f00027,
+       0x0037f105,
+       0x0034cf14,
+       0xb0014594,
+       0x18f40055,
+       0x0602fa17,
+       0x4af003f8,
+       0x0034d01e,
+       0xd00147f0,
+       0x0ef48034,
+/* 0x0075: ctxload */
+       0x4034cf33,
+       0xb0014f94,
+       0x18f400f5,
+       0x0502fa21,
+       0x57f003f8,
+       0x0267f000,
+/* 0x008c: ctxload_dma_loop */
+       0xa07856bc,
+       0xb6018068,
+       0x87d00884,
+       0x0162b600,
+/* 0x009f: dummyload */
+       0xf0f018f4,
+       0x35d00257,
+/* 0x00a5: noctx */
+       0x0412c480,
+       0xf50024b0,
+       0xf100df0b,
+       0xcf190037,
+       0x33cf4032,
+       0xff24e400,
+       0x1024b607,
+       0x07bf45e4,
+       0xf50054b0,
+       0xf100b90b,
+       0xf1fae057,
+       0xb000ce67,
+       0x18f4c044,
+       0xa057f14d,
+       0x8867f1fc,
+       0x8044b000,
+       0xb03f18f4,
+       0x18f46044,
+       0x5044b019,
+       0xf1741bf4,
+       0xbd220027,
+       0x0233f034,
+       0xf50023d0,
+/* 0x0103: dma_cmd */
+       0xb000810e,
+       0x18f46344,
+       0x0245945e,
+       0xfe8050b7,
+       0x801e39f0,
+       0x40b70053,
+       0x44b60120,
+       0x0043d008,
+/* 0x0123: dtable_cmd */
+       0xb8600ef4,
+       0x18f40446,
+       0x0344b63e,
+       0x980045bb,
+       0x53fd0145,
+       0x0054b004,
+       0x58291bf4,
+       0x46580045,
+       0x0264b001,
+       0x98170bf4,
+       0x67fd0807,
+       0x0164b004,
+       0xf9300bf4,
+       0x0f01f455,
+/* 0x015b: cmd_setctx */
+       0x80280ef4,
+       0x0ef40053,
+/* 0x0161: invalid_bitfield */
+       0x0125f022,
+/* 0x0164: dispatch_error */
+/* 0x0164: illegal_mthd */
+       0x100047f1,
+       0xd00042d0,
+       0x47f04043,
+       0x0004d040,
+/* 0x0174: im_loop */
+       0xf08004cf,
+       0x44b04044,
+       0xf71bf400,
+/* 0x0180: cmddone */
+       0x1d0037f1,
+       0xd00147f0,
+/* 0x018a: nocmd */
+       0x11c40034,
+       0x4001d00c,
+/* 0x0192: cmd_query_get */
+       0x38f201f8,
+       0x0325f001,
+       0x0b0047f1,
+/* 0x019c: ptimer_retry */
+       0xcf4046cf,
+       0x47cf0045,
+       0x0467b840,
+       0x98f41bf4,
+       0x04800504,
+       0x21008020,
+       0x80220580,
+       0x0bfe2306,
+       0x03049800,
+       0xfe1844b6,
+       0x04980047,
+       0x8057f104,
+       0x0253f000,
+       0xf80645fa,
+/* 0x01d7: cmd_cond_mode */
+       0xf400f803,
+       0x25f00131,
+       0x0534b002,
+       0xf41218f4,
+       0x34b00132,
+       0x0b18f402,
+       0x800136f0,
+/* 0x01f2: return */
+       0x00f80803,
+/* 0x01f4: cmd_cond_mode_queryful */
+       0x98060498,
+       0x56c40705,
+       0x0855b6ff,
+       0xfd1844b6,
+       0x47fe0545,
+       0x000bfe00,
+       0x008057f1,
+       0xfa0253f0,
+       0x34b00565,
+       0x131bf402,
+       0x049803f8,
+       0x0044b021,
+       0x800b4cf0,
+       0x00f80804,
+/* 0x022c: cmd_cond_mode_double */
+       0xb61060b6,
+       0x65fa1050,
+       0x9803f805,
+       0x06982005,
+       0x0456b824,
+       0x980b4cf0,
+       0x06982105,
+       0x0456b825,
+       0xfd0b5cf0,
+       0x34b00445,
+       0x0b5cf003,
+       0x800645fd,
+       0x00f80804,
+/* 0x0260: cmd_wrcache_flush */
+       0xf10132f4,
+       0xbd220027,
+       0x0133f034,
+       0xf80023d0,
+/* 0x0271: sec_cmd_mode */
+       0x0131f400,
+       0xb00225f0,
+       0x18f40f34,
+       0x0132f409,
+/* 0x0283: sec_cmd_mode_return */
+       0xf80d0380,
+/* 0x0285: sec_cmd_length */
+       0x0034b000,
+       0xf4fb0bf4,
+       0x47f0033c,
+       0x0743f040,
+       0xf00604fa,
+       0x43f05047,
+       0x0604fa06,
+       0x3cf503f8,
+       0x47f1c407,
+       0x4bfe2100,
+       0x09049800,
+       0x950a0598,
+       0x44b60858,
+       0x0548fd18,
+       0x98ff55c4,
+       0x07980b06,
+       0x0878950c,
+       0xfd1864b6,
+       0x77c40568,
+       0x0d0898ff,
+       0x580284b6,
+       0x95f9a889,
+       0xf9a98958,
+       0x013cf495,
+       0x3cf403f8,
+       0xf803f861,
+       0x18489503,
+       0xbb084994,
+       0x81b60095,
+       0x09088000,
+       0x950a0980,
+       0x69941868,
+       0x0097bb08,
+       0x800081b6,
+       0x09800b08,
+       0x023cf40c,
+       0xf05047f0,
+       0x04fa0643,
+       0xf803f805,
+/* 0x0321: sec_copy_prep */
+       0x203cf500,
+       0x003cf594,
+       0x003cf588,
+/* 0x032f: sec_store_prep */
+       0xf500f88c,
+       0xf594103c,
+       0xf88c063c,
+/* 0x0339: sec_ecb_e_prep */
+       0x303cf500,
+       0x003cf594,
+       0x003cf588,
+       0x003cf5d0,
+/* 0x034b: sec_ecb_d_prep */
+       0xf500f88c,
+       0xf5c8773c,
+       0xf594303c,
+       0xf588003c,
+       0xf5d4003c,
+       0xf88c003c,
+/* 0x0361: sec_cbc_e_prep */
+       0x403cf500,
+       0x003cf594,
+       0x063cf588,
+       0x663cf5ac,
+       0x063cf5d0,
+/* 0x0377: sec_cbc_d_prep */
+       0xf500f88c,
+       0xf5c8773c,
+       0xf594503c,
+       0xf584623c,
+       0xf588063c,
+       0xf5d4603c,
+       0xf5ac203c,
+       0xf88c003c,
+/* 0x0395: sec_pcbc_e_prep */
+       0x503cf500,
+       0x003cf594,
+       0x063cf588,
+       0x663cf5ac,
+       0x063cf5d0,
+       0x063cf58c,
+/* 0x03af: sec_pcbc_d_prep */
+       0xf500f8ac,
+       0xf5c8773c,
+       0xf594503c,
+       0xf588003c,
+       0xf5d4013c,
+       0xf5ac163c,
+       0xf58c063c,
+       0xf8ac063c,
+/* 0x03cd: sec_cfb_e_prep */
+       0x403cf500,
+       0x663cf594,
+       0x003cf5d0,
+       0x063cf588,
+       0x063cf5ac,
+/* 0x03e3: sec_cfb_d_prep */
+       0xf500f88c,
+       0xf594403c,
+       0xf5d0603c,
+       0xf588063c,
+       0xf5ac603c,
+       0xf88c003c,
+/* 0x03f9: sec_ofb_prep */
+       0x403cf500,
+       0x663cf594,
+       0x003cf5d0,
+       0x603cf588,
+       0x003cf5ac,
+/* 0x040f: sec_ctr_prep */
+       0xf500f88c,
+       0xf594503c,
+       0xf5d0613c,
+       0xf5b0163c,
+       0xf588003c,
+       0xf5ac103c,
+       0xf88c003c,
+/* 0x0429: sec_cbc_mac_prep */
+       0x303cf500,
+       0x003cf594,
+       0x063cf588,
+       0x663cf5ac,
+/* 0x043b: sec_cmac_finish_complete_prep */
+       0xf500f8d0,
+       0xf594703c,
+       0xf588003c,
+       0xf5ac063c,
+       0xf5ac003c,
+       0xf5d0003c,
+       0xf5bc003c,
+       0xf5ac063c,
+       0xf8d0663c,
+/* 0x045d: sec_cmac_finish_partial_prep */
+       0x803cf500,
+       0x003cf594,
+       0x063cf588,
+       0x003cf5ac,
+       0x003cf5ac,
+       0x003cf5d0,
+       0x003cf5bc,
+       0x063cf5bc,
+       0x663cf5ac,
+/* 0x0483: sec_do_in */
+       0xbb00f8d0,
+       0x47fe0035,
+       0x8097f100,
+       0x0293f000,
+/* 0x0490: sec_do_in_loop */
+       0xf80559fa,
+       0x223cf403,
+       0xf50609fa,
+       0xf898103c,
+       0x1050b603,
+       0xf40453b8,
+       0x3cf4e91b,
+       0xf803f801,
+/* 0x04b1: sec_do_out */
+       0x0037bb00,
+       0xf10067fe,
+       0xf0008097,
+/* 0x04be: sec_do_out_loop */
+       0x3cf50293,
+       0x3cf49810,
+       0x0579fa61,
+       0xf40679fa,
+       0x03f8013c,
+       0xb81070b6,
+       0x1bf40473,
+/* 0x04db: sec_do_inout */
+       0xbb00f8e8,
+       0x97f10035,
+       0x93f00080,
+/* 0x04e5: sec_do_inout_loop */
+       0x0047fe02,
+       0xf80559fa,
+       0x213cf403,
+       0xf50609fa,
+       0xf498103c,
+       0x67fe613c,
+       0x0579fa00,
+       0xf40679fa,
+       0x03f8013c,
+       0xb61050b6,
+       0x53b81070,
+       0xd41bf404,
+       0x000000f8,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/nv98.c
new file mode 100644 (file)
index 0000000..10d0d1f
--- /dev/null
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <core/client.h>
+#include <core/os.h>
+#include <core/enum.h>
+#include <core/engctx.h>
+
+#include <subdev/timer.h>
+#include <subdev/fb.h>
+
+#include <engine/falcon.h>
+#include <engine/fifo.h>
+#include <engine/sec.h>
+
+#include "fuc/nv98.fuc0s.h"
+
+struct nv98_sec_priv {
+       struct nouveau_falcon base;
+};
+
+/*******************************************************************************
+ * Crypt object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_sec_sclass[] = {
+       { 0x88b4, &nouveau_object_ofuncs },
+       {},
+};
+
+/*******************************************************************************
+ * PSEC context
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_sec_cclass = {
+       .handle = NV_ENGCTX(SEC, 0x98),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = _nouveau_falcon_context_ctor,
+               .dtor = _nouveau_falcon_context_dtor,
+               .init = _nouveau_falcon_context_init,
+               .fini = _nouveau_falcon_context_fini,
+               .rd32 = _nouveau_falcon_context_rd32,
+               .wr32 = _nouveau_falcon_context_wr32,
+       },
+};
+
+/*******************************************************************************
+ * PSEC engine/subdev functions
+ ******************************************************************************/
+
+static const struct nouveau_enum nv98_sec_isr_error_name[] = {
+       { 0x0000, "ILLEGAL_MTHD" },
+       { 0x0001, "INVALID_BITFIELD" },
+       { 0x0002, "INVALID_ENUM" },
+       { 0x0003, "QUERY" },
+       {}
+};
+
+static void
+nv98_sec_intr(struct nouveau_subdev *subdev)
+{
+       struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
+       struct nouveau_engine *engine = nv_engine(subdev);
+       struct nouveau_object *engctx;
+       struct nv98_sec_priv *priv = (void *)subdev;
+       u32 disp = nv_rd32(priv, 0x08701c);
+       u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
+       u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
+       u32 ssta = nv_rd32(priv, 0x087040) & 0x0000ffff;
+       u32 addr = nv_rd32(priv, 0x087040) >> 16;
+       u32 mthd = (addr & 0x07ff) << 2;
+       u32 subc = (addr & 0x3800) >> 11;
+       u32 data = nv_rd32(priv, 0x087044);
+       int chid;
+
+       engctx = nouveau_engctx_get(engine, inst);
+       chid   = pfifo->chid(pfifo, engctx);
+
+       if (stat & 0x00000040) {
+               nv_error(priv, "DISPATCH_ERROR [");
+               nouveau_enum_print(nv98_sec_isr_error_name, ssta);
+               pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
+                      chid, (u64)inst << 12, nouveau_client_name(engctx),
+                      subc, mthd, data);
+               nv_wr32(priv, 0x087004, 0x00000040);
+               stat &= ~0x00000040;
+       }
+
+       if (stat) {
+               nv_error(priv, "unhandled intr 0x%08x\n", stat);
+               nv_wr32(priv, 0x087004, stat);
+       }
+
+       nouveau_engctx_put(engctx);
+}
+
+static int
+nv98_sec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+              struct nouveau_oclass *oclass, void *data, u32 size,
+              struct nouveau_object **pobject)
+{
+       struct nv98_sec_priv *priv;
+       int ret;
+
+       ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true,
+                                   "PSEC", "sec", &priv);
+       *pobject = nv_object(priv);
+       if (ret)
+               return ret;
+
+       nv_subdev(priv)->unit = 0x00004000;
+       nv_subdev(priv)->intr = nv98_sec_intr;
+       nv_engine(priv)->cclass = &nv98_sec_cclass;
+       nv_engine(priv)->sclass = nv98_sec_sclass;
+       nv_falcon(priv)->code.data = nv98_psec_code;
+       nv_falcon(priv)->code.size = sizeof(nv98_psec_code);
+       nv_falcon(priv)->data.data = nv98_psec_data;
+       nv_falcon(priv)->data.size = sizeof(nv98_psec_data);
+       return 0;
+}
+
+struct nouveau_oclass
+nv98_sec_oclass = {
+       .handle = NV_ENGINE(SEC, 0x98),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = nv98_sec_ctor,
+               .dtor = _nouveau_falcon_dtor,
+               .init = _nouveau_falcon_init,
+               .fini = _nouveau_falcon_fini,
+               .rd32 = _nouveau_falcon_rd32,
+               .wr32 = _nouveau_falcon_wr32,
+       },
+};
index a7c80ded77cdce591f65c035e8cd69f88db7dc8a..c4f4c158dc1b296168b781df43f36c90caf33fea 100644 (file)
@@ -36,7 +36,7 @@ nv84_devinit_disable(struct nouveau_devinit *devinit)
                disable |= (1ULL << NVDEV_ENGINE_MPEG);
                disable |= (1ULL << NVDEV_ENGINE_VP);
                disable |= (1ULL << NVDEV_ENGINE_BSP);
-               disable |= (1ULL << NVDEV_ENGINE_CRYPT);
+               disable |= (1ULL << NVDEV_ENGINE_CIPHER);
        }
 
        if (!(r00154c & 0x00000004))
@@ -44,7 +44,7 @@ nv84_devinit_disable(struct nouveau_devinit *devinit)
        if (!(r00154c & 0x00000020))
                disable |= (1ULL << NVDEV_ENGINE_BSP);
        if (!(r00154c & 0x00000040))
-               disable |= (1ULL << NVDEV_ENGINE_CRYPT);
+               disable |= (1ULL << NVDEV_ENGINE_CIPHER);
 
        return disable;
 }
index 820f069fbaac068972322a4c66499ad9067296b9..b27984bbfebb0f0cf06e13b121ae85e8187c56c2 100644 (file)
@@ -43,7 +43,7 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
        if (!(r00154c & 0x00000020))
                disable |= (1ULL << NVDEV_ENGINE_MSVLD);
        if (!(r00154c & 0x00000040))
-               disable |= (1ULL << NVDEV_ENGINE_CRYPT);
+               disable |= (1ULL << NVDEV_ENGINE_SEC);
 
        return disable;
 }
index df07c046213e3de771d5c7d9e46111816f167378..31c90dbea579880d0419ae0f292312b206234ed4 100644 (file)
@@ -124,7 +124,7 @@ static const struct nouveau_enum vm_engine[] = {
        { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
        { 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
        { 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
-       { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT },
+       { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },
        { 0x0000000b, "PCOUNTER", NULL },
        { 0x0000000c, "SEMAPHORE_BG", NULL },
        { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
@@ -192,6 +192,8 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
                        /*XXX: clean this up */
                        if (!engine && en->data2 == NVDEV_ENGINE_BSP)
                                engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD);
+                       if (!engine && en->data2 == NVDEV_ENGINE_CIPHER)
+                               engine = nouveau_engine(subdev, NVDEV_ENGINE_SEC);
                        if (engine) {
                                engctx = nouveau_engctx_get(engine, chan);
                                if (engctx)
index 9ca93e2718f79d50fca7436bacf639ac88588733..9100f2875636d61a36697aafe8bd4c54654e8de6 100644 (file)
@@ -30,7 +30,7 @@ nv50_mc_intr[] = {
        { 0x00000001, NVDEV_ENGINE_MPEG },
        { 0x00000100, NVDEV_ENGINE_FIFO },
        { 0x00001000, NVDEV_ENGINE_GR },
-       { 0x00004000, NVDEV_ENGINE_CRYPT },     /* NV84- */
+       { 0x00004000, NVDEV_ENGINE_CIPHER },    /* NV84- */
        { 0x00008000, NVDEV_ENGINE_BSP },       /* NV84- */
        { 0x00020000, NVDEV_ENGINE_VP },        /* NV84- */
        { 0x00100000, NVDEV_SUBDEV_TIMER },
index bb1346f6fa1286b7132d51f80e3bf9b09485f97c..17ea7e74ed2867eff0c9449cdeee1eac03c94c14 100644 (file)
@@ -30,7 +30,7 @@ nv98_mc_intr[] = {
        { 0x00000001, NVDEV_ENGINE_PPP },
        { 0x00000100, NVDEV_ENGINE_FIFO },
        { 0x00001000, NVDEV_ENGINE_GR },
-       { 0x00004000, NVDEV_ENGINE_CRYPT },     /* NV84:NVA3 */
+       { 0x00004000, NVDEV_ENGINE_SEC },       /* NV84:NVA3 */
        { 0x00008000, NVDEV_ENGINE_MSVLD },
        { 0x00020000, NVDEV_ENGINE_VP },
        { 0x00040000, NVDEV_SUBDEV_PMU },       /* NVA3:NVC0 */
index eabf2bab1d100bc4e7eabd5b4ede370b492681f5..9a8cbfb0718e4a44fb7fdbf390bed36355a78cde 100644 (file)
@@ -171,15 +171,16 @@ nv50_vm_flush(struct nouveau_vm *vm)
                }
 
                switch (i) {
-               case NVDEV_ENGINE_GR   : vme = 0x00; break;
-               case NVDEV_ENGINE_VP   : vme = 0x01; break;
-               case NVDEV_SUBDEV_BAR  : vme = 0x06; break;
-               case NVDEV_ENGINE_PPP  :
-               case NVDEV_ENGINE_MPEG : vme = 0x08; break;
-               case NVDEV_ENGINE_BSP  :
-               case NVDEV_ENGINE_MSVLD: vme = 0x09; break;
-               case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;
-               case NVDEV_ENGINE_COPY0: vme = 0x0d; break;
+               case NVDEV_ENGINE_GR    : vme = 0x00; break;
+               case NVDEV_ENGINE_VP    : vme = 0x01; break;
+               case NVDEV_SUBDEV_BAR   : vme = 0x06; break;
+               case NVDEV_ENGINE_PPP   :
+               case NVDEV_ENGINE_MPEG  : vme = 0x08; break;
+               case NVDEV_ENGINE_BSP   :
+               case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
+               case NVDEV_ENGINE_CIPHER:
+               case NVDEV_ENGINE_SEC   : vme = 0x0a; break;
+               case NVDEV_ENGINE_COPY0 : vme = 0x0d; break;
                default:
                        continue;
                }