.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
.fourcc = V4L2_PIX_FMT_RGB565,
- .lcd_cfg = lcdc0_modes,
- .num_cfg = ARRAY_SIZE(lcdc0_modes),
+ .lcd_modes = lcdc0_modes,
+ .num_modes = ARRAY_SIZE(lcdc0_modes),
.panel_cfg = {
.width = 44,
.height = 79,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
- .lcd_cfg = ap4evb_lcdc_modes,
- .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
+ .lcd_modes = ap4evb_lcdc_modes,
+ .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
.meram_cfg = &lcd_meram_cfg,
#ifdef CONFIG_AP4EVB_QHD
.tx_dev = &mipidsi0_device,
.interface_type = RGB24,
.clock_divider = 5,
.flags = 0,
- .lcd_cfg = &lcdc0_mode,
- .num_cfg = 1,
+ .lcd_modes = &lcdc0_mode,
+ .num_modes = 1,
.panel_cfg = {
.width = 152,
.height = 91,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
.fourcc = V4L2_PIX_FMT_RGB565,
- .lcd_cfg = mackerel_lcdc_modes,
- .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
+ .lcd_modes = mackerel_lcdc_modes,
+ .num_modes = ARRAY_SIZE(mackerel_lcdc_modes),
.interface_type = RGB24,
.clock_divider = 3,
.flags = 0,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB18,
.clock_divider = 1,
- .lcd_cfg = ap325rxa_lcdc_modes,
- .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
+ .lcd_modes = ap325rxa_lcdc_modes,
+ .num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
.panel_cfg = {
.width = 152, /* 7.0 inch */
.height = 91,
/* DVI */
lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
lcdc_info.ch[0].clock_divider = 1;
- lcdc_info.ch[0].lcd_cfg = ecovec_dvi_modes;
- lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_dvi_modes);
+ lcdc_info.ch[0].lcd_modes = ecovec_dvi_modes;
+ lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_dvi_modes);
gpio_set_value(GPIO_PTA2, 1);
gpio_set_value(GPIO_PTU1, 1);
/* Panel */
lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
lcdc_info.ch[0].clock_divider = 2;
- lcdc_info.ch[0].lcd_cfg = ecovec_lcd_modes;
- lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_lcd_modes);
+ lcdc_info.ch[0].lcd_modes = ecovec_lcd_modes;
+ lcdc_info.ch[0].num_modes = ARRAY_SIZE(ecovec_lcd_modes);
gpio_set_value(GPIO_PTR1, 1);
.interface_type = SYS18,
.clock_divider = 6,
.flags = LCDC_FLAGS_DWPOL,
- .lcd_cfg = kfr2r09_lcdc_modes,
- .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
+ .lcd_modes = kfr2r09_lcdc_modes,
+ .num_modes = ARRAY_SIZE(kfr2r09_lcdc_modes),
.panel_cfg = {
.width = 35,
.height = 58,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB16,
.clock_divider = 2,
- .lcd_cfg = migor_lcd_modes,
- .num_cfg = ARRAY_SIZE(migor_lcd_modes),
+ .lcd_modes = migor_lcd_modes,
+ .num_modes = ARRAY_SIZE(migor_lcd_modes),
.panel_cfg = { /* 7.0 inch */
.width = 152,
.height = 91,
.fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = SYS16A,
.clock_divider = 10,
- .lcd_cfg = migor_lcd_modes,
- .num_cfg = ARRAY_SIZE(migor_lcd_modes),
+ .lcd_modes = migor_lcd_modes,
+ .num_modes = ARRAY_SIZE(migor_lcd_modes),
.panel_cfg = {
.width = 49, /* 2.4 inch */
.height = 37,
if (sw & SW41_B) {
/* 720p */
- lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
- lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
+ lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
+ lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
} else {
/* VGA */
- lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
- lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
+ lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
+ lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
}
if (sw & SW41_A) {
pctype = 0;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg[0].xres * 3;
+ linelength = ch->lcd_modes[0].xres * 3;
yuv = false;
break;
case MIPI_RGB565:
pctype = 1;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg[0].xres * 2;
+ linelength = ch->lcd_modes[0].xres * 2;
yuv = false;
break;
case MIPI_RGB666_LP:
pctype = 2;
datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg[0].xres * 3;
+ linelength = ch->lcd_modes[0].xres * 3;
yuv = false;
break;
case MIPI_RGB666:
pctype = 3;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
- linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
+ linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
yuv = false;
break;
case MIPI_BGR888:
pctype = 8;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg[0].xres * 3;
+ linelength = ch->lcd_modes[0].xres * 3;
yuv = false;
break;
case MIPI_BGR565:
pctype = 9;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg[0].xres * 2;
+ linelength = ch->lcd_modes[0].xres * 2;
yuv = false;
break;
case MIPI_BGR666_LP:
pctype = 0xa;
datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
- linelength = ch->lcd_cfg[0].xres * 3;
+ linelength = ch->lcd_modes[0].xres * 3;
yuv = false;
break;
case MIPI_BGR666:
pctype = 0xb;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
- linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
+ linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
yuv = false;
break;
case MIPI_YUYV:
pctype = 4;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg[0].xres * 2;
+ linelength = ch->lcd_modes[0].xres * 2;
yuv = true;
break;
case MIPI_UYVY:
pctype = 5;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
- linelength = ch->lcd_cfg[0].xres * 2;
+ linelength = ch->lcd_modes[0].xres * 2;
yuv = true;
break;
case MIPI_YUV420_L:
pctype = 6;
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
- linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
+ linelength = (ch->lcd_modes[0].xres * 12 + 7) / 8;
yuv = true;
break;
case MIPI_YUV420:
datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
/* Length of U/V line */
- linelength = (ch->lcd_cfg[0].xres + 1) / 2;
+ linelength = (ch->lcd_modes[0].xres + 1) / 2;
yuv = true;
break;
default:
*/
iowrite32(0x00000006, mipi->linkbase + DTCTR);
/* VSYNC width = 2 (<< 17) */
- iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) |
+ iowrite32((ch->lcd_modes[0].vsync_len << pdata->vsynw_offset) |
(pdata->clksrc << 16) | (pctype << 12) | datatype,
mipi->linkbase + VMCTR1);
top = linelength << 16; /* RGBLEN */
bottom = 0x00000001;
if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
- bottom = (pdata->lane * ch->lcd_cfg[0].hsync_len) - 10;
+ bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
iowrite32(top | bottom , mipi->linkbase + VMLEN1);
/*
div = 2;
if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
- top = ch->lcd_cfg[0].hsync_len + ch->lcd_cfg[0].left_margin;
+ top = ch->lcd_modes[0].hsync_len + ch->lcd_modes[0].left_margin;
top = ((pdata->lane * top / div) - 10) << 16;
}
if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
- bottom = ch->lcd_cfg[0].right_margin;
+ bottom = ch->lcd_modes[0].right_margin;
bottom = (pdata->lane * bottom / div) - 12;
}
- bpp = linelength / ch->lcd_cfg[0].xres; /* byte / pixel */
+ bpp = linelength / ch->lcd_modes[0].xres; /* byte / pixel */
if ((pdata->lane / div) > bpp) {
- tmp = ch->lcd_cfg[0].xres / bpp; /* output cycle */
- tmp = ch->lcd_cfg[0].xres - tmp; /* (input - output) cycle */
+ tmp = ch->lcd_modes[0].xres / bpp; /* output cycle */
+ tmp = ch->lcd_modes[0].xres - tmp; /* (input - output) cycle */
delay = (pdata->lane * tmp);
}
* distance between two modes is defined as the size of the
* non-overlapping parts of the two rectangles.
*/
- for (i = 0; i < ch->cfg.num_cfg; ++i) {
- const struct fb_videomode *mode = &ch->cfg.lcd_cfg[i];
+ for (i = 0; i < ch->cfg.num_modes; ++i) {
+ const struct fb_videomode *mode = &ch->cfg.lcd_modes[i];
unsigned int dist;
/* We can only round up. */
}
/* If no available mode can be used, return an error. */
- if (ch->cfg.num_cfg != 0) {
+ if (ch->cfg.num_modes != 0) {
if (best_dist == (unsigned int)-1)
return -EINVAL;
struct fb_var_screeninfo *var;
struct fb_info *info;
unsigned int max_size;
- int num_cfg;
+ int num_modes;
void *buf;
int ret;
int i;
max_mode = NULL;
max_size = 0;
- for (i = 0, mode = cfg->lcd_cfg; i < cfg->num_cfg; i++, mode++) {
+ for (i = 0, mode = cfg->lcd_modes; i < cfg->num_modes; i++, mode++) {
unsigned int size = mode->yres * mode->xres;
/* NV12/NV21 buffers must have even number of lines */
max_mode->xres, max_mode->yres);
/* Create the mode list. */
- if (cfg->lcd_cfg == NULL) {
+ if (cfg->lcd_modes == NULL) {
mode = &default_720p;
- num_cfg = 1;
+ num_modes = 1;
} else {
- mode = cfg->lcd_cfg;
- num_cfg = cfg->num_cfg;
+ mode = cfg->lcd_modes;
+ num_modes = cfg->num_modes;
}
- fb_videomode_to_modelist(mode, num_cfg, &info->modelist);
+ fb_videomode_to_modelist(mode, num_modes, &info->modelist);
/* Initialize the transmitter device if present. */
if (cfg->tx_dev) {
int interface_type; /* selects RGBn or SYSn I/F, see above */
int clock_divider;
unsigned long flags; /* LCDC_FLAGS_... */
- const struct fb_videomode *lcd_cfg;
- int num_cfg;
+ const struct fb_videomode *lcd_modes;
+ int num_modes;
struct sh_mobile_lcdc_panel_cfg panel_cfg;
struct sh_mobile_lcdc_bl_info bl_info;
struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */