Recognize a few more documented register name aliases for ARM in the asm lexer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122523 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp b/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp
index e79a332f7eb60acc55da92deea1d72738aa4d6af..c93fb248e7a0dd8d82394d0b6ac40f3dcef6c25c 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp
@@ -121,6 +121,24 @@ AsmToken ARMBaseAsmLexer::LexTokenUAL() {
     StringRef lowerRef(lowerCase);
 
     unsigned regID = MatchRegisterName(lowerRef);
+    // Check for register aliases.
+    //   r13 -> sp
+    //   r14 -> lr
+    //   r15 -> pc
+    //   ip  -> r12
+    //   FIXME: Some assemblers support lots of others. Do we want them all?
+    if (!regID) {
+     if (lowerCase.size() == 3 && lowerCase[0] == 'r'
+        && lowerCase[1] == '1') {
+       switch (lowerCase[2]) {
+       default: break;
+       case '3': regID = ARM::SP;
+       case '4': regID = ARM::LR;
+       case '5': regID = ARM::PC;
+       }
+     } else if (lowerCase == "ip")
+       regID = ARM::R12;
+    }
 
     if (regID) {
       return AsmToken(AsmToken::Register,