drm/i915/chv: Move data lane deassert to encoder pre_enable

We need to pick the correct data lanes based on the port not the
pipe, so move the data lane deassert into the encoder .pre_enable()
hook from the chv_enable_pll().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fb1b6184ddf2edfd9016dc0aebcc13ff2a39adac..39f37bb7a16a690b9424da4af7289500076b3bea 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1603,11 +1603,6 @@ static void chv_enable_pll(struct intel_crtc *crtc)
        I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
        POSTING_READ(DPLL_MD(pipe));
 
-       /* Deassert soft data lane reset*/
-       tmp = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
-       tmp |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), tmp);
-
        mutex_unlock(&dev_priv->dpio_lock);
 }
 

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7f2dc72b65d1f931afd1010378b8f21ad7c7b251..da1d0dffacc3cf23f8c0758a4209c15c8c3775f7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1994,9 +1994,16 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
        enum dpio_channel ch = vlv_dport_to_channel(dport);
        int pipe = intel_crtc->pipe;
        int data, i;
+       u32 val;
 
-       /* Program Tx lane latency optimal setting*/
        mutex_lock(&dev_priv->dpio_lock);
+
+       /* Deassert soft data lane reset*/
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+       /* Program Tx lane latency optimal setting*/
        for (i = 0; i < 4; i++) {
                /* Set the latency optimal bit */
                data = (i == 1) ? 0x0 : 0x6;

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 6b635f7a86d86e49f1e9c1c8e73fff735ce8d8f5..ca6ca5a17aec6e8364bce28562a21326c29df959 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1257,8 +1257,14 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
        int data, i;
        u32 val;
 
-       /* Program Tx latency optimal setting */
        mutex_lock(&dev_priv->dpio_lock);
+
+       /* Deassert soft data lane reset*/
+       val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+       val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+       vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+
+       /* Program Tx latency optimal setting */
        for (i = 0; i < 4; i++) {
                /* Set the latency optimal bit */
                data = (i == 1) ? 0x0 : 0x6;