Merge branch 'tracking-armlt-cci' into lsk-3.10-vexpress

Conflicts:
	arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

diff --cc arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index f51f21a66352392d8a6d7bdbedec9e8ae8ac8016,9d802fc71fcfe77432e71724d272468b67a1d3ed..eea14dad38167994773fcb2eab1c5fa1035fd3fe
--- 1/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
--- 2/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@@ -81,47 -51,22 +81,51 @@@
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <0x100>;
 +                      cluster = <&cluster1>;
 +                      core = <&core2>;
 +                      clock-frequency = <800000000>;
+                       cci-control-port = <&cci_control2>;
                };
  
                cpu3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <0x101>;
 +                      cluster = <&cluster1>;
 +                      core = <&core3>;
 +                      clock-frequency = <800000000>;
+                       cci-control-port = <&cci_control2>;
                };
  
                cpu4: cpu@4 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
                        reg = <0x102>;
 +                      cluster = <&cluster1>;
 +                      core = <&core4>;
 +                      clock-frequency = <800000000>;
+                       cci-control-port = <&cci_control2>;
                };
- 
 +
 +              cpu0: cpu@0 {
 +                      device_type = "cpu";
 +                      compatible = "arm,cortex-a15";
 +                      reg = <0>;
 +                      cluster = <&cluster0>;
 +                      core = <&core0>;
 +                      clock-frequency = <1000000000>;
++                      cci-control-port = <&cci_control1>;
 +              };
 +
 +              cpu1: cpu@1 {
 +                      device_type = "cpu";
 +                      compatible = "arm,cortex-a15";
 +                      reg = <1>;
 +                      cluster = <&cluster0>;
 +                      core = <&core1>;
 +                      clock-frequency = <1000000000>;
++                      cci-control-port = <&cci_control1>;
 +              };
        };
  
        memory@80000000 {
@@@ -164,36 -107,38 +168,66 @@@
                      <0 0x2c004000 0 0x2000>,
                      <0 0x2c006000 0 0x2000>;
                interrupts = <1 9 0xf04>;
 +
 +              gic-cpuif@0 {
 +                      compatible = "arm,gic-cpuif";
 +                      cpuif-id = <0>;
 +                      cpu = <&cpu0>;
 +              };
 +              gic-cpuif@1 {
 +                      compatible = "arm,gic-cpuif";
 +                      cpuif-id = <1>;
 +                      cpu = <&cpu1>;
 +              };
 +              gic-cpuif@2 {
 +                      compatible = "arm,gic-cpuif";
 +                      cpuif-id = <2>;
 +                      cpu = <&cpu2>;
 +              };
 +
 +              gic-cpuif@3 {
 +                      compatible = "arm,gic-cpuif";
 +                      cpuif-id = <3>;
 +                      cpu = <&cpu3>;
 +              };
 +
 +              gic-cpuif@4 {
 +                      compatible = "arm,gic-cpuif";
 +                      cpuif-id = <4>;
 +                      cpu = <&cpu4>;
 +              };
        };
  
+       cci@2c090000 {
+               compatible = "arm,cci-400";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0 0x2c090000 0 0x1000>;
+               ranges = <0x0 0x0 0x2c090000 0x10000>;
+ 
+               cci_control1: slave-if@4000 {
+                       compatible = "arm,cci-400-ctrl-if";
+                       interface-type = "ace";
+                       reg = <0x4000 0x1000>;
+               };
+ 
+               cci_control2: slave-if@5000 {
+                       compatible = "arm,cci-400-ctrl-if";
+                       interface-type = "ace";
+                       reg = <0x5000 0x1000>;
+               };
+       };
+ 
+       cci-pmu@2c099000 {
+               compatible = "arm,cci-400-pmu";
+               reg = <0 0x2c099000 0 0x6000>;
+               interrupts = <0 101 4>,
+                            <0 102 4>,
+                            <0 103 4>,
+                            <0 104 4>,
+                            <0 105 4>;
+       };
+ 
        memory-controller@7ffd0000 {
                compatible = "arm,pl354", "arm,primecell";
                reg = <0 0x7ffd0000 0 0x1000>;