Move function-live-in-handling code from the sdisel code to the scheduler.

This code should be emitted after legalize, so it can't be in sdisel.

Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG.  The X86 backend is the only one currently using this hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28315 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3fab99e372737152b188e1c272ff54a99154a519..523062053d881f259fe4f36ab4c367b5c0c42e98 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -539,6 +539,20 @@ void ScheduleDAG::EmitNoop() {
 
 /// EmitSchedule - Emit the machine code in scheduled order.
 void ScheduleDAG::EmitSchedule() {
+  // If this is the first basic block in the function, and if it has live ins
+  // that need to be copied into vregs, emit the copies into the top of the
+  // block before emitting the code for the block.
+  MachineFunction &MF = DAG.getMachineFunction();
+  if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
+    for (MachineFunction::livein_iterator LI = MF.livein_begin(),
+         E = MF.livein_end(); LI != E; ++LI)
+      if (LI->second)
+        MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
+                          LI->first, RegMap->getRegClass(LI->second));
+  }
+  
+  
+  // Finally, emit the code for all of the scheduled instructions.
   std::map<SDNode*, unsigned> VRBaseMap;
   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
     if (SUnit *SU = Sequence[i]) {

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index cc34d5196976f54ccab398ac3a21e8d599f156c6..1cac134187269df30ff2f2c601d2f9542ca44c1c 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3150,24 +3150,11 @@ LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
       }
     }
 
-  // Next, if the function has live ins that need to be copied into vregs,
-  // emit the copies now, into the top of the block.
-  MachineFunction &MF = SDL.DAG.getMachineFunction();
-  if (MF.livein_begin() != MF.livein_end()) {
-    SSARegMap *RegMap = MF.getSSARegMap();
-    const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
-    for (MachineFunction::livein_iterator LI = MF.livein_begin(),
-         E = MF.livein_end(); LI != E; ++LI)
-      if (LI->second)
-        MRI.copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
-                         LI->first, RegMap->getRegClass(LI->second));
-  }
-    
   // Finally, if the target has anything special to do, allow it to do so.
+  // FIXME: this should insert code into the DAG!
   EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
 }
 
-
 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
        std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
                                          FunctionLoweringInfo &FuncInfo) {