cl::desc("Form IT blocks early before register allocation"),
cl::init(false));
-static cl::opt<bool>
-EarlyIfConvert("arm-early-if-convert", cl::Hidden,
- cl::desc("Run if-conversion before post-ra scheduling"),
- cl::init(false));
-
static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
Triple TheTriple(TT);
switch (TheTriple.getOS()) {
// proper scheduling.
PM.add(createARMExpandPseudoPass());
- if (EarlyIfConvert && OptLevel != CodeGenOpt::None) {
+ if (OptLevel != CodeGenOpt::None) {
if (!Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
if (Subtarget.isThumb2())
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
- if (!EarlyIfConvert && OptLevel != CodeGenOpt::None) {
- if (!Subtarget.isThumb1Only())
- PM.add(createIfConverterPass());
- }
-
- if (Subtarget.isThumb2()) {
- if (!EarlyIfConvert)
- PM.add(createThumb2ITBlockPass());
+ if (Subtarget.isThumb2())
PM.add(createThumb2SizeReductionPass());
- }
PM.add(createARMConstantIslandPass());
return true;
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
; CHECK: t1
; CHECK: sub.w r0, r1, #-2147483648
+; CHECK: subs r0, #1
; CHECK: cmp r2, #10
-; CHECK: sub.w r0, r0, #1
; CHECK: it gt
; CHECK: movgt r0, r1
%tmp1 = icmp sgt i32 %c, 10