Fix opcode: no immediate in an `or r1, r2, r3' (all registers) instr.
authorMisha Brukman <brukman+llvm@gmail.com>
Fri, 25 Jun 2004 18:36:53 +0000 (18:36 +0000)
committerMisha Brukman <brukman+llvm@gmail.com>
Fri, 25 Jun 2004 18:36:53 +0000 (18:36 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14411 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC32ISelSimple.cpp
lib/Target/PowerPC/PowerPCISelSimple.cpp

index 6f214f88cfdb94cc3639f56bc92aea9620544d3e..a75a4b0aaaeeae594859f364cc9649be07feae39 100644 (file)
@@ -1052,7 +1052,7 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
     break;
   case cInt:
     // Move value into target register (32->32)
-    BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(Reg).addReg(Reg);
+    BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
     break;
   default:
     assert(0 && "Unpromotable operand class in promote32");
index 6f214f88cfdb94cc3639f56bc92aea9620544d3e..a75a4b0aaaeeae594859f364cc9649be07feae39 100644 (file)
@@ -1052,7 +1052,7 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
     break;
   case cInt:
     // Move value into target register (32->32)
-    BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(Reg).addReg(Reg);
+    BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
     break;
   default:
     assert(0 && "Unpromotable operand class in promote32");