const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << TRI->getAsmName(MO1.getReg());
// Print the shift opc.
O << ", "
if (MO2.getReg()) {
assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
- O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
+ O << TRI->getAsmName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
return;
}
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
if (!MO2.getReg()) {
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
O << ", "
<< (char)ARM_AM::getAM2Op(MO3.getImm())
- << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
+ << TRI->getAsmName(MO2.getReg());
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
}
O << (char)ARM_AM::getAM2Op(MO2.getImm())
- << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ << TRI->getAsmName(MO1.getReg());
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
if (MO2.getReg()) {
O << ", "
<< (char)ARM_AM::getAM3Op(MO3.getImm())
- << TM.getRegisterInfo()->get(MO2.getReg()).AsmName
+ << TRI->getAsmName(MO2.getReg())
<< "]";
return;
}
if (MO1.getReg()) {
O << (char)ARM_AM::getAM3Op(MO2.getImm())
- << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ << TRI->getAsmName(MO1.getReg());
return;
}
return;
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
- O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << TRI->getAsmName(MO1.getReg());
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
O << ", #"
const MachineOperand &MO3 = MI->getOperand(Op+2);
// FIXME: No support yet for specifying alignment.
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
+ O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
if (MO2.getReg() == 0)
O << "!";
else
- O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
+ O << ", " << TRI->getAsmName(MO2.getReg());
}
}
const MachineOperand &MO1 = MI->getOperand(Op);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
+ O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
}
void
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
- O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName << "]";
+ O << "[" << TRI->getAsmName(MO1.getReg());
+ O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
}
void
return;
}
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
if (MO3.getReg())
- O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
+ O << ", " << TRI->getAsmName(MO3.getReg());
else if (unsigned ImmOffs = MO2.getImm()) {
O << ", #" << ImmOffs;
if (Scale > 1)
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
if (unsigned ImmOffs = MO2.getImm())
O << ", #" << ImmOffs << " * 4";
O << "]";
unsigned Reg = MO1.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
- O << TM.getRegisterInfo()->getAsmName(Reg);
+ O << TRI->getAsmName(Reg);
// Print the shift opc.
O << ", "
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
unsigned OffImm = MO2.getImm();
if (OffImm) // Don't print +0.
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm();
// Don't print +0.
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm() / 4;
// Don't print +0.
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
- O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
+ O << "[" << TRI->getAsmName(MO1.getReg());
if (MO2.getReg()) {
- O << ", +"
- << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
+ O << ", +" << TRI->getAsmName(MO2.getReg());
unsigned ShAmt = MO3.getImm();
if (ShAmt) {