source "drivers/video/rockchip/tve/Kconfig"
source "drivers/video/rockchip/rga/Kconfig"
source "drivers/video/rockchip/rga2/Kconfig"
+source "drivers/video/rockchip/iep/Kconfig"
obj-$(CONFIG_ROCKCHIP_RGA) += rga/
obj-$(CONFIG_ROCKCHIP_RGA2) += rga2/
obj-$(CONFIG_RK_HDMI) += display-sys.o hdmi/
+obj-$(CONFIG_IEP) += iep/
--- /dev/null
+menu "IEP"
+ depends on ARCH_ROCKCHIP
+
+config IEP
+ tristate "ROCKCHIP IEP driver"
+ default y
+ help
+ rockchip iep module.
+
+config IEP_MMU
+ tristate "ROCKCHIP IEP MMU driver"
+ depends on ARCH_ROCKCHIP
+ default n
+ help
+ rockchip iep mmu
+
+endmenu
--- /dev/null
+obj-$(CONFIG_IEP) += hw_iep_reg.o iep_drv.o
+obj-$(CONFIG_IEP_MMU) += iep_mmu.o
--- /dev/null
+#ifndef HW_IEP_CONFIG_ADDR_H_\r
+#define HW_IEP_CONFIG_ADDR_H_\r
+\r
+#include <asm/io.h>\r
+\r
+#define IEP_BASE 0x0 //ignore the IEP_BASE when program running in linux kernel //0x10108000\r
+\r
+#define IEP_CONFIG0 0x0000\r
+#define IEP_CONFIG1 0x0004\r
+\r
+#define IEP_STATUS 0x0008\r
+#define IEP_INT 0x000C\r
+#define IEP_FRM_START 0x0010\r
+#define IEP_SOFT_RST 0x0014\r
+#define IEP_CONF_DONE 0x0018\r
+\r
+#define IEP_VIR_IMG_WIDTH 0x0020\r
+\r
+#define IEP_IMG_SCL_FCT 0x0024\r
+\r
+#define IEP_SRC_IMG_SIZE 0x0028\r
+#define IEP_DST_IMG_SIZE 0x002C\r
+\r
+#define IEP_DST_IMG_WIDTH_TILE0 0x0030\r
+#define IEP_DST_IMG_WIDTH_TILE1 0x0034\r
+#define IEP_DST_IMG_WIDTH_TILE2 0x0038\r
+#define IEP_DST_IMG_WIDTH_TILE3 0x003C\r
+\r
+#define IEP_ENH_YUV_CNFG_0 0x0040\r
+#define IEP_ENH_YUV_CNFG_1 0x0044\r
+#define IEP_ENH_YUV_CNFG_2 0x0048\r
+#define IEP_ENH_RGB_CNFG 0x004C\r
+#define IEP_ENH_C_COE 0x0050\r
+\r
+#define IEP_SRC_ADDR_YRGB 0x0080\r
+#define IEP_SRC_ADDR_CBCR 0x0084\r
+#define IEP_SRC_ADDR_CR 0x0088\r
+#define IEP_SRC_ADDR_Y1 0x008C\r
+#define IEP_SRC_ADDR_CBCR1 0x0090\r
+#define IEP_SRC_ADDR_CR1 0x0094\r
+#define IEP_SRC_ADDR_Y_ITEMP 0x0098\r
+#define IEP_SRC_ADDR_CBCR_ITEMP 0x009C\r
+#define IEP_SRC_ADDR_CR_ITEMP 0x00A0\r
+#define IEP_SRC_ADDR_Y_FTEMP 0x00A4\r
+#define IEP_SRC_ADDR_CBCR_FTEMP 0x00A8\r
+#define IEP_SRC_ADDR_CR_FTEMP 0x00AC\r
+\r
+#define IEP_DST_ADDR_YRGB 0x00B0\r
+#define IEP_DST_ADDR_CBCR 0x00B4\r
+#define IEP_DST_ADDR_CR 0x00B8\r
+#define IEP_DST_ADDR_Y1 0x00BC\r
+#define IEP_DST_ADDR_CBCR1 0x00C0\r
+#define IEP_DST_ADDR_CR1 0x00C4\r
+#define IEP_DST_ADDR_Y_ITEMP 0x00C8\r
+#define IEP_DST_ADDR_CBCR_ITEMP 0x00CC\r
+#define IEP_DST_ADDR_CR_ITEMP 0x00D0\r
+#define IEP_DST_ADDR_Y_FTEMP 0x00D4\r
+#define IEP_DST_ADDR_CBCR_FTEMP 0x00D8\r
+#define IEP_DST_ADDR_CR_FTEMP 0x00DC\r
+\r
+#define IEP_DIL_MTN_TAB0 0x00E0\r
+#define IEP_DIL_MTN_TAB1 0x00E4\r
+#define IEP_DIL_MTN_TAB2 0x00E8\r
+#define IEP_DIL_MTN_TAB3 0x00EC\r
+#define IEP_DIL_MTN_TAB4 0x00F0\r
+#define IEP_DIL_MTN_TAB5 0x00F4\r
+#define IEP_DIL_MTN_TAB6 0x00F8\r
+#define IEP_DIL_MTN_TAB7 0x00FC\r
+\r
+#define IEP_ENH_CG_TAB 0x0100\r
+\r
+#define IEP_YUV_DNS_CRCT_TEMP 0x0400\r
+#define IEP_YUV_DNS_CRCT_SPAT 0x0800\r
+\r
+#define IEP_ENH_DDE_COE0 0x0C00\r
+#define IEP_ENH_DDE_COE1 0x0E00\r
+\r
+#define RAW_IEP_CONFIG0 0x0058\r
+#define RAW_IEP_CONFIG1 0x005C\r
+#define RAW_IEP_VIR_IMG_WIDTH 0x0060\r
+\r
+#define RAW_IEP_IMG_SCL_FCT 0x0064\r
+\r
+#define RAW_IEP_SRC_IMG_SIZE 0x0068\r
+#define RAW_IEP_DST_IMG_SIZE 0x006C\r
+\r
+#define RAW_IEP_ENH_YUV_CNFG_0 0x0070\r
+#define RAW_IEP_ENH_YUV_CNFG_1 0x0074\r
+#define RAW_IEP_ENH_YUV_CNFG_2 0x0078\r
+#define RAW_IEP_ENH_RGB_CNFG 0x007C\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+#define IEP_MMU_BASE 0x0800\r
+#define IEP_MMU_DTE_ADDR (IEP_MMU_BASE+0x00)\r
+#define IEP_MMU_STATUS (IEP_MMU_BASE+0x04)\r
+#define IEP_MMU_CMD (IEP_MMU_BASE+0x08)\r
+#define IEP_MMU_PAGE_FAULT_ADDR (IEP_MMU_BASE+0x0c)\r
+#define IEP_MMU_ZAP_ONE_LINE (IEP_MMU_BASE+0x10)\r
+#define IEP_MMU_INT_RAWSTAT (IEP_MMU_BASE+0x14)\r
+#define IEP_MMU_INT_CLEAR (IEP_MMU_BASE+0x18)\r
+#define IEP_MMU_INT_MASK (IEP_MMU_BASE+0x1c)\r
+#define IEP_MMU_INT_STATUS (IEP_MMU_BASE+0x20)\r
+#define IEP_MMU_AUTO_GATING (IEP_MMU_BASE+0x24)\r
+#endif\r
+\r
+#define ReadReg32(base, raddr) (__raw_readl(base + raddr))\r
+#define WriteReg32(base, waddr, value) (__raw_writel(value, base + waddr))\r
+#define ConfRegBits32(base, raddr, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))\r
+#define MaskRegBits32(base, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))\r
+\r
+#endif\r
--- /dev/null
+/* \r
+ * Copyright (C) 2013 ROCKCHIP, Inc.\r
+ *\r
+ * This software is licensed under the terms of the GNU General Public\r
+ * License version 2, as published by the Free Software Foundation, and\r
+ * may be copied, distributed, and modified under those terms.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ * \r
+ */\r
+\r
+#include <linux/delay.h>\r
+#include <linux/slab.h>\r
+#include "hw_iep_reg.h"\r
+#include "iep_api.h"\r
+#include "iep.h"\r
+#include "hw_iep_config_addr.h"\r
+\r
+static void iep_config_src_size(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_SRC_IMG_WIDTH(iep_msg->base, iep_msg->src.act_w - 1);\r
+ IEP_REGB_SRC_IMG_HEIGHT(iep_msg->base, iep_msg->src.act_h - 1);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG(" //==source image size config===================//\n\n");\r
+ IEP_DBG("sw_src_img_height = %d;//source image height \n", iep_msg->src.act_h - 1);\r
+ IEP_DBG("sw_src_img_width = %d;//source image width \n\n", iep_msg->src.act_w - 1);\r
+#endif\r
+}\r
+\r
+static void iep_config_dst_size(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_DST_IMG_WIDTH(iep_msg->base, iep_msg->dst.act_w - 1);\r
+ IEP_REGB_DST_IMG_HEIGHT(iep_msg->base, iep_msg->dst.act_h - 1);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG(" //==destination image size config===================//\n\n");\r
+ IEP_DBG("sw_dst_img_height = %d;//source image height \n", iep_msg->dst.act_h - 1);\r
+ IEP_DBG("sw_dst_img_width = %d;//source image width \n", iep_msg->dst.act_w - 1);\r
+#endif\r
+}\r
+\r
+static void iep_config_dst_width_tile(IEP_MSG *iep_msg)\r
+{\r
+// IEP_REGB_DST_IMG_WIDTH_TILE0();\r
+// IEP_REGB_DST_IMG_WIDTH_TILE1();\r
+// IEP_REGB_DST_IMG_WIDTH_TILE2();\r
+// IEP_REGB_DST_IMG_WIDTH_TILE3();\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("sw_dst_width_tile0 = 0;\n");\r
+ IEP_DBG("sw_dst_width_tile1 = 0;\n");\r
+ IEP_DBG("sw_dst_width_tile2 = 0;\n");\r
+ IEP_DBG("sw_dst_width_tile3 = 0;\n\n");\r
+#endif\r
+}\r
+\r
+static void iep_config_dst_fmt(IEP_MSG *iep_msg)\r
+{\r
+ unsigned int dst_fmt = 0;\r
+ unsigned int dst_rgb_swap = 0;\r
+ unsigned int dst_yuv_swap = 0;\r
+ switch (iep_msg->dst.format) {\r
+ case IEP_FORMAT_ARGB_8888 :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 0);\r
+ IEP_REGB_DST_RGB_SWAP(iep_msg->base, 0);\r
+ dst_fmt = 0;\r
+ dst_rgb_swap = 0;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_ABGR_8888 :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 0);\r
+ IEP_REGB_DST_RGB_SWAP(iep_msg->base, 1);\r
+ dst_fmt = 0;\r
+ dst_rgb_swap = 1;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_RGBA_8888 :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 0);\r
+ IEP_REGB_DST_RGB_SWAP(iep_msg->base, 2);\r
+ dst_fmt = 0;\r
+ dst_rgb_swap = 2;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_BGRA_8888 :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 0);\r
+ IEP_REGB_DST_RGB_SWAP(iep_msg->base, 3);\r
+ dst_fmt = 0;\r
+ dst_rgb_swap = 3;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_RGB_565 :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 1);\r
+ IEP_REGB_DST_RGB_SWAP(iep_msg->base, 0);\r
+ dst_fmt = 1;\r
+ dst_rgb_swap = 0;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_BGR_565 :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 1);\r
+ IEP_REGB_DST_RGB_SWAP(iep_msg->base, 1);\r
+ dst_fmt = 1;\r
+ dst_rgb_swap = 1;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_SP :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 2);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 0);\r
+ dst_fmt = 2;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_P :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 2);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 2);\r
+ dst_fmt = 2;\r
+ dst_yuv_swap = 2;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_SP :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 3);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 0);\r
+ dst_fmt = 3;\r
+ dst_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_P :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 3);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 2);\r
+ dst_fmt = 3;\r
+ dst_yuv_swap = 2;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_SP :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 2);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 1);\r
+ dst_fmt = 2;\r
+ dst_yuv_swap = 1;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_P :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 2);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 2);\r
+ dst_fmt = 2;\r
+ dst_yuv_swap = 2;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_SP :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 3);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 1);\r
+ dst_fmt = 3;\r
+ dst_yuv_swap = 1;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_P :\r
+ IEP_REGB_DST_FMT(iep_msg->base, 3);\r
+ IEP_REGB_DST_YUV_SWAP(iep_msg->base, 2);\r
+ dst_fmt = 3;\r
+ dst_yuv_swap = 2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG(" //==destination data format config============//\n\n");\r
+ IEP_DBG("sw_dst_yuv_swap = %d;//0:sp uv; 1:sp vu; 2:p ; 3:p;\n", dst_yuv_swap);\r
+ IEP_DBG("sw_dst_rgb_swap = %d;//if ARGB 0:argb; 1,abgr; 2:rgba; 3:bgra; if rgb565: 0,2:rgb; 1,3:bgr;\n", dst_rgb_swap);\r
+ IEP_DBG("sw_dst_fmt = %d;//0:argb; 1:rgb565; 2:yuv422; 3:yuv420;\n\n", dst_fmt);\r
+#endif\r
+}\r
+\r
+static void iep_config_src_fmt(IEP_MSG *iep_msg)\r
+{\r
+ unsigned int src_fmt = 0;\r
+ unsigned int src_rgb_swap = 0;\r
+ unsigned int src_yuv_swap = 0;\r
+ switch (iep_msg->src.format) {\r
+ case IEP_FORMAT_ARGB_8888 :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 0);\r
+ IEP_REGB_SRC_RGB_SWAP(iep_msg->base, 0);\r
+ src_fmt = 0;\r
+ src_rgb_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_ABGR_8888 :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 0);\r
+ IEP_REGB_SRC_RGB_SWAP(iep_msg->base, 1);\r
+ src_fmt = 0;\r
+ src_rgb_swap = 1;\r
+ break;\r
+ case IEP_FORMAT_RGBA_8888 :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 0);\r
+ IEP_REGB_SRC_RGB_SWAP(iep_msg->base, 2);\r
+ src_fmt = 0;\r
+ src_rgb_swap = 2;\r
+ break;\r
+ case IEP_FORMAT_BGRA_8888 :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 0);\r
+ IEP_REGB_SRC_RGB_SWAP(iep_msg->base, 3);\r
+ src_fmt = 0;\r
+ src_rgb_swap = 3;\r
+ break;\r
+ case IEP_FORMAT_RGB_565 :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 1);\r
+ IEP_REGB_SRC_RGB_SWAP(iep_msg->base, 0);\r
+ src_fmt = 1;\r
+ src_rgb_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_BGR_565 :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 1);\r
+ IEP_REGB_SRC_RGB_SWAP(iep_msg->base, 1);\r
+ src_fmt = 1;\r
+ src_rgb_swap = 1;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_SP :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 2);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 0);\r
+ src_fmt = 2;\r
+ src_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_P :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 2);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 2);\r
+ src_fmt = 2;\r
+ src_yuv_swap = 2;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_SP :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 3);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 0);\r
+ src_fmt = 3;\r
+ src_yuv_swap = 0;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_P :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 3);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 2);\r
+ src_fmt = 3;\r
+ src_yuv_swap = 2;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_SP :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 2);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 1);\r
+ src_fmt = 2;\r
+ src_yuv_swap = 1;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_P :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 2);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 2);\r
+ src_fmt = 2;\r
+ src_yuv_swap = 2;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_SP :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 3);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 1);\r
+ src_fmt = 3;\r
+ src_yuv_swap = 1;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_P :\r
+ IEP_REGB_SRC_FMT(iep_msg->base, 3);\r
+ IEP_REGB_SRC_YUV_SWAP(iep_msg->base, 2);\r
+ src_fmt = 3;\r
+ src_yuv_swap = 2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG(" //==source data format config=================//\n\n");\r
+ IEP_DBG("sw_src_yuv_swap = %d;//0:sp uv; 1:sp vu; 2:p ; 3:p;\n", src_yuv_swap);\r
+ IEP_DBG("sw_src_rgb_swap = %d;//if ARGB 0:argb; 1,abgr; 2:rgba; 3:bgra; if rgb565: 0,2:rgb; 1,3:bgr;\n", src_rgb_swap);\r
+ IEP_DBG("sw_src_fmt = %d;//0:argb; 1:rgb565; 2:yuv422; 3:yuv420;\n\n", src_fmt);\r
+#endif\r
+}\r
+\r
+static void iep_config_scl(IEP_MSG *iep_msg)\r
+{\r
+ int scl_en;\r
+ int scl_sel;\r
+ //int vrt_fct;\r
+ //int hrz_fct;\r
+\r
+ unsigned int src_height, src_width, dst_height, dst_width;\r
+\r
+ int div_height_dst_src;\r
+ int div_width_dst_src;\r
+\r
+ src_height = iep_msg->src.act_h - 1;\r
+ src_width = iep_msg->src.act_w - 1;\r
+ dst_height = iep_msg->dst.act_h - 1;\r
+ dst_width = iep_msg->dst.act_w - 1;\r
+\r
+ if ((iep_msg->src.act_w == iep_msg->dst.act_w) && (iep_msg->src.act_h == iep_msg->dst.act_h)) scl_en = 0;\r
+ else scl_en = 1;\r
+\r
+ if ((iep_msg->src.act_w >= iep_msg->dst.act_w) && (iep_msg->src.act_h >= iep_msg->dst.act_h)) scl_sel = 0;\r
+ else if ((iep_msg->src.act_w >= iep_msg->dst.act_w) && (iep_msg->src.act_h <= iep_msg->dst.act_h)) scl_sel = 1;\r
+ else if ((iep_msg->src.act_w <= iep_msg->dst.act_w) && (iep_msg->src.act_h >= iep_msg->dst.act_h)) scl_sel = 2;\r
+ else scl_sel = 3;\r
+\r
+ //for vrt_fct\r
+ if ((scl_sel == 1) || (scl_sel == 3)) {\r
+ div_height_dst_src = src_height * 65536 / dst_height;\r
+ } else {\r
+ div_height_dst_src = (dst_height + 1) * 65536 / (src_height + 1);\r
+ if ((div_height_dst_src * (src_height + 1)) < ((dst_height + 1) * 65536)) div_height_dst_src = div_height_dst_src + 1;\r
+ }\r
+\r
+ if (div_height_dst_src == 65536) div_height_dst_src = 0;\r
+\r
+ //for hrz_fct\r
+ if ((scl_sel == 2) || (scl_sel == 3)) {\r
+ div_width_dst_src = src_width * 65536 / dst_width;\r
+ } else {\r
+ div_width_dst_src = (dst_width + 1) * 65536 / (src_width + 1);\r
+ if ((div_width_dst_src * (src_width + 1)) < ((dst_width + 1) * 65536)) div_width_dst_src = div_width_dst_src + 1;\r
+ }\r
+\r
+ if (div_width_dst_src == 65536) div_width_dst_src = 0;\r
+\r
+\r
+ IEP_REGB_SCL_EN(iep_msg->base, scl_en);\r
+\r
+ if (scl_en == 1) {\r
+ IEP_REGB_SCL_SEL(iep_msg->base, scl_sel);\r
+ IEP_REGB_SCL_UP_COE_SEL(iep_msg->base, iep_msg->scale_up_mode);\r
+ IEP_REGB_SCL_VRT_FCT(iep_msg->base, div_height_dst_src);\r
+ IEP_REGB_SCL_HRZ_FCT(iep_msg->base, div_width_dst_src);\r
+ }\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG(" //==scaling config============================//\n\n");\r
+ IEP_DBG("sw_scl_en = %d;//0:disable; 1:enable;\n", scl_en);\r
+ IEP_DBG("sw_scl_sel = %d;//0:hrz down & vrt down; 1:hrz down & vrt up; 2:hrz up & vrt down; 3:hrz up & vrt up;\n", scl_sel);\r
+ IEP_DBG("sw_scl_up_coe_sel = %d;//select four groups of up scaling coefficient\n", iep_msg->scale_up_mode);\r
+ IEP_DBG("sw_scl_vrt_fct = %d;//if up-scaling,equal to floor(src_img_height/dst_image_height)*2^16; if down-scaling,equal to ceiling(dst_image_height/src_image_height)*2^16;\n", div_height_dst_src);\r
+ IEP_DBG("sw_scl_hrz_fct = %d;//if up-scaling,equal to floor(src_img_widht/dst_image_width)*2^16; if down-scaling,equal to ceiling(dst_image_width/src_image_width)*2^16 ; \n\n", div_width_dst_src);\r
+#endif\r
+}\r
+\r
+static void iep_config_cg_order(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_CON_GAM_ORDER(iep_msg->base, iep_msg->rgb_contrast_enhance_mode);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG(" //==rgb enhancement & denoise config==========//\n\n");\r
+ IEP_DBG("sw_con_gam_order = %d;//0:CG(contrast/gamma operation)prior to DDE(de-noise/detail/edge enhance); 1:DDE prior to CG;\n", iep_msg->rgb_contrast_enhance_mode);\r
+#endif\r
+}\r
+\r
+static void iep_config_cg(IEP_MSG *iep_msg)\r
+{\r
+ unsigned i;\r
+ unsigned int cg_conf_addr;\r
+\r
+ IEP_REGB_RGB_CON_GAM_EN(iep_msg->base, iep_msg->rgb_cg_en);\r
+\r
+ if (iep_msg->rgb_cg_en) {\r
+ cg_conf_addr = rIEP_CG_TAB_ADDR;\r
+\r
+ for (i=0; i<192; i++) {\r
+ WriteReg32(iep_msg->base, cg_conf_addr, iep_msg->cg_tab[i]);\r
+ cg_conf_addr += 0x04;\r
+ }\r
+ }\r
+\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("sw_rgb_con_gam_en = 0;//0:contrast & gamma disable; 1:enable;\n", iep_msg->rgb_cg_en);\r
+#endif\r
+}\r
+\r
+static void iep_config_dde(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_RGB_ENH_SEL(iep_msg->base, iep_msg->rgb_enhance_mode);\r
+ IEP_REGB_ENH_THRESHOLD(iep_msg->base, iep_msg->enh_threshold);\r
+ IEP_REGB_ENH_ALPHA(iep_msg->base, iep_msg->enh_alpha);\r
+ IEP_REGB_ENH_RADIUS(iep_msg->base, iep_msg->enh_radius);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("sw_rgb_enh_sel = %d;//0:no operation; 1:de-noise; 2:detail enhance; 3:edge enhance;\n", iep_msg->rgb_enhance_mode);\r
+#endif\r
+\r
+}\r
+\r
+static void iep_config_color_enh(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_RGB_COLOR_ENH_EN(iep_msg->base, iep_msg->rgb_color_enhance_en);\r
+ IEP_REGB_ENH_C_COE(iep_msg->base, iep_msg->rgb_enh_coe);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("sw_rgb_color_enh_en = %d;//0:color enhance disable; 1:enable;\n\n", iep_msg->rgb_color_enhance_en);\r
+#endif\r
+}\r
+\r
+static void iep_config_yuv_dns(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_YUV_DNS_EN(iep_msg->base, iep_msg->yuv_3D_denoise_en);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//==yuv denoise config========================// \n\n");\r
+ IEP_DBG("sw_yuv_dns_en = %d;//0:yuv 3d denoise disable; 1:enable\n\n", iep_msg->yuv_3D_denoise_en);\r
+#endif\r
+}\r
+\r
+\r
+static void iep_config_dil(IEP_MSG *iep_msg)\r
+{\r
+ //unsigned int value_tab0, value_tab1, value_tab2, value_tab3, value_tab4, value_tab5, value_tab6, value_tab7;\r
+ int dein_mode;\r
+ //double tab[256] =\r
+ //{\r
+ // 1.0,1.0,1.0,1.0,\r
+ // 1.000000,0.996856,0.987464,0.971942,\r
+ // 0.950484,0.923362,0.890916,0.853553,\r
+ // 0.811745,0.766016,0.716942,0.665140,\r
+ // 0.611260,0.555982,0.500000,0.444018,\r
+ // 0.388740,0.334860,0.283058,0.233984,\r
+ // 0.188255,0.146447,0.109084,0.076638,\r
+ // 0.049516,0.028058,0.012536,0.003144\r
+ //};\r
+ switch (iep_msg->dein_mode) {\r
+ case IEP_DEINTERLACE_MODE_DISABLE:\r
+ dein_mode = dein_mode_bypass_dis;\r
+ break;\r
+ case IEP_DEINTERLACE_MODE_I2O1:\r
+ dein_mode = iep_msg->field_order == FIELD_ORDER_TOP_FIRST ? dein_mode_I2O1T : dein_mode_I2O1B;\r
+ break;\r
+ case IEP_DEINTERLACE_MODE_I4O1:\r
+#if 1\r
+ dein_mode = iep_msg->field_order == FIELD_ORDER_TOP_FIRST ? dein_mode_I4O1B : dein_mode_I4O1T;\r
+#else\r
+ dein_mode = iep_msg->field_order == FIELD_ORDER_TOP_FIRST ? dein_mode_I4O1T : dein_mode_I4O1B;\r
+#endif\r
+ break;\r
+ case IEP_DEINTERLACE_MODE_I4O2:\r
+ dein_mode = dein_mode_I4O2;\r
+ break;\r
+ case IEP_DEINTERLACE_MODE_BYPASS:\r
+ dein_mode = dein_mode_bypass;\r
+ break;\r
+ default:\r
+ IEP_ERR("unknown deinterlace mode, set deinterlace mode (bypass)\n");\r
+ dein_mode = dein_mode_bypass;\r
+ }\r
+\r
+ IEP_REGB_DIL_MODE(iep_msg->base, dein_mode);\r
+ //hf\r
+ IEP_REGB_DIL_HF_EN(iep_msg->base, iep_msg->dein_high_fre_en);\r
+ if (iep_msg->dein_high_fre_en == 1) IEP_REGB_DIL_HF_FCT(iep_msg->base, iep_msg->dein_high_fre_fct);\r
+ //ei\r
+ IEP_REGB_DIL_EI_MODE(iep_msg->base, iep_msg->dein_ei_mode);\r
+ IEP_REGB_DIL_EI_SMOOTH(iep_msg->base, iep_msg->dein_ei_smooth);\r
+ IEP_REGB_DIL_EI_SEL(iep_msg->base, iep_msg->dein_ei_sel);\r
+ if (iep_msg->dein_ei_sel == 0) IEP_REGB_DIL_EI_RADIUS(iep_msg->base, iep_msg->dein_ei_radius);\r
+\r
+ /*\r
+ value_tab0=(64<<24)+(64<<16)+(64<<8)+64;\r
+ IEP_REGB_DIL_MTN_TAB0(value_tab0);\r
+ \r
+ value_tab1=(62<<24)+(63<<16)+(63<<8)+64;\r
+ IEP_REGB_DIL_MTN_TAB1(value_tab1);\r
+ \r
+ value_tab2=(54<<24)+(57<<16)+(59<<8)+60;\r
+ IEP_REGB_DIL_MTN_TAB2(value_tab2);\r
+ \r
+ value_tab3=(42<<24)+(45<<16)+(49<<8)+51;\r
+ IEP_REGB_DIL_MTN_TAB3(value_tab3);\r
+ \r
+ value_tab4=(28<<24)+(32<<16)+(35<<8)+39;\r
+ IEP_REGB_DIL_MTN_TAB4(value_tab4);\r
+ \r
+ value_tab5=(14<<24)+(18<<16)+(21<<8)+24;\r
+ IEP_REGB_DIL_MTN_TAB5(value_tab5);\r
+ \r
+ value_tab6=(4<<24)+(6<<16)+(9<<8)+12;\r
+ IEP_REGB_DIL_MTN_TAB6(value_tab6);\r
+ \r
+ value_tab6=(1<<8)+3;\r
+ IEP_REGB_DIL_MTN_TAB7(value_tab6); \r
+ */\r
+ IEP_REGB_DIL_MTN_TAB0(iep_msg->base, 0x40404040);\r
+ IEP_REGB_DIL_MTN_TAB1(iep_msg->base, 0x3c3e3f3f);\r
+ IEP_REGB_DIL_MTN_TAB2(iep_msg->base, 0x3336393b);\r
+ IEP_REGB_DIL_MTN_TAB3(iep_msg->base, 0x272a2d31);\r
+ IEP_REGB_DIL_MTN_TAB4(iep_msg->base, 0x181c2023);\r
+ IEP_REGB_DIL_MTN_TAB5(iep_msg->base, 0x0c0e1215);\r
+ IEP_REGB_DIL_MTN_TAB6(iep_msg->base, 0x03040609);\r
+ IEP_REGB_DIL_MTN_TAB7(iep_msg->base, 0x00000001);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG(" //==deinterlace config========================//\n\n");\r
+ IEP_DBG("sw_dil_hf_en = %d;//0:disable high-frequency deinterlace; 1:enahble\n", iep_msg->dein_high_fre_en);\r
+ IEP_DBG("sw_dil_mode = %d;//0:deinterlace disable; 1:I4O2; 2:I4O1B; 3:I4O1T; 4:I201B; 5:I201T 6:bypass\n", iep_msg->dein_mode);\r
+ IEP_DBG("sw_dil_ei_mode = %d;//edge interpolation\n", iep_msg->dein_ei_mode);\r
+ IEP_DBG("sw_dil_mtn_tab0 = 63,64,64,64;//motion table 0~ 3,7bit\n");\r
+ IEP_DBG("sw_dil_mtn_tab1 = 52,57,60,62;//motion table 0~ 3,7bit\n");\r
+ IEP_DBG("sw_dil_mtn_tab2 = 0,0,0,0,46;//motion table 0~ 3,7bit\n");\r
+ IEP_DBG("sw_dil_mtn_tab3 = 0;//motion table 0~ 3,7bit\n");\r
+ IEP_DBG("sw_dil_mtn_tab4 = 0;//motion table 0~ 3,7bit\n");\r
+ IEP_DBG("sw_dil_mtn_tab5 = 0;//motion table 0~ 3,7bit\n");\r
+ IEP_DBG("sw_dil_mtn_tab6 = 0;//motion table 0~ 3,7bit\n");\r
+ IEP_DBG("sw_dil_mtn_tab7 = 0;//motion table 0~ 3,7bit\n\n");\r
+#endif\r
+}\r
+\r
+static void iep_config_yuv_enh(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_YUV_ENH_EN(iep_msg->base, iep_msg->yuv_enhance_en);\r
+ if (iep_msg->yuv_enhance_en == 1) {\r
+ IEP_REGB_VIDEO_MODE(iep_msg->base, iep_msg->video_mode);\r
+ if (iep_msg->video_mode == normal_mode) {\r
+ IEP_REGB_SAT_CON(iep_msg->base, iep_msg->sat_con_int);\r
+ IEP_REGB_CONTRAST(iep_msg->base, iep_msg->contrast_int);\r
+ IEP_REGB_BRIGHTNESS(iep_msg->base, iep_msg->yuv_enh_brightness);\r
+ IEP_REGB_COS_HUE(iep_msg->base, iep_msg->cos_hue_int);\r
+ IEP_REGB_SIN_HUE(iep_msg->base, iep_msg->sin_hue_int);\r
+ } else if (iep_msg->video_mode == color_bar) { //color bar\r
+ IEP_REGB_COLOR_BAR_Y(iep_msg->base, iep_msg->color_bar_y);\r
+ IEP_REGB_COLOR_BAR_U(iep_msg->base, iep_msg->color_bar_u);\r
+ IEP_REGB_COLOR_BAR_V(iep_msg->base, iep_msg->color_bar_v);\r
+ }\r
+\r
+ }\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//==yuv contrast,saturation,hue,bright cofing==//\n\n");\r
+ IEP_DBG("sw_yuv_enh_en = %d;//yuv enhance enable\n", iep_msg->yuv_enhance_en);\r
+ IEP_DBG("sw_sat_con = %d;//saturation*contrast*128 (0<saturation<1.992,0<contrast<1.992)\n", iep_msg->sat_con_int);\r
+ IEP_DBG("sw_contrast = %d;//contrast*128 (0<contrast<1.992)\n", iep_msg->contrast_int);\r
+ IEP_DBG("sw_brightness = %d;//brightness (-32<brightness<31)\n", iep_msg->yuv_enh_brightness);\r
+ IEP_DBG("sw_cos_hue = %d;//cos(hue) (0<hue<30,triangle)\n", iep_msg->cos_hue_int);\r
+ IEP_DBG("sw_sin_hue = %d;//sin(hue) (0<hue<30,triangle)\n", iep_msg->sin_hue_int);\r
+ IEP_DBG("sw_color_bar_y = %d;\n", iep_msg->color_bar_y);\r
+ IEP_DBG("sw_color_bar_u = %d;\n", iep_msg->color_bar_u);\r
+ IEP_DBG("sw_color_bar_v = %d;\n", iep_msg->color_bar_v);\r
+ IEP_DBG("sw_video_mode = %d;\n\n", iep_msg->video_mode);\r
+#endif\r
+\r
+}\r
+\r
+static void iep_config_rgb2yuv(IEP_MSG *iep_msg)\r
+{\r
+ unsigned char cond1, cond2;\r
+ unsigned int rgb2yuv_en = 0;\r
+\r
+ //rgb in,yuv out\r
+ cond1 = ((iep_msg->src.format <= 5) && (iep_msg->dst.format > 5)) ? 1 : 0;\r
+\r
+ //rgb process,yuv out\r
+ cond2 = (((iep_msg->rgb_color_enhance_en == 1) || (iep_msg->rgb_cg_en == 1) \r
+ || (iep_msg->rgb_enhance_mode != rgb_enhance_bypass)) && (iep_msg->dst.format > 5)) ? 1 : 0;\r
+\r
+\r
+ if ((cond1 == 1) || (cond2 == 1)) {\r
+ IEP_REGB_RGB_TO_YUV_EN(iep_msg->base, 1);\r
+ rgb2yuv_en = 1;\r
+ IEP_REGB_RGB2YUV_COE_SEL(iep_msg->base, iep_msg->rgb2yuv_mode);\r
+ IEP_REGB_RGB2YUV_INPUT_CLIP(iep_msg->base, iep_msg->rgb2yuv_clip_en);\r
+ } else IEP_REGB_RGB_TO_YUV_EN(iep_msg->base, 0);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//==color space conversion config============//\n\n");\r
+ IEP_DBG("sw_rgb_to_yuv_en = %d;\n", rgb2yuv_en);\r
+ IEP_DBG("sw_rgb2yuv_coe_sel = %d;\n", iep_msg->rgb2yuv_mode);\r
+ IEP_DBG("sw_rgb2yuv_input_clip = %d;\n\n", iep_msg->rgb2yuv_clip_en);\r
+#endif\r
+\r
+}\r
+\r
+static void iep_config_yuv2rgb(IEP_MSG *iep_msg)\r
+{\r
+ unsigned char cond1, cond2;\r
+ unsigned int yuv2rgb_en = 0;\r
+\r
+ //yuv in,rgb out\r
+ cond1 = ((iep_msg->src.format > 5) && (iep_msg->dst.format <= 5)) ? 1 : 0;\r
+\r
+ //yuv in,rgb process\r
+ cond2 = (((iep_msg->rgb_color_enhance_en == 1) || (iep_msg->rgb_cg_en == 1) \r
+ || (iep_msg->rgb_enhance_mode != rgb_enhance_bypass)) && (iep_msg->src.format > 5)) ? 1 : 0;\r
+\r
+ if ((cond1 == 1) || (cond2 == 1)) {\r
+ IEP_REGB_YUV_TO_RGB_EN(iep_msg->base, 1);\r
+ yuv2rgb_en = 1;\r
+ IEP_REGB_YUV2RGB_COE_SEL(iep_msg->base, iep_msg->yuv2rgb_mode);\r
+ IEP_REGB_YUV2RGB_INPUT_CLIP(iep_msg->base, iep_msg->yuv2rgb_clip_en);\r
+ } else IEP_REGB_YUV_TO_RGB_EN(iep_msg->base, 0);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("sw_yuv_to_rgb_en = %d;\n", yuv2rgb_en);\r
+ IEP_DBG("sw_yuv2rgb_coe_sel = %d;\n", iep_msg->yuv2rgb_mode);\r
+ IEP_DBG("sw_yuv2rgb_input_clip = %d;\n\n", iep_msg->yuv2rgb_clip_en);\r
+#endif\r
+}\r
+\r
+static void iep_config_dither_up(IEP_MSG *iep_msg)\r
+{\r
+ unsigned int dither_up = 0;\r
+ if ((iep_msg->src.format == IEP_FORMAT_RGB_565) || (iep_msg->src.format == IEP_FORMAT_BGR_565)) {\r
+ IEP_REGB_DITHER_UP_EN(iep_msg->base, iep_msg->dither_up_en);\r
+ dither_up = iep_msg->dither_up_en;\r
+ } else IEP_REGB_DITHER_UP_EN(iep_msg->base, 0);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//==dither config=============================//\n\n");\r
+ IEP_DBG("sw_dither_up_en = %d;\n", dither_up);\r
+#endif\r
+}\r
+\r
+static void iep_config_dither_down(IEP_MSG *iep_msg)\r
+{\r
+ unsigned int dither_down = 0;\r
+ if ((iep_msg->dst.format == IEP_FORMAT_RGB_565) || (iep_msg->dst.format == IEP_FORMAT_BGR_565)) {\r
+ IEP_REGB_DITHER_DOWN_EN(iep_msg->base, 1);\r
+ dither_down = 1;\r
+ } else IEP_REGB_DITHER_DOWN_EN(iep_msg->base, 0);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("sw_dither_down_en = %d;\n\n", dither_down);\r
+#endif\r
+}\r
+\r
+static void iep_config_glb_alpha(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_GLB_ALPHA(iep_msg->base, iep_msg->global_alpha_value);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//==global alpha for ARGB config=============//\n\n");\r
+ IEP_DBG("sw_glb_alpha = %d;//global alpha value for output ARGB\n\n", iep_msg->global_alpha_value);\r
+#endif\r
+}\r
+\r
+static void iep_config_vir_line(IEP_MSG *iep_msg)\r
+{\r
+ unsigned int src_vir_w;\r
+ unsigned int dst_vir_w;\r
+\r
+ switch (iep_msg->src.format) {\r
+ case IEP_FORMAT_ARGB_8888 :\r
+ src_vir_w = iep_msg->src.vir_w;\r
+ break;\r
+ case IEP_FORMAT_ABGR_8888 :\r
+ src_vir_w = iep_msg->src.vir_w;\r
+ break;\r
+ case IEP_FORMAT_RGBA_8888 :\r
+ src_vir_w = iep_msg->src.vir_w;\r
+ break;\r
+ case IEP_FORMAT_BGRA_8888 :\r
+ src_vir_w = iep_msg->src.vir_w;\r
+ break;\r
+ case IEP_FORMAT_RGB_565 :\r
+ if (iep_msg->src.vir_w % 2 == 1) src_vir_w = (iep_msg->src.vir_w + 1) / 2;\r
+ else src_vir_w = iep_msg->src.vir_w / 2;\r
+ break;\r
+ case IEP_FORMAT_BGR_565 :\r
+ if (iep_msg->src.vir_w % 2 == 1) src_vir_w = iep_msg->src.vir_w / 2 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 2;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_SP :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_P :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_SP :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_P :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_SP :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_P :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_SP :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_P :\r
+ if (iep_msg->src.vir_w % 4 != 0) src_vir_w = iep_msg->src.vir_w / 4 + 1;\r
+ else src_vir_w = iep_msg->src.vir_w / 4;\r
+ break;\r
+ default:\r
+ IEP_ERR("Unkown format, set the source image virtual width 0\n");\r
+ src_vir_w = 0;\r
+ break;\r
+ }\r
+\r
+ switch (iep_msg->dst.format) {\r
+ case IEP_FORMAT_ARGB_8888 :\r
+ dst_vir_w = iep_msg->dst.vir_w;\r
+ break;\r
+ case IEP_FORMAT_ABGR_8888 :\r
+ dst_vir_w = iep_msg->dst.vir_w;\r
+ break;\r
+ case IEP_FORMAT_RGBA_8888 :\r
+ dst_vir_w = iep_msg->dst.vir_w;\r
+ break;\r
+ case IEP_FORMAT_BGRA_8888 :\r
+ dst_vir_w = iep_msg->dst.vir_w;\r
+ break;\r
+ case IEP_FORMAT_RGB_565 :\r
+ if (iep_msg->dst.vir_w % 2 == 1) dst_vir_w = (iep_msg->dst.vir_w + 1) / 2;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 2;\r
+ break;\r
+ case IEP_FORMAT_BGR_565 :\r
+ if (iep_msg->dst.vir_w % 2 == 1) dst_vir_w = iep_msg->dst.vir_w / 2 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 2;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_SP :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_P :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_SP :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_P :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_SP :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_P :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_SP :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_P :\r
+ if (iep_msg->dst.vir_w % 4 != 0) dst_vir_w = iep_msg->dst.vir_w / 4 + 1;\r
+ else dst_vir_w = iep_msg->dst.vir_w / 4;\r
+ break;\r
+ default:\r
+ IEP_ERR("Unkown format, set the destination image virtual width 0\n");\r
+ dst_vir_w = 0;\r
+ break;\r
+ }\r
+ IEP_REGB_DST_VIR_LINE_WIDTH(iep_msg->base, dst_vir_w);\r
+ IEP_REGB_SRC_VIR_LINE_WIDTH(iep_msg->base, src_vir_w);\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("/==virtual line width config==================//\n\n");\r
+ IEP_DBG("sw_dst_vir_line_width = %d;//destination virtual line width \n", dst_vir_w);\r
+ IEP_DBG("sw_src_vir_line_width = %d;//source virtual line width \n\n", src_vir_w);\r
+#endif\r
+}\r
+\r
+static void iep_config_src_addr(IEP_MSG *iep_msg)\r
+{\r
+ u32 src_addr_yrgb;\r
+ u32 src_addr_cbcr;\r
+ u32 src_addr_cr;\r
+ u32 src_addr_y1;\r
+ u32 src_addr_cbcr1;\r
+ u32 src_addr_cr1;\r
+ u32 src_addr_y_itemp;\r
+ u32 src_addr_cbcr_itemp;\r
+ u32 src_addr_cr_itemp;\r
+ u32 src_addr_y_ftemp;\r
+ u32 src_addr_cbcr_ftemp;\r
+ u32 src_addr_cr_ftemp;\r
+ unsigned int offset_addr_y = 0;\r
+ unsigned int offset_addr_uv = 0;\r
+ unsigned int offset_addr_v = 0;\r
+ //unsigned int offset_addr_y_w = 0;\r
+ unsigned int offset_addr_uv_w = 0;\r
+ unsigned int offset_addr_v_w = 0;\r
+ //unsigned int offset_addr_y_h = 0;\r
+ unsigned int offset_addr_uv_h = 0;\r
+ unsigned int offset_addr_v_h = 0;\r
+\r
+ unsigned int offset_x_equ_uv;\r
+ unsigned int offset_x_u_byte;\r
+ unsigned int offset_x_v_byte;\r
+ unsigned int vir_w_euq_uv;\r
+ unsigned int line_u_byte;\r
+ unsigned int line_v_byte;\r
+ unsigned int offset_y_equ_420_uv = 0;\r
+\r
+ //**********************************************//\r
+ //***********y addr offset**********************//\r
+ //**********************************************//\r
+ if (iep_msg->src.format <= 3) {\r
+ offset_addr_y = iep_msg->src.y_off * 4 * iep_msg->src.vir_w + iep_msg->src.x_off * 4;\r
+ } else if (iep_msg->src.format <= 5) {\r
+ offset_addr_y = iep_msg->src.y_off * 2 * iep_msg->src.vir_w + iep_msg->src.x_off * 2;\r
+ } else {\r
+ offset_addr_y = iep_msg->src.y_off * iep_msg->src.vir_w + iep_msg->src.x_off;\r
+ }\r
+\r
+ //**********************************************//\r
+ //***********uv addr offset*********************//\r
+ //**********************************************//\r
+ // note: image size align to even when image format is yuv\r
+\r
+ //----------offset_w--------//\r
+ if (iep_msg->src.x_off % 2 == 1) offset_x_equ_uv = iep_msg->src.x_off + 1;\r
+ else offset_x_equ_uv = iep_msg->src.x_off;\r
+\r
+ offset_x_u_byte = offset_x_equ_uv / 2;\r
+ offset_x_v_byte = offset_x_equ_uv / 2;\r
+\r
+ if ((iep_msg->src.format == IEP_FORMAT_YCbCr_422_SP) || (iep_msg->src.format == IEP_FORMAT_YCbCr_420_SP) \r
+ || (iep_msg->src.format == IEP_FORMAT_YCrCb_422_SP) || (iep_msg->src.format == IEP_FORMAT_YCrCb_420_SP)) offset_addr_uv_w = offset_x_u_byte + offset_x_v_byte;\r
+ else {\r
+ offset_addr_uv_w = offset_x_u_byte;\r
+ offset_addr_v_w = offset_x_v_byte;\r
+ }\r
+\r
+ //----------offset_h--------//\r
+ if (iep_msg->src.vir_w % 2 == 1) vir_w_euq_uv = iep_msg->src.vir_w + 1;\r
+ else vir_w_euq_uv = iep_msg->src.vir_w;\r
+\r
+ line_u_byte = vir_w_euq_uv / 2;\r
+ line_v_byte = vir_w_euq_uv / 2;\r
+\r
+ if (iep_msg->src.y_off % 2 == 1) offset_y_equ_420_uv = iep_msg->src.y_off + 1;\r
+ else offset_y_equ_420_uv = iep_msg->src.y_off;\r
+\r
+ switch (iep_msg->src.format) {\r
+ case IEP_FORMAT_YCbCr_422_SP :\r
+ offset_addr_uv_h = (line_u_byte + line_v_byte) * iep_msg->src.y_off;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_P :\r
+ offset_addr_uv_h = line_u_byte * iep_msg->src.y_off;\r
+ offset_addr_v_h = line_v_byte * iep_msg->src.y_off;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_SP :\r
+ offset_addr_uv_h = (line_u_byte + line_v_byte) * offset_y_equ_420_uv / 2;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_P :\r
+ offset_addr_uv_h = line_u_byte * offset_y_equ_420_uv / 2;\r
+ offset_addr_v_h = line_v_byte * offset_y_equ_420_uv / 2;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_SP :\r
+ offset_addr_uv_h = (line_u_byte + line_v_byte) * iep_msg->src.y_off;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_422_P :\r
+ offset_addr_uv_h = line_u_byte * iep_msg->src.y_off;\r
+ offset_addr_v_h = line_v_byte * iep_msg->src.y_off;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_SP :\r
+ offset_addr_uv_h = (line_u_byte + line_v_byte) * offset_y_equ_420_uv / 2;\r
+ break;\r
+ case IEP_FORMAT_YCrCb_420_P :\r
+ offset_addr_uv_h = line_u_byte * offset_y_equ_420_uv / 2;\r
+ offset_addr_v_h = line_v_byte * offset_y_equ_420_uv / 2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ //----------offset u/v addr--------//\r
+\r
+ offset_addr_uv = offset_addr_uv_w + offset_addr_uv_h;\r
+ offset_addr_v = offset_addr_v_w + offset_addr_v_h;\r
+ //**********************************************//\r
+ //***********yuv address *********************//\r
+ //**********************************************//\r
+ src_addr_yrgb = ((u32)iep_msg->src.mem_addr) + offset_addr_y;\r
+ src_addr_cbcr = ((u32)iep_msg->src.uv_addr) + offset_addr_uv;\r
+ src_addr_cr = ((u32)iep_msg->src.v_addr) + offset_addr_v;\r
+\r
+ // former frame when processing deinterlace\r
+ src_addr_y1 = ((u32)iep_msg->src1.mem_addr) + offset_addr_y;\r
+ src_addr_cbcr1 = ((u32)iep_msg->src1.uv_addr) + offset_addr_uv;\r
+ src_addr_cr1 = ((u32)iep_msg->src1.v_addr) + offset_addr_v;\r
+\r
+ src_addr_y_itemp = ((u32)iep_msg->src_itemp.mem_addr) + offset_addr_y;\r
+ src_addr_cbcr_itemp = ((u32)iep_msg->src_itemp.uv_addr) + offset_addr_uv;\r
+ src_addr_cr_itemp = ((u32)iep_msg->src_itemp.v_addr) + offset_addr_v;\r
+\r
+ src_addr_y_ftemp = ((u32)iep_msg->src_ftemp.mem_addr) + offset_addr_y;\r
+ src_addr_cbcr_ftemp = ((u32)iep_msg->src_ftemp.uv_addr) + offset_addr_uv;\r
+ src_addr_cr_ftemp = ((u32)iep_msg->src_ftemp.v_addr) + offset_addr_v;\r
+\r
+ if ((iep_msg->dein_mode == IEP_DEINTERLACE_MODE_I4O1 || iep_msg->dein_mode == IEP_DEINTERLACE_MODE_I4O2) &&\r
+#if 1\r
+ iep_msg->field_order == FIELD_ORDER_BOTTOM_FIRST\r
+#else\r
+ iep_msg->field_order == FIELD_ORDER_TOP_FIRST\r
+#endif\r
+ ) {\r
+ IEP_REGB_SRC_ADDR_YRGB(iep_msg->base, src_addr_y1);\r
+ IEP_REGB_SRC_ADDR_CBCR(iep_msg->base, src_addr_cbcr1);\r
+ IEP_REGB_SRC_ADDR_CR(iep_msg->base, src_addr_cr1);\r
+ IEP_REGB_SRC_ADDR_Y1(iep_msg->base, src_addr_yrgb);\r
+ IEP_REGB_SRC_ADDR_CBCR1(iep_msg->base, src_addr_cbcr);\r
+ IEP_REGB_SRC_ADDR_CR1(iep_msg->base, src_addr_cr);\r
+ } else {\r
+ IEP_REGB_SRC_ADDR_YRGB(iep_msg->base, src_addr_yrgb);\r
+ IEP_REGB_SRC_ADDR_CBCR(iep_msg->base, src_addr_cbcr);\r
+ IEP_REGB_SRC_ADDR_CR(iep_msg->base, src_addr_cr);\r
+ IEP_REGB_SRC_ADDR_Y1(iep_msg->base, src_addr_y1);\r
+ IEP_REGB_SRC_ADDR_CBCR1(iep_msg->base, src_addr_cbcr1);\r
+ IEP_REGB_SRC_ADDR_CR1(iep_msg->base, src_addr_cr1);\r
+ }\r
+\r
+ if (iep_msg->yuv_3D_denoise_en) {\r
+ IEP_REGB_SRC_ADDR_Y_ITEMP(iep_msg->base, src_addr_y_itemp);\r
+ IEP_REGB_SRC_ADDR_CBCR_ITEMP(iep_msg->base, src_addr_cbcr_itemp);\r
+ IEP_REGB_SRC_ADDR_Y_FTEMP(iep_msg->base, src_addr_y_ftemp);\r
+ IEP_REGB_SRC_ADDR_CBCR_FTEMP(iep_msg->base, src_addr_cbcr_ftemp);\r
+ if ((iep_msg->src.format == IEP_FORMAT_YCbCr_422_P) || (iep_msg->src.format == IEP_FORMAT_YCbCr_420_P) \r
+ || (iep_msg->src.format == IEP_FORMAT_YCrCb_422_P) || (iep_msg->src.format == IEP_FORMAT_YCrCb_420_P)) {\r
+ IEP_REGB_SRC_ADDR_CR_ITEMP(iep_msg->base, src_addr_cr_itemp);\r
+ IEP_REGB_SRC_ADDR_CR_FTEMP(iep_msg->base, src_addr_cr_ftemp);\r
+ }\r
+ }\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//-------source address for image-------// \n\n");\r
+ IEP_DBG("sw_src_addr_yrgb = 32'h%x;\n", src_addr_yrgb);\r
+ IEP_DBG("sw_src_addr_cbcr = 32'h%x;\n", src_addr_cbcr);\r
+ IEP_DBG("sw_src_addr_cr = 32'h%x;\n", src_addr_cr);\r
+ IEP_DBG("sw_src_addr_y1 = 32'h%x;\n", src_addr_y1);\r
+ IEP_DBG("sw_src_addr_cbcr0 = 32'h%x;\n", src_addr_cbcr1);\r
+ IEP_DBG("sw_src_addr_cr0 = 32'h%x;\n", src_addr_cr1);\r
+ IEP_DBG("sw_src_addr_y_itemp = 32'h%x;\n", src_addr_y_itemp);\r
+ IEP_DBG("sw_src_addr_cbcr_itemp = 32'h%x;\n", src_addr_cbcr_itemp);\r
+ IEP_DBG("sw_src_addr_cr_itemp = 32'h%x;\n", src_addr_cr_itemp);\r
+ IEP_DBG("sw_src_addr_y_ftemp = 32'h%x;\n", src_addr_y_ftemp);\r
+ IEP_DBG("sw_src_addr_cbcr_ftemp = 32'h%x;\n", src_addr_cbcr_ftemp);\r
+ IEP_DBG("sw_src_addr_cr_ftemp = 32'h%x;\n\n", src_addr_cr_ftemp);\r
+#endif\r
+}\r
+\r
+static void iep_config_dst_addr(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_DST_ADDR_YRGB(iep_msg->base, (u32)iep_msg->dst.mem_addr);\r
+ IEP_REGB_DST_ADDR_CBCR(iep_msg->base, (u32)iep_msg->dst.uv_addr);\r
+ IEP_REGB_DST_ADDR_Y1(iep_msg->base, (u32)iep_msg->dst1.mem_addr);\r
+ IEP_REGB_DST_ADDR_CBCR1(iep_msg->base, (u32)iep_msg->dst1.uv_addr);\r
+ IEP_REGB_DST_ADDR_CR(iep_msg->base, (u32)iep_msg->dst.v_addr);\r
+ IEP_REGB_DST_ADDR_CR1(iep_msg->base, (u32)iep_msg->dst1.v_addr);\r
+\r
+ if (iep_msg->yuv_3D_denoise_en) {\r
+ IEP_REGB_DST_ADDR_Y_ITEMP(iep_msg->base, (u32)iep_msg->dst_itemp.mem_addr);\r
+ IEP_REGB_DST_ADDR_CBCR_ITEMP(iep_msg->base, (u32)iep_msg->dst_itemp.uv_addr);\r
+ IEP_REGB_DST_ADDR_Y_FTEMP(iep_msg->base, (u32)iep_msg->dst_ftemp.mem_addr);\r
+ IEP_REGB_DST_ADDR_CBCR_FTEMP(iep_msg->base, (u32)iep_msg->dst_ftemp.uv_addr);\r
+ if ((iep_msg->dst.format == IEP_FORMAT_YCbCr_422_P) || (iep_msg->dst.format == IEP_FORMAT_YCbCr_420_P) \r
+ || (iep_msg->dst.format == IEP_FORMAT_YCrCb_422_P) || (iep_msg->dst.format == IEP_FORMAT_YCrCb_420_P)) {\r
+ IEP_REGB_DST_ADDR_CR_ITEMP(iep_msg->base, (u32)iep_msg->dst_itemp.v_addr);\r
+ IEP_REGB_DST_ADDR_CR_FTEMP(iep_msg->base, (u32)iep_msg->dst_ftemp.v_addr);\r
+ }\r
+ }\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//-------destination address for image-------// \n\n");\r
+ IEP_DBG("sw_dst_addr_yrgb = 32'h%x;\n", (u32)iep_msg->dst.mem_addr);\r
+ IEP_DBG("sw_dst_addr_cbcr = 32'h%x;\n", (u32)iep_msg->dst.uv_addr);\r
+ IEP_DBG("sw_dst_addr_cr = 32'h%x;\n", (u32)iep_msg->dst.v_addr);\r
+ IEP_DBG("sw_dst_addr_y1 = 32'h%x;\n", (u32)iep_msg->dst1.mem_addr);\r
+ IEP_DBG("sw_dst_addr_cbcr0 = 32'h%x;\n", (u32)iep_msg->dst1.uv_addr);\r
+ IEP_DBG("sw_dst_addr_cr0 = 32'h%x;\n", (u32)iep_msg->dst1.v_addr);\r
+ IEP_DBG("sw_dst_addr_y_itemp = 32'h%x;\n", (u32)iep_msg->dst_itemp.mem_addr);\r
+ IEP_DBG("sw_dst_addr_cbcr_itemp = 32'h%x;\n", (u32)iep_msg->dst_itemp.uv_addr);\r
+ IEP_DBG("sw_dst_addr_cr_itemp = 32'h%x;\n", (u32)iep_msg->dst_itemp.v_addr);\r
+ IEP_DBG("sw_dst_addr_y_ftemp = 32'h%x;\n", (u32)iep_msg->dst_ftemp.mem_addr);\r
+ IEP_DBG("sw_dst_addr_cbcr_ftemp = 32'h%x;\n", (u32)iep_msg->dst_ftemp.uv_addr);\r
+ IEP_DBG("sw_dst_addr_cr_ftemp = 32'h%x;\n\n", (u32)iep_msg->dst_ftemp.v_addr);\r
+#endif\r
+}\r
+\r
+void iep_config_lcdc_path(IEP_MSG *iep_msg)\r
+{\r
+ IEP_REGB_LCDC_PATH_EN(iep_msg->base, iep_msg->lcdc_path_en);\r
+\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//==write back or lcdc direct path config=====// \n\n");\r
+ IEP_DBG("sw_lcdc_path_en = %d;//lcdc direct path enable,c model don't care this value\n\n", iep_msg->lcdc_path_en);\r
+#endif\r
+}\r
+\r
+int iep_probe_int(void *base)\r
+{\r
+ return ReadReg32(base, rIEP_INT) & 1;\r
+}\r
+\r
+void iep_config_frame_end_int_clr(void *base)\r
+{\r
+ IEP_REGB_FRAME_END_INT_CLR(base, 1);\r
+}\r
+\r
+void iep_config_frame_end_int_en(void *base)\r
+{\r
+ IEP_REGB_FRAME_END_INT_CLR(base, 1);\r
+ IEP_REGB_FRAME_END_INT_EN(base, 1);\r
+}\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+struct iep_mmu_int_status iep_probe_mmu_int_status(void *base)\r
+{\r
+ uint32_t mmu_int_sts = IEP_REGB_MMU_INT_STATUS(base);\r
+ struct iep_mmu_int_status sts;\r
+\r
+ memcpy(&sts, &mmu_int_sts, 4);\r
+\r
+ return sts;\r
+}\r
+\r
+void iep_config_mmu_page_fault_int_en(void *base, bool en)\r
+{\r
+ IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN(base, en);\r
+}\r
+\r
+void iep_config_mmu_page_fault_int_clr(void *base)\r
+{\r
+ IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR(base, 1);\r
+}\r
+\r
+void iep_config_mmu_read_bus_error_int_clr(void *base)\r
+{\r
+ IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR(base, 1);\r
+}\r
+\r
+uint32_t iep_probe_mmu_page_fault_addr(void *base)\r
+{\r
+ return IEP_REGB_MMU_PAGE_FAULT_ADDR(base);\r
+}\r
+\r
+void iep_config_mmu_cmd(void *base, enum iep_mmu_cmd cmd)\r
+{\r
+ IEP_REGB_MMU_CMD(base, cmd);\r
+}\r
+\r
+void iep_config_mmu_dte_addr(void *base, uint32_t addr) {\r
+ IEP_REGB_MMU_DTE_ADDR(base, addr);\r
+}\r
+#endif\r
+\r
+void iep_config_misc(IEP_MSG *iep_msg)\r
+{\r
+// IEP_REGB_V_REVERSE_DISP();\r
+// IEP_REGB_H_REVERSE_DISP();\r
+#ifdef IEP_PRINT_INFO\r
+ IEP_DBG("//==misc config==========================//\n\n");\r
+ IEP_DBG("sw_v_reverse_disp = 0;\n");\r
+ IEP_DBG("sw_u_reverse_disp = 0;\n\n");\r
+#endif\r
+}\r
+\r
+#define IEP_RESET_TIMEOUT 1000\r
+void iep_soft_rst(void *base)\r
+{\r
+ unsigned int rst_state = 0;\r
+ int i = 0;\r
+ WriteReg32(base, rIEP_SOFT_RST, 2);\r
+ WriteReg32(base, rIEP_SOFT_RST, 1);\r
+ while (i++ < IEP_RESET_TIMEOUT) {\r
+ rst_state = ReadReg32(base, IEP_STATUS);\r
+ if ((rst_state & 0x200) == 0x200) {\r
+ break;\r
+ }\r
+\r
+ udelay(1);\r
+ }\r
+ WriteReg32(base, IEP_SOFT_RST, 2);\r
+\r
+ if (i == IEP_RESET_TIMEOUT) IEP_DBG("soft reset timeout.\n");\r
+}\r
+\r
+void iep_config_done(void *base)\r
+{\r
+ WriteReg32(base, rIEP_CONF_DONE, 1);\r
+}\r
+\r
+void iep_config_frm_start(void *base)\r
+{\r
+ IEP_REGB_FRM_START(base, 1);\r
+}\r
+\r
+struct iep_status iep_get_status(void *base)\r
+{\r
+ uint32_t sts_int = IEP_REGB_STATUS(base);\r
+ struct iep_status sts;\r
+\r
+ memcpy(&sts, &sts_int, 4);\r
+\r
+ return sts;\r
+}\r
+\r
+int iep_get_deinterlace_mode(void *base)\r
+{\r
+ int cfg = ReadReg32(base, IEP_CONFIG0);\r
+ return (cfg >> 8) & 0x7;\r
+}\r
+\r
+void iep_set_deinterlace_mode(int mode, void *base)\r
+{\r
+ int cfg;\r
+\r
+ if (mode > dein_mode_bypass) {\r
+ IEP_ERR("invalid deinterlace mode\n");\r
+ return;\r
+ }\r
+\r
+ cfg = ReadReg32(base, RAW_IEP_CONFIG0);\r
+ cfg = (cfg & (~(7<<8))) | (mode << 8);\r
+ WriteReg32(base, IEP_CONFIG0, cfg);\r
+\r
+ //IEP_REGB_DIL_MODE(base, mode);\r
+}\r
+\r
+void iep_switch_input_address(void *base) {\r
+ u32 src_addr_yrgb = ReadReg32(base, IEP_SRC_ADDR_YRGB);\r
+ u32 src_addr_cbcr = ReadReg32(base, IEP_SRC_ADDR_CBCR);\r
+ u32 src_addr_cr = ReadReg32(base, IEP_SRC_ADDR_CR);\r
+\r
+ u32 src_addr_y1 = ReadReg32(base, IEP_SRC_ADDR_Y1);\r
+ u32 src_addr_cbcr1 = ReadReg32(base, IEP_SRC_ADDR_CBCR1);\r
+ u32 src_addr_cr1 = ReadReg32(base, IEP_SRC_ADDR_CR1);\r
+\r
+ IEP_REGB_SRC_ADDR_YRGB (base, src_addr_y1);\r
+ IEP_REGB_SRC_ADDR_CBCR (base, src_addr_cbcr1);\r
+ IEP_REGB_SRC_ADDR_CR (base, src_addr_cr1);\r
+ IEP_REGB_SRC_ADDR_Y1 (base, src_addr_yrgb);\r
+ IEP_REGB_SRC_ADDR_CBCR1(base, src_addr_cbcr);\r
+ IEP_REGB_SRC_ADDR_CR1 (base, src_addr_cr);\r
+}\r
+\r
+/**\r
+ * generating a series of registers copy from iep message\r
+ */\r
+extern iep_service_info iep_service;\r
+void iep_config(iep_session *session, IEP_MSG *iep_msg)\r
+{\r
+ struct iep_reg *reg = kzalloc(sizeof(struct iep_reg), GFP_KERNEL);\r
+\r
+ reg->session = session;\r
+ iep_msg->base = reg->reg;\r
+ atomic_set(®->session->done, 0);\r
+\r
+ INIT_LIST_HEAD(®->session_link);\r
+ INIT_LIST_HEAD(®->status_link);\r
+\r
+ //write config\r
+ iep_config_src_size(iep_msg);\r
+ iep_config_dst_size(iep_msg);\r
+ iep_config_dst_width_tile(iep_msg); //not implement\r
+ iep_config_dst_fmt(iep_msg);\r
+ iep_config_src_fmt(iep_msg);\r
+ iep_config_scl(iep_msg);\r
+ iep_config_cg_order(iep_msg);\r
+\r
+ iep_config_cg(iep_msg);\r
+ iep_config_dde(iep_msg); //not implement\r
+ iep_config_color_enh(iep_msg); //not implement\r
+ iep_config_yuv_dns(iep_msg);\r
+ iep_config_dil(iep_msg);\r
+ iep_config_yuv_enh(iep_msg);\r
+ iep_config_rgb2yuv(iep_msg);\r
+ iep_config_yuv2rgb(iep_msg);\r
+ iep_config_dither_up(iep_msg);\r
+ iep_config_dither_down(iep_msg);\r
+ iep_config_glb_alpha(iep_msg);\r
+ iep_config_vir_line(iep_msg);\r
+ iep_config_src_addr(iep_msg);\r
+ iep_config_dst_addr(iep_msg);\r
+ iep_config_lcdc_path(iep_msg);\r
+ iep_config_misc(iep_msg); //not implement\r
+\r
+ if (iep_msg->lcdc_path_en) {\r
+ reg->dpi_en = true;\r
+ reg->act_width = iep_msg->dst.act_w;\r
+ reg->act_height = iep_msg->dst.act_h;\r
+ reg->off_x = iep_msg->off_x;\r
+ reg->off_y = iep_msg->off_y;\r
+ reg->vir_width = iep_msg->width;\r
+ reg->vir_height = iep_msg->height;\r
+ reg->layer = iep_msg->layer;\r
+ reg->format = iep_msg->dst.format;\r
+ } else {\r
+ reg->dpi_en = false;\r
+ }\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+ if (iep_msg->vir_addr_enable) {\r
+ iep_config_mmu_cmd(iep_msg->base, MMU_ENABLE_PAGING);\r
+ iep_config_mmu_page_fault_int_en(iep_msg->base, 1);\r
+ } else {\r
+ iep_config_mmu_cmd(iep_msg->base, MMU_DISABLE_PAGING);\r
+ iep_config_mmu_page_fault_int_en(iep_msg->base, 0);\r
+ }\r
+ iep_config_mmu_dte_addr(iep_msg->base, (uint32_t)virt_to_phys((uint32_t*)session->dte_table));\r
+#endif\r
+\r
+ mutex_lock(&iep_service.lock);\r
+\r
+ list_add_tail(®->status_link, &iep_service.waiting);\r
+ list_add_tail(®->session_link, &session->waiting);\r
+ mutex_unlock(&iep_service.lock);\r
+}\r
+\r
--- /dev/null
+#ifndef IEP_REGS_H\r
+#define IEP_REGS_H\r
+#include "hw_iep_config_addr.h"\r
+#include "iep_api.h"\r
+#include "iep.h"\r
+#include "iep_drv.h"\r
+//#include "typedef.h"\r
+\r
+struct iep_status {\r
+ uint32_t reserved0 : 1; \r
+ uint32_t scl_sts : 1;\r
+ uint32_t dil_sts : 1;\r
+ uint32_t reserved1 : 1;\r
+ uint32_t wyuv_sts : 1;\r
+ uint32_t ryuv_sts : 1;\r
+ uint32_t wrgb_sts : 1;\r
+ uint32_t rrgb_sts : 1;\r
+ uint32_t voi_sts : 1;\r
+};\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+struct iep_mmu_status {\r
+ uint32_t paging_enabled : 1;\r
+ uint32_t page_fault_active : 1;\r
+ uint32_t stall_active : 1;\r
+ uint32_t idle : 1;\r
+ uint32_t replay_buffer_empty : 1;\r
+ uint32_t page_fault_is_write : 1;\r
+ uint32_t page_fault_bus_id : 5;\r
+};\r
+\r
+struct iep_mmu_int_status {\r
+ uint32_t page_fault : 1;\r
+ uint32_t read_bus_error : 1;\r
+};\r
+\r
+enum iep_mmu_cmd {\r
+ MMU_ENABLE_PAGING,\r
+ MMU_DISABLE_PAGING,\r
+ MMU_ENABLE_STALL,\r
+ MMU_DISABLE_STALL,\r
+ MMU_ZAP_CACHE,\r
+ MMU_PAGE_FAULT_DONE,\r
+ MMU_FORCE_RESET\r
+};\r
+#endif\r
+\r
+//Öмä±äÁ¿£¬¼Ä´æÆ÷ÅäÖõØÖ·\r
+#define rIEP_CONFIG0 (IEP_BASE+IEP_CONFIG0)\r
+#define rIEP_CONFIG1 (IEP_BASE+IEP_CONFIG1)\r
+\r
+#define rIEP_STATUS (IEP_BASE+IEP_STATUS)\r
+#define rIEP_INT (IEP_BASE+IEP_INT)\r
+#define rIEP_FRM_START (IEP_BASE+IEP_FRM_START)\r
+#define rIEP_SOFT_RST (IEP_BASE+IEP_SOFT_RST)\r
+#define rIEP_CONF_DONE (IEP_BASE+IEP_CONF_DONE)\r
+\r
+#define rIEP_VIR_IMG_WIDTH (IEP_BASE+IEP_VIR_IMG_WIDTH)\r
+\r
+#define rIEP_IMG_SCL_FCT (IEP_BASE+IEP_IMG_SCL_FCT)\r
+\r
+#define rIEP_SRC_IMG_SIZE (IEP_BASE+IEP_SRC_IMG_SIZE)\r
+#define rIEP_DST_IMG_SIZE (IEP_BASE+IEP_DST_IMG_SIZE)\r
+\r
+#define rIEP_DST_IMG_WIDTH_TILE0 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE0)\r
+#define rIEP_DST_IMG_WIDTH_TILE1 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE1)\r
+#define rIEP_DST_IMG_WIDTH_TILE2 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE2)\r
+#define rIEP_DST_IMG_WIDTH_TILE3 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE3)\r
+\r
+#define rIEP_ENH_YUV_CNFG_0 (IEP_BASE+IEP_ENH_YUV_CNFG_0)\r
+#define rIEP_ENH_YUV_CNFG_1 (IEP_BASE+IEP_ENH_YUV_CNFG_1)\r
+#define rIEP_ENH_YUV_CNFG_2 (IEP_BASE+IEP_ENH_YUV_CNFG_2)\r
+#define rIEP_ENH_RGB_CNFG (IEP_BASE+IEP_ENH_RGB_CNFG) \r
+#define rIEP_ENH_C_COE (IEP_BASE+IEP_ENH_C_COE)\r
+\r
+#define rIEP_SRC_ADDR_YRGB (IEP_BASE+IEP_SRC_ADDR_YRGB)\r
+#define rIEP_SRC_ADDR_CBCR (IEP_BASE+IEP_SRC_ADDR_CBCR)\r
+#define rIEP_SRC_ADDR_CR (IEP_BASE+IEP_SRC_ADDR_CR)\r
+#define rIEP_SRC_ADDR_Y1 (IEP_BASE+IEP_SRC_ADDR_Y1)\r
+#define rIEP_SRC_ADDR_CBCR1 (IEP_BASE+IEP_SRC_ADDR_CBCR1)\r
+#define rIEP_SRC_ADDR_CR1 (IEP_BASE+IEP_SRC_ADDR_CR1)\r
+#define rIEP_SRC_ADDR_Y_ITEMP (IEP_BASE+IEP_SRC_ADDR_Y_ITEMP)\r
+#define rIEP_SRC_ADDR_CBCR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_ITEMP)\r
+#define rIEP_SRC_ADDR_CR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CR_ITEMP)\r
+#define rIEP_SRC_ADDR_Y_FTEMP (IEP_BASE+IEP_SRC_ADDR_Y_FTEMP)\r
+#define rIEP_SRC_ADDR_CBCR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_FTEMP)\r
+#define rIEP_SRC_ADDR_CR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CR_FTEMP)\r
+\r
+#define rIEP_DST_ADDR_YRGB (IEP_BASE+IEP_DST_ADDR_YRGB)\r
+#define rIEP_DST_ADDR_CBCR (IEP_BASE+IEP_DST_ADDR_CBCR)\r
+#define rIEP_DST_ADDR_CR (IEP_BASE+IEP_DST_ADDR_CR)\r
+#define rIEP_DST_ADDR_Y1 (IEP_BASE+IEP_DST_ADDR_Y1)\r
+#define rIEP_DST_ADDR_CBCR1 (IEP_BASE+IEP_DST_ADDR_CBCR1)\r
+#define rIEP_DST_ADDR_CR1 (IEP_BASE+IEP_DST_ADDR_CR1)\r
+#define rIEP_DST_ADDR_Y_ITEMP (IEP_BASE+IEP_DST_ADDR_Y_ITEMP)\r
+#define rIEP_DST_ADDR_CBCR_ITEMP (IEP_BASE+IEP_DST_ADDR_CBCR_ITEMP)\r
+#define rIEP_DST_ADDR_CR_ITEMP (IEP_BASE+IEP_DST_ADDR_CR_ITEMP)\r
+#define rIEP_DST_ADDR_Y_FTEMP (IEP_BASE+IEP_DST_ADDR_Y_FTEMP)\r
+#define rIEP_DST_ADDR_CBCR_FTEMP (IEP_BASE+IEP_DST_ADDR_CBCR_FTEMP)\r
+#define rIEP_DST_ADDR_CR_FTEMP (IEP_BASE+IEP_DST_ADDR_CR_FTEMP)\r
+\r
+#define rIEP_DIL_MTN_TAB0 (IEP_BASE+IEP_DIL_MTN_TAB0)\r
+#define rIEP_DIL_MTN_TAB1 (IEP_BASE+IEP_DIL_MTN_TAB1)\r
+#define rIEP_DIL_MTN_TAB2 (IEP_BASE+IEP_DIL_MTN_TAB2)\r
+#define rIEP_DIL_MTN_TAB3 (IEP_BASE+IEP_DIL_MTN_TAB3)\r
+#define rIEP_DIL_MTN_TAB4 (IEP_BASE+IEP_DIL_MTN_TAB4)\r
+#define rIEP_DIL_MTN_TAB5 (IEP_BASE+IEP_DIL_MTN_TAB5)\r
+#define rIEP_DIL_MTN_TAB6 (IEP_BASE+IEP_DIL_MTN_TAB6)\r
+#define rIEP_DIL_MTN_TAB7 (IEP_BASE+IEP_DIL_MTN_TAB7)\r
+\r
+#define rIEP_ENH_CG_TAB (IEP_BASE+IEP_ENH_CG_TAB)\r
+\r
+#define rIEP_YUV_DNS_CRCT_TEMP (IEP_BASE+IEP_YUV_DNS_CRCT_TEMP)\r
+#define rIEP_YUV_DNS_CRCT_SPAT (IEP_BASE+IEP_YUV_DNS_CRCT_SPAT)\r
+\r
+#define rIEP_ENH_DDE_COE0 (IEP_BASE+IEP_ENH_DDE_COE0)\r
+#define rIEP_ENH_DDE_COE1 (IEP_BASE+IEP_ENH_DDE_COE1)\r
+\r
+#define RAW_rIEP_CONFIG0 (IEP_BASE+RAW_IEP_CONFIG0)\r
+#define RAW_rIEP_CONFIG1 (IEP_BASE+RAW_IEP_CONFIG1)\r
+#define RAW_rIEP_VIR_IMG_WIDTH (IEP_BASE+RAW_IEP_VIR_IMG_WIDTH)\r
+\r
+#define RAW_rIEP_IMG_SCL_FCT (IEP_BASE+RAW_IEP_IMG_SCL_FCT)\r
+\r
+#define RAW_rIEP_SRC_IMG_SIZE (IEP_BASE+RAW_IEP_SRC_IMG_SIZE)\r
+#define RAW_rIEP_DST_IMG_SIZE (IEP_BASE+RAW_IEP_DST_IMG_SIZE)\r
+\r
+#define RAW_rIEP_ENH_YUV_CNFG_0 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_0)\r
+#define RAW_rIEP_ENH_YUV_CNFG_1 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_1)\r
+#define RAW_rIEP_ENH_YUV_CNFG_2 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_2)\r
+#define RAW_rIEP_ENH_RGB_CNFG (IEP_BASE+RAW_IEP_ENH_RGB_CNFG)\r
+\r
+#define rIEP_CG_TAB_ADDR (IEP_BASE+0x0100) \r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+#define rIEP_MMU_BASE 0x0800\r
+#define rIEP_MMU_DTE_ADDR (IEP_MMU_BASE+0x00)\r
+#define rIEP_MMU_STATUS (IEP_MMU_BASE+0x04)\r
+#define rIEP_MMU_CMD (IEP_MMU_BASE+0x08)\r
+#define rIEP_MMU_PAGE_FAULT_ADDR (IEP_MMU_BASE+0x0c)\r
+#define rIEP_MMU_ZAP_ONE_LINE (IEP_MMU_BASE+0x10)\r
+#define rIEP_MMU_INT_RAWSTAT (IEP_MMU_BASE+0x14)\r
+#define rIEP_MMU_INT_CLEAR (IEP_MMU_BASE+0x18)\r
+#define rIEP_MMU_INT_MASK (IEP_MMU_BASE+0x1c)\r
+#define rIEP_MMU_INT_STATUS (IEP_MMU_BASE+0x20)\r
+#define rIEP_MMU_AUTO_GATING (IEP_MMU_BASE+0x24)\r
+#endif\r
+\r
+/*-----------------------------------------------------------------\r
+//reg bit operation definition\r
+-----------------------------------------------------------------*/\r
+/*-----------------------------------------------------------------\r
+//MaskRegBits32(addr, y, z),get z£¬Öмä±äÁ¿¡£\r
+-----------------------------------------------------------------*/\r
+//iep_config0\r
+#define IEP_REGB_V_REVERSE_DISP_Z(x) (((x)&0x1 ) << 31 )\r
+#define IEP_REGB_H_REVERSE_DISP_Z(x) (((x)&0x1 ) << 30 )\r
+#define IEP_REGB_SCL_EN_Z(x) (((x)&0x1 ) << 28 )\r
+#define IEP_REGB_SCL_SEL_Z(x) (((x)&0x3 ) << 26 )\r
+#define IEP_REGB_SCL_UP_COE_SEL_Z(x) (((x)&0x3 ) << 24 )\r
+#define IEP_REGB_DIL_EI_SEL_Z(x) (((x)&0x1 ) << 23 )\r
+#define IEP_REGB_DIL_EI_RADIUS_Z(x) (((x)&0x3 ) << 21 )\r
+#define IEP_REGB_CON_GAM_ORDER_Z(x) (((x)&0x1 ) << 20 )\r
+#define IEP_REGB_RGB_ENH_SEL_Z(x) (((x)&0x3 ) << 18 )\r
+#define IEP_REGB_RGB_CON_GAM_EN_Z(x) (((x)&0x1 ) << 17 )\r
+#define IEP_REGB_RGB_COLOR_ENH_EN_Z(x) (((x)&0x1 ) << 16 )\r
+#define IEP_REGB_DIL_EI_SMOOTH_Z(x) (((x)&0x1 ) << 15 )\r
+#define IEP_REGB_YUV_ENH_EN_Z(x) (((x)&0x1 ) << 14 )\r
+#define IEP_REGB_YUV_DNS_EN_Z(x) (((x)&0x1 ) << 13 )\r
+#define IEP_REGB_DIL_EI_MODE_Z(x) (((x)&0x1 ) << 12 )\r
+#define IEP_REGB_DIL_HF_EN_Z(x) (((x)&0x1 ) << 11 )\r
+#define IEP_REGB_DIL_MODE_Z(x) (((x)&0x7 ) << 8 )\r
+#define IEP_REGB_DIL_HF_FCT_Z(x) (((x)&0x7F) << 1 )\r
+#define IEP_REGB_LCDC_PATH_EN_Z(x) (((x)&0x1 ) << 0 )\r
+\r
+//iep_conig1\r
+#define IEP_REGB_GLB_ALPHA_Z(x) (((x)&0xff) << 24 )\r
+#define IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x) (((x)&0x1 ) << 23 )\r
+#define IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x) (((x)&0x1 ) << 22 )\r
+#define IEP_REGB_RGB_TO_YUV_EN_Z(x) (((x)&0x1 ) << 21 )\r
+#define IEP_REGB_YUV_TO_RGB_EN_Z(x) (((x)&0x1 ) << 20 )\r
+#define IEP_REGB_RGB2YUV_COE_SEL_Z(x) (((x)&0x3 ) << 18 )\r
+#define IEP_REGB_YUV2RGB_COE_SEL_Z(x) (((x)&0x3 ) << 16 )\r
+#define IEP_REGB_DITHER_DOWN_EN_Z(x) (((x)&0x1 ) << 15 )\r
+#define IEP_REGB_DITHER_UP_EN_Z(x) (((x)&0x1 ) << 14 )\r
+#define IEP_REGB_DST_YUV_SWAP_Z(x) (((x)&0x3 ) << 12 )\r
+#define IEP_REGB_DST_RGB_SWAP_Z(x) (((x)&0x3 ) << 10 )\r
+#define IEP_REGB_DST_FMT_Z(x) (((x)&0x3 ) << 8 )\r
+#define IEP_REGB_SRC_YUV_SWAP_Z(x) (((x)&0x3 ) << 4 )\r
+#define IEP_REGB_SRC_RGB_SWAP_Z(x) (((x)&0x3 ) << 2 )\r
+#define IEP_REGB_SRC_FMT_Z(x) (((x)&0x3 ) << 0 )\r
+\r
+//iep_int\r
+#define IEP_REGB_FRAME_END_INT_CLR_Z(x) (((x)&0x1 ) << 16 )\r
+#define IEP_REGB_FRAME_END_INT_EN_Z(x) (((x)&0x1 ) << 8 )\r
+\r
+//frm_start\r
+#define IEP_REGB_FRM_START_Z(x) (((x)&0x01 ) << 0 )\r
+\r
+//soft_rst\r
+#define IEP_REGB_SOFT_RST_Z(x) (((x)&0x01 ) << 0 )\r
+\r
+//iep_vir_img_width\r
+#define IEP_REGB_DST_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 16 )\r
+#define IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 0 )\r
+\r
+//iep_img_scl_fct\r
+#define IEP_REGB_SCL_VRT_FCT_Z(x) (((x)&0xffff) << 16 )\r
+#define IEP_REGB_SCL_HRZ_FCT_Z(x) (((x)&0xffff) << 0 )\r
+\r
+//iep_src_img_size\r
+#define IEP_REGB_SRC_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )\r
+#define IEP_REGB_SRC_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )\r
+//iep_dst_img_size\r
+#define IEP_REGB_DST_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )\r
+#define IEP_REGB_DST_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )\r
+\r
+//dst_img_width_tile0/1/2/3\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE0_Z(x) (((x)&0x3ff ) << 0 )\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE1_Z(x) (((x)&0x3ff ) << 0 )\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE2_Z(x) (((x)&0x3ff ) << 0 )\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE3_Z(x) (((x)&0x3ff ) << 0 )\r
+\r
+//iep_enh_yuv_cnfg0\r
+#define IEP_REGB_SAT_CON_Z(x) (((x)&0x1ff ) << 16 )\r
+#define IEP_REGB_CONTRAST_Z(x) (((x)&0xff ) << 8 )\r
+#define IEP_REGB_BRIGHTNESS_Z(x) (((x)&0x3f ) << 0 )\r
+//iep_enh_yuv_cnfg1\r
+#define IEP_REGB_COS_HUE_Z(x) (((x)&0xff ) << 8 )\r
+#define IEP_REGB_SIN_HUE_Z(x) (((x)&0xff ) << 0 )\r
+//iep_enh_yuv_cnfg2\r
+#define IEP_REGB_VIDEO_MODE_Z(x) (((x)&0x3 ) << 24 )\r
+#define IEP_REGB_COLOR_BAR_V_Z(x) (((x)&0xff ) << 16 )\r
+#define IEP_REGB_COLOR_BAR_U_Z(x) (((x)&0xff ) << 8 )\r
+#define IEP_REGB_COLOR_BAR_Y_Z(x) (((x)&0xff ) << 0 )\r
+//iep_enh_rgb_cnfg\r
+#define IEP_REGB_ENH_THRESHOLD_Z(x) (((x)&0xff ) << 16 )\r
+#define IEP_REGB_ENH_ALPHA_Z(x) (((x)&0x3f ) << 8 )\r
+#define IEP_REGB_ENH_RADIUS_Z(x) (((x)&0x3 ) << 0 )\r
+//iep_enh_c_coe\r
+#define IEP_REGB_ENH_C_COE_Z(x) (((x)&0x7f ) << 0 )\r
+//dil_mtn_tab\r
+#define IEP_REGB_DIL_MTN_TAB0_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB0_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB0_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB0_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB1_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB1_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB1_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB1_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB2_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB2_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB2_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB2_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB3_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB3_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB3_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB3_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB4_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB4_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB4_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB4_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB5_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB5_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB5_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB5_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB6_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB6_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB6_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB6_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB7_0_Z(x) (((x)&0x7f ) << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB7_1_Z(x) (((x)&0x7f ) << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB7_2_Z(x) (((x)&0x7f ) << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB7_3_Z(x) (((x)&0x7f ) << 24 )\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+// mmu\r
+#define IEP_REGB_MMU_STATUS_PAGING_ENABLE_Z(x) (((x)&0x01) << 0) \r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_Z(x) (((x)&0x01) << 1)\r
+#define IEP_REGB_MMU_STATUS_STALL_ACTIVE_Z(x) (((x)&0x01) << 2)\r
+#define IEP_REGB_MMU_STATUS_IDLE_Z(x) (((x)&0x01) << 3)\r
+#define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_Z(x) (((x)&0x01) << 4)\r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_Z(x) (((x)&0x01) << 5)\r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_Z(x) (((x)&0x1F) << 6)\r
+ \r
+#define IEP_REGB_MMU_CMD_Z(x) (((x)&0x07) << 0)\r
+ \r
+#define IEP_REGB_MMU_ZAP_ONE_LINE_Z(x) (((x)&0x01) << 0)\r
+ \r
+#define IEP_REGB_MMU_INT_RAWSTAT_PAGE_FAULT_Z(x) (((x)&0x01) << 0)\r
+#define IEP_REGB_MMU_INT_RAWSTAT_READ_BUS_ERROR_Z(x) (((x)&0x01) << 1)\r
+\r
+#define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Z(x) (((x)&0x01) << 0)\r
+#define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Z(x) (((x)&0x01) << 1)\r
+\r
+#define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x) (((x)&0x01) << 0)\r
+#define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Z(x) (((x)&0x01) << 1)\r
+\r
+#define IEP_REGB_MMU_INT_STATUS_PAGE_FAULT_Z(x) (((x)&0x01) << 0)\r
+#define IEP_REGB_MMU_INT_STATUS_READ_BUS_ERROR_Z(x) (((x)&0x01) << 1)\r
+\r
+#define IEP_REGB_MMU_AUTO_GATING_Z(x) (((x)&0x01) << 0)\r
+#endif\r
+\r
+/*-----------------------------------------------------------------\r
+//MaskRegBits32(addr, y, z),get y£¬Öмä±äÁ¿\r
+-----------------------------------------------------------------*/\r
+//iep_config0\r
+#define IEP_REGB_V_REVERSE_DISP_Y (0x1 << 31 )\r
+#define IEP_REGB_H_REVERSE_DISP_Y (0x1 << 30 )\r
+#define IEP_REGB_SCL_EN_Y (0x1 << 28 )\r
+#define IEP_REGB_SCL_SEL_Y (0x3 << 26 )\r
+#define IEP_REGB_SCL_UP_COE_SEL_Y (0x3 << 24 )\r
+#define IEP_REGB_DIL_EI_SEL_Y (0x1 << 23 )\r
+#define IEP_REGB_DIL_EI_RADIUS_Y (0x3 << 21 )\r
+#define IEP_REGB_CON_GAM_ORDER_Y (0x1 << 20 )\r
+#define IEP_REGB_RGB_ENH_SEL_Y (0x3 << 18 )\r
+#define IEP_REGB_RGB_CON_GAM_EN_Y (0x1 << 17 )\r
+#define IEP_REGB_RGB_COLOR_ENH_EN_Y (0x1 << 16 )\r
+#define IEP_REGB_DIL_EI_SMOOTH_Y (0x1 << 15 )\r
+#define IEP_REGB_YUV_ENH_EN_Y (0x1 << 14 )\r
+#define IEP_REGB_YUV_DNS_EN_Y (0x1 << 13 )\r
+#define IEP_REGB_DIL_EI_MODE_Y (0x1 << 12 )\r
+#define IEP_REGB_DIL_HF_EN_Y (0x1 << 11 )\r
+#define IEP_REGB_DIL_MODE_Y (0x7 << 8 )\r
+#define IEP_REGB_DIL_HF_FCT_Y (0x7F << 1 )\r
+#define IEP_REGB_LCDC_PATH_EN_Y (0x1 << 0 )\r
+\r
+//iep_conig1\r
+#define IEP_REGB_GLB_ALPHA_Y (0xff << 24 )\r
+#define IEP_REGB_RGB2YUV_INPUT_CLIP_Y (0x1 << 23 )\r
+#define IEP_REGB_YUV2RGB_INPUT_CLIP_Y (0x1 << 22 )\r
+#define IEP_REGB_RGB_TO_YUV_EN_Y (0x1 << 21 )\r
+#define IEP_REGB_YUV_TO_RGB_EN_Y (0x1 << 20 )\r
+#define IEP_REGB_RGB2YUV_COE_SEL_Y (0x3 << 18 )\r
+#define IEP_REGB_YUV2RGB_COE_SEL_Y (0x3 << 16 )\r
+#define IEP_REGB_DITHER_DOWN_EN_Y (0x1 << 15 )\r
+#define IEP_REGB_DITHER_UP_EN_Y (0x1 << 14 )\r
+#define IEP_REGB_DST_YUV_SWAP_Y (0x3 << 12 )\r
+#define IEP_REGB_DST_RGB_SWAP_Y (0x3 << 10 )\r
+#define IEP_REGB_DST_FMT_Y (0x3 << 8 )\r
+#define IEP_REGB_SRC_YUV_SWAP_Y (0x3 << 4 )\r
+#define IEP_REGB_SRC_RGB_SWAP_Y (0x3 << 2 )\r
+#define IEP_REGB_SRC_FMT_Y (0x3 << 0 )\r
+\r
+//iep_int\r
+#define IEP_REGB_FRAME_END_INT_CLR_Y (0x1 << 16 )\r
+#define IEP_REGB_FRAME_END_INT_EN_Y (0x1 << 8 )\r
+\r
+//frm_start\r
+#define IEP_REGB_FRM_START_Y (0x1 << 0 )\r
+\r
+//soft_rst\r
+#define IEP_REGB_SOFT_RST_Y (0x1 << 0 )\r
+\r
+//iep_vir_img_width\r
+#define IEP_REGB_DST_VIR_LINE_WIDTH_Y (0xffff << 16 )\r
+#define IEP_REGB_SRC_VIR_LINE_WIDTH_Y (0xffff << 0 )\r
+\r
+//iep_img_scl_fct\r
+#define IEP_REGB_SCL_VRT_FCT_Y (0xffff << 16 )\r
+#define IEP_REGB_SCL_HRZ_FCT_Y (0xffff << 0 )\r
+\r
+//iep_src_img_size\r
+#define IEP_REGB_SRC_IMG_HEIGHT_Y (0x1fff << 16 )\r
+#define IEP_REGB_SRC_IMG_WIDTH_Y (0x1fff << 0 )\r
+//iep_dst_img_size\r
+#define IEP_REGB_DST_IMG_HEIGHT_Y (0x1fff << 16 )\r
+#define IEP_REGB_DST_IMG_WIDTH_Y (0x1fff << 0 )\r
+\r
+//dst_img_width_tile0/1/2/3\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE0_Y (0x3ff << 0 )\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE1_Y (0x3ff << 0 )\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE2_Y (0x3ff << 0 )\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE3_Y (0x3ff << 0 )\r
+\r
+//iep_enh_yuv_cnfg0\r
+#define IEP_REGB_SAT_CON_Y (0x1ff << 16)\r
+#define IEP_REGB_CONTRAST_Y (0xff << 8 )\r
+#define IEP_REGB_BRIGHTNESS_Y (0x3f << 0 )\r
+//iep_enh_yuv_cnfg1\r
+#define IEP_REGB_COS_HUE_Y (0xff << 8 )\r
+#define IEP_REGB_SIN_HUE_Y (0xff << 0 )\r
+//iep_enh_yuv_cnfg2\r
+#define IEP_REGB_VIDEO_MODE_Y (0x3 << 24)\r
+#define IEP_REGB_COLOR_BAR_V_Y (0xff << 16)\r
+#define IEP_REGB_COLOR_BAR_U_Y (0xff << 8 )\r
+#define IEP_REGB_COLOR_BAR_Y_Y (0xff << 0 )\r
+//iep_enh_rgb_cnfg\r
+#define IEP_REGB_ENH_THRESHOLD_Y (0xff << 16)\r
+#define IEP_REGB_ENH_ALPHA_Y (0x3f << 8 )\r
+#define IEP_REGB_ENH_RADIUS_Y (0x3 << 0 )\r
+//iep_enh_c_coe\r
+#define IEP_REGB_ENH_C_COE_Y (0x7f << 0 )\r
+//dil_mtn_tab\r
+#define IEP_REGB_DIL_MTN_TAB0_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB0_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB0_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB0_3_Y (0x7f << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB1_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB1_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB1_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB1_3_Y (0x7f << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB2_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB2_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB2_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB2_3_Y (0x7f << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB3_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB3_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB3_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB3_3_Y (0x7f << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB4_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB4_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB4_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB4_3_Y (0x7f << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB5_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB5_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB5_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB5_3_Y (0x7f << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB6_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB6_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB6_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB6_3_Y (0x7f << 24 )\r
+\r
+#define IEP_REGB_DIL_MTN_TAB7_0_Y (0x7f << 0 )\r
+#define IEP_REGB_DIL_MTN_TAB7_1_Y (0x7f << 8 )\r
+#define IEP_REGB_DIL_MTN_TAB7_2_Y (0x7f << 16 )\r
+#define IEP_REGB_DIL_MTN_TAB7_3_Y (0x7f << 24 )\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+// mmu\r
+#define IEP_REGB_MMU_STATUS_PAGING_ENABLE_Y (0x01 << 0) \r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_Y (0x01 << 1)\r
+#define IEP_REGB_MMU_STATUS_STALL_ACTIVE_Y (0x01 << 2)\r
+#define IEP_REGB_MMU_STATUS_IDLE_Y (0x01 << 3)\r
+#define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_Y (0x01 << 4)\r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_Y (0x01 << 5)\r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_Y (0x1F << 6)\r
+ \r
+#define IEP_REGB_MMU_CMD_Y (0x07 << 0)\r
+ \r
+#define IEP_REGB_MMU_ZAP_ONE_LINE_Y (0x01 << 0)\r
+ \r
+#define IEP_REGB_MMU_INT_RAWSTAT_PAGE_FAULT_Y (0x01 << 0)\r
+#define IEP_REGB_MMU_INT_RAWSTAT_READ_BUS_ERROR_Y (0x01 << 1)\r
+\r
+#define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Y (0x01 << 0)\r
+#define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Y (0x01 << 1)\r
+\r
+#define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Y (0x01 << 0)\r
+#define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Y (0x01 << 1)\r
+\r
+#define IEP_REGB_MMU_INT_STATUS_PAGE_FAULT_Y (0x01 << 0)\r
+#define IEP_REGB_MMU_INT_STATUS_READ_BUS_ERROR_Y (0x01 << 1)\r
+\r
+#define IEP_REGB_MMU_AUTO_GATING_Y (0x01 << 0)\r
+\r
+// offset\r
+#define IEP_REGB_MMU_STATUS_PAGING_ENABLE_F (0) \r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_F (1)\r
+#define IEP_REGB_MMU_STATUS_STALL_ACTIVE_F (2)\r
+#define IEP_REGB_MMU_STATUS_IDLE_F (3)\r
+#define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_F (4)\r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_F (5)\r
+#define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_F (6)\r
+#endif\r
+\r
+/*-----------------------------------------------------------------\r
+//MaskRegBits32(addr, y, z),¼Ä´æÆ÷ÅäÖÃ\r
+-----------------------------------------------------------------*/\r
+//iep_config0\r
+#define IEP_REGB_V_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_V_REVERSE_DISP_Y,IEP_REGB_V_REVERSE_DISP_Z(x))\r
+#define IEP_REGB_H_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_H_REVERSE_DISP_Y,IEP_REGB_H_REVERSE_DISP_Z(x))\r
+#define IEP_REGB_SCL_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_EN_Y,IEP_REGB_SCL_EN_Z(x))\r
+#define IEP_REGB_SCL_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_SEL_Y,IEP_REGB_SCL_SEL_Z(x))\r
+#define IEP_REGB_SCL_UP_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_UP_COE_SEL_Y,IEP_REGB_SCL_UP_COE_SEL_Z(x))\r
+#define IEP_REGB_DIL_EI_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SEL_Y,IEP_REGB_DIL_EI_SEL_Z(x))\r
+#define IEP_REGB_DIL_EI_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_RADIUS_Y,IEP_REGB_DIL_EI_RADIUS_Z(x))\r
+#define IEP_REGB_CON_GAM_ORDER(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_CON_GAM_ORDER_Y,IEP_REGB_CON_GAM_ORDER_Z(x))\r
+#define IEP_REGB_RGB_ENH_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_ENH_SEL_Y,IEP_REGB_RGB_ENH_SEL_Z(x))\r
+#define IEP_REGB_RGB_CON_GAM_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_CON_GAM_EN_Y,IEP_REGB_RGB_CON_GAM_EN_Z(x))\r
+#define IEP_REGB_RGB_COLOR_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_COLOR_ENH_EN_Y,IEP_REGB_RGB_COLOR_ENH_EN_Z(x))\r
+#define IEP_REGB_DIL_EI_SMOOTH(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SMOOTH_Y,IEP_REGB_DIL_EI_SMOOTH_Z(x))\r
+#define IEP_REGB_YUV_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_ENH_EN_Y,IEP_REGB_YUV_ENH_EN_Z(x))\r
+#define IEP_REGB_YUV_DNS_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_DNS_EN_Y,IEP_REGB_YUV_DNS_EN_Z(x))\r
+#define IEP_REGB_DIL_EI_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_MODE_Y,IEP_REGB_DIL_EI_MODE_Z(x))\r
+#define IEP_REGB_DIL_HF_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_EN_Y,IEP_REGB_DIL_HF_EN_Z(x))\r
+#define IEP_REGB_DIL_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_MODE_Y,IEP_REGB_DIL_MODE_Z(x))\r
+#define IEP_REGB_DIL_HF_FCT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_FCT_Y,IEP_REGB_DIL_HF_FCT_Z(x))\r
+#define IEP_REGB_LCDC_PATH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_LCDC_PATH_EN_Y,IEP_REGB_LCDC_PATH_EN_Z(x))\r
+\r
+//iep_conig1\r
+#define IEP_REGB_GLB_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_GLB_ALPHA_Y,IEP_REGB_GLB_ALPHA_Z(x))\r
+#define IEP_REGB_RGB2YUV_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_INPUT_CLIP_Y,IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x))\r
+#define IEP_REGB_YUV2RGB_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_INPUT_CLIP_Y,IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x))\r
+#define IEP_REGB_RGB_TO_YUV_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB_TO_YUV_EN_Y,IEP_REGB_RGB_TO_YUV_EN_Z(x))\r
+#define IEP_REGB_YUV_TO_RGB_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV_TO_RGB_EN_Y,IEP_REGB_YUV_TO_RGB_EN_Z(x))\r
+#define IEP_REGB_RGB2YUV_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_COE_SEL_Y,IEP_REGB_RGB2YUV_COE_SEL_Z(x))\r
+#define IEP_REGB_YUV2RGB_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_COE_SEL_Y,IEP_REGB_YUV2RGB_COE_SEL_Z(x))\r
+#define IEP_REGB_DITHER_DOWN_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_DOWN_EN_Y,IEP_REGB_DITHER_DOWN_EN_Z(x))\r
+#define IEP_REGB_DITHER_UP_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_UP_EN_Y,IEP_REGB_DITHER_UP_EN_Z(x))\r
+#define IEP_REGB_DST_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_YUV_SWAP_Y,IEP_REGB_DST_YUV_SWAP_Z(x))\r
+#define IEP_REGB_DST_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_RGB_SWAP_Y,IEP_REGB_DST_RGB_SWAP_Z(x))\r
+#define IEP_REGB_DST_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_FMT_Y,IEP_REGB_DST_FMT_Z(x))\r
+#define IEP_REGB_SRC_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_YUV_SWAP_Y,IEP_REGB_SRC_YUV_SWAP_Z(x))\r
+#define IEP_REGB_SRC_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_RGB_SWAP_Y,IEP_REGB_SRC_RGB_SWAP_Z(x))\r
+#define IEP_REGB_SRC_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_FMT_Y,IEP_REGB_SRC_FMT_Z(x))\r
+\r
+//iep_int\r
+#define IEP_REGB_FRAME_END_INT_CLR(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_CLR_Y,IEP_REGB_FRAME_END_INT_CLR_Z(x))\r
+#define IEP_REGB_FRAME_END_INT_EN(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_EN_Y,IEP_REGB_FRAME_END_INT_EN_Z(x))\r
+\r
+//frm_start\r
+#define IEP_REGB_FRM_START(base, x) WriteReg32(base, rIEP_FRM_START,x)\r
+\r
+//soft_rst\r
+#define IEP_REGB_SOFT_RST(base, x) WriteReg32(base, rIEP_SOFT_RST,x)\r
+\r
+//iep_vir_img_width\r
+#define IEP_REGB_DST_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_DST_VIR_LINE_WIDTH_Y,IEP_REGB_DST_VIR_LINE_WIDTH_Z(x))\r
+#define IEP_REGB_SRC_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_SRC_VIR_LINE_WIDTH_Y,IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x))\r
+\r
+//iep_img_scl_fct\r
+#define IEP_REGB_SCL_VRT_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_VRT_FCT_Y,IEP_REGB_SCL_VRT_FCT_Z(x))\r
+#define IEP_REGB_SCL_HRZ_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_HRZ_FCT_Y,IEP_REGB_SCL_HRZ_FCT_Z(x))\r
+\r
+//iep_src_img_size\r
+#define IEP_REGB_SRC_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_HEIGHT_Y,IEP_REGB_SRC_IMG_HEIGHT_Z(x))\r
+#define IEP_REGB_SRC_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_WIDTH_Y,IEP_REGB_SRC_IMG_WIDTH_Z(x))\r
+//iep_dst_img_size\r
+#define IEP_REGB_DST_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_HEIGHT_Y,IEP_REGB_DST_IMG_HEIGHT_Z(x))\r
+#define IEP_REGB_DST_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_WIDTH_Y,IEP_REGB_DST_IMG_WIDTH_Z(x))\r
+\r
+//dst_img_width_tile0/1/2/3\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE0(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE0,x)\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE1(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE1,x)\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE2(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE2,x)\r
+#define IEP_REGB_DST_IMG_WIDTH_TILE3(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE3,x)\r
+\r
+//iep_enh_yuv_cnfg0\r
+#define IEP_REGB_SAT_CON(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_SAT_CON_Y,IEP_REGB_SAT_CON_Z(x))\r
+#define IEP_REGB_CONTRAST(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_CONTRAST_Y,IEP_REGB_CONTRAST_Z(x))\r
+#define IEP_REGB_BRIGHTNESS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_BRIGHTNESS_Y,IEP_REGB_BRIGHTNESS_Z(x))\r
+//iep_enh_yuv_cnfg1\r
+#define IEP_REGB_COS_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_COS_HUE_Y,IEP_REGB_COS_HUE_Z(x))\r
+#define IEP_REGB_SIN_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_SIN_HUE_Y,IEP_REGB_SIN_HUE_Z(x))\r
+//iep_enh_yuv_cnfg2\r
+#define IEP_REGB_VIDEO_MODE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_VIDEO_MODE_Y,IEP_REGB_VIDEO_MODE_Z(x))\r
+#define IEP_REGB_COLOR_BAR_V(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_V_Y,IEP_REGB_COLOR_BAR_V_Z(x))\r
+#define IEP_REGB_COLOR_BAR_U(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_U_Y,IEP_REGB_COLOR_BAR_U_Z(x))\r
+#define IEP_REGB_COLOR_BAR_Y(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_Y_Y,IEP_REGB_COLOR_BAR_Y_Z(x))\r
+//iep_enh_rgb_cnfg\r
+#define IEP_REGB_ENH_THRESHOLD(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_THRESHOLD_Y,IEP_REGB_ENH_THRESHOLD_Z(x))\r
+#define IEP_REGB_ENH_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_ALPHA_Y,IEP_REGB_ENH_ALPHA_Z(x))\r
+#define IEP_REGB_ENH_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_RADIUS_Y,IEP_REGB_ENH_RADIUS_Z(x))\r
+//iep_enh_c_coe\r
+#define IEP_REGB_ENH_C_COE(base, x) WriteReg32(base, rIEP_ENH_C_COE,x) \r
+//src_addr\r
+#define IEP_REGB_SRC_ADDR_YRGB(base, x) WriteReg32(base, rIEP_SRC_ADDR_YRGB, x)\r
+#define IEP_REGB_SRC_ADDR_CBCR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR, x)\r
+#define IEP_REGB_SRC_ADDR_CR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR, x)\r
+#define IEP_REGB_SRC_ADDR_Y1(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y1, x)\r
+#define IEP_REGB_SRC_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR1, x)\r
+#define IEP_REGB_SRC_ADDR_CR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR1, x)\r
+#define IEP_REGB_SRC_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_ITEMP, x)\r
+#define IEP_REGB_SRC_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_ITEMP, x)\r
+#define IEP_REGB_SRC_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_ITEMP, x)\r
+#define IEP_REGB_SRC_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_FTEMP, x)\r
+#define IEP_REGB_SRC_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_FTEMP, x)\r
+#define IEP_REGB_SRC_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_FTEMP, x)\r
+//dst_addr\r
+#define IEP_REGB_DST_ADDR_YRGB(base, x) WriteReg32(base, rIEP_DST_ADDR_YRGB,x)\r
+#define IEP_REGB_DST_ADDR_CBCR(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR, x)\r
+#define IEP_REGB_DST_ADDR_CR(base, x) WriteReg32(base, rIEP_DST_ADDR_CR, x)\r
+#define IEP_REGB_DST_ADDR_Y1(base, x) WriteReg32(base, rIEP_DST_ADDR_Y1, x)\r
+#define IEP_REGB_DST_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR1, x)\r
+#define IEP_REGB_DST_ADDR_CR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CR1, x)\r
+#define IEP_REGB_DST_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_ITEMP, x)\r
+#define IEP_REGB_DST_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_ITEMP, x)\r
+#define IEP_REGB_DST_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_ITEMP, x)\r
+#define IEP_REGB_DST_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_FTEMP, x)\r
+#define IEP_REGB_DST_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_FTEMP, x)\r
+#define IEP_REGB_DST_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_FTEMP, x)\r
+\r
+//dil_mtn_tab\r
+#define IEP_REGB_DIL_MTN_TAB0(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB0,x)\r
+#define IEP_REGB_DIL_MTN_TAB1(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB1,x)\r
+#define IEP_REGB_DIL_MTN_TAB2(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB2,x)\r
+#define IEP_REGB_DIL_MTN_TAB3(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB3,x)\r
+#define IEP_REGB_DIL_MTN_TAB4(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB4,x)\r
+#define IEP_REGB_DIL_MTN_TAB5(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB5,x)\r
+#define IEP_REGB_DIL_MTN_TAB6(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB6,x)\r
+#define IEP_REGB_DIL_MTN_TAB7(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB7,x)\r
+\r
+#define IEP_REGB_STATUS(base) ReadReg32(base, rIEP_STATUS)\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+// mmu\r
+#define IEP_REGB_MMU_DTE_ADDR(base, x) WriteReg32(base, rIEP_MMU_DTE_ADDR, x)\r
+#define IEP_REGB_MMU_STATUS(base) ReadReg32(base, rIEP_MMU_STATUS)\r
+ \r
+#define IEP_REGB_MMU_CMD(base, x) MaskRegBits32(base, rIEP_MMU_CMD, IEP_REGB_MMU_CMD_Y, IEP_REGB_MMU_CMD_Z(x))\r
+ \r
+#define IEP_REGB_MMU_PAGE_FAULT_ADDR(base) ReadReg32(base, rIEP_MMU_PAGE_FAULT_ADDR)\r
+ \r
+#define IEP_REGB_MMU_ZAP_ONE_LINE(base, x) MaskRegBits32(base, rIEP_MMU_ZAP_ONE_LINE, \\r
+ IEP_REGB_MMU_ZAP_ONE_LINE_Y, \\r
+ IEP_REGB_MMU_ZAP_ONE_LINE_Z(x))\r
+ \r
+#define IEP_REGB_MMU_INT_RAWSTAT(base) ReadReg32(base, rIEP_MMU_INT_RAWSTAT)\r
+\r
+#define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR(base, x) MaskRegBits32(base, rIEP_MMU_INT_CLEAR, \\r
+ IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Y, \\r
+ IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Z(x))\r
+#define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR(base, x) MaskRegBits32(base, rIEP_MMU_INT_CLEAR, \\r
+ IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Y, \\r
+ IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Z(x))\r
+\r
+#define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN(base, x) MaskRegBits32(base, rIEP_MMU_INT_MASK, \\r
+ IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Y, \\r
+ IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x))\r
+#define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN(base, x) MaskRegBits32(base, rIEP_MMU_INT_MASK, \\r
+ IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Y, \\r
+ IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x))\r
+\r
+#define IEP_REGB_MMU_INT_STATUS(base) ReadReg32(base, rIEP_MMU_INT_STATUS)\r
+\r
+#define IEP_REGB_MMU_AUTO_GATING(base, x) MaskRegBits32(base, rIEP_MMU_AUTO_GATING, \\r
+ IEP_REGB_MMU_AUTO_GATING_Y, \\r
+ IEP_REGB_MMU_AUTO_GATING_Z(x))\r
+#endif\r
+\r
+///function define\r
+void iep_config_lcdc_path(IEP_MSG *iep_msg);\r
+\r
+/// system control, directly operating the device registers. \r
+/// parameter @base need to be set to device base address.\r
+void iep_soft_rst(void *base);\r
+void iep_config_done(void *base);\r
+void iep_config_frm_start(void *base);\r
+int iep_probe_int(void *base);\r
+void iep_config_frame_end_int_clr(void *base);\r
+void iep_config_frame_end_int_en(void *base); \r
+struct iep_status iep_get_status(void *base);\r
+#if defined(CONFIG_IEP_MMU)\r
+struct iep_mmu_int_status iep_probe_mmu_int_status(void *base);\r
+void iep_config_mmu_page_fault_int_en(void *base, bool en);\r
+void iep_config_mmu_page_fault_int_clr(void *base);\r
+void iep_config_mmu_read_bus_error_int_clr(void *base);\r
+uint32_t iep_probe_mmu_page_fault_addr(void *base);\r
+void iep_config_mmu_cmd(void *base, enum iep_mmu_cmd cmd);\r
+void iep_config_mmu_dte_addr(void *base, uint32_t addr);\r
+#endif\r
+int iep_get_deinterlace_mode(void *base);\r
+void iep_set_deinterlace_mode(int mode, void *base);\r
+void iep_switch_input_address(void *base);\r
+\r
+/// generating a series of iep registers copy to the session private buffer\r
+void iep_config(iep_session *session, IEP_MSG *iep_msg); \r
+\r
+//#define IEP_PRINT_INFO\r
+#endif\r
+\r
+\r
--- /dev/null
+#ifndef _IEP_H_\r
+#define _IEP_H_\r
+\r
+#define IEP_IOC_MAGIC 'i'\r
+\r
+#define IEP_SET_PARAMETER_REQ _IOW(IEP_IOC_MAGIC, 1, unsigned long)\r
+#define IEP_SET_PARAMETER_DEINTERLACE _IOW(IEP_IOC_MAGIC, 2, unsigned long)\r
+#define IEP_SET_PARAMETER_ENHANCE _IOW(IEP_IOC_MAGIC, 3, unsigned long)\r
+#define IEP_SET_PARAMETER_CONVERT _IOW(IEP_IOC_MAGIC, 4, unsigned long)\r
+#define IEP_SET_PARAMETER_SCALE _IOW(IEP_IOC_MAGIC, 5, unsigned long)\r
+#define IEP_GET_RESULT_SYNC _IOW(IEP_IOC_MAGIC, 6, unsigned long)\r
+#define IEP_GET_RESULT_ASYNC _IOW(IEP_IOC_MAGIC, 7, unsigned long)\r
+#define IEP_SET_PARAMETER _IOW(IEP_IOC_MAGIC, 8, unsigned long)\r
+#define IEP_RELEASE_CURRENT_TASK _IOW(IEP_IOC_MAGIC, 9, unsigned long)\r
+\r
+/* Driver information */\r
+#define DRIVER_DESC "IEP Device Driver"\r
+#define DRIVER_NAME "iep"\r
+\r
+/* Logging */\r
+#define IEP_DEBUG 0\r
+#if IEP_DEBUG\r
+#define IEP_DBG(format, args...) printk("%s: " format, DRIVER_NAME, ## args)\r
+#else\r
+#define IEP_DBG(format, args...)\r
+#endif\r
+\r
+#define IEP_INFORMATION 1\r
+#if IEP_INFORMATION\r
+#define IEP_INFO(format, args...) printk(format, ## args)\r
+#else\r
+#define IEP_INFO(format, args...)\r
+#endif\r
+\r
+#define IEP_ERR(format, args...) printk(KERN_ERR "%s: " format, DRIVER_NAME, ## args)\r
+#define IEP_WARNING(format, args...) printk(KERN_WARNING "%s: " format, DRIVER_NAME, ## args)\r
+\r
+enum\r
+{\r
+ yuv2rgb_BT_601_l = 0x0, /* BT.601_1 */\r
+ yuv2rgb_BT_601_f = 0x1, /* BT.601_f */\r
+ yuv2rgb_BT_709_l = 0x2, /* BT.709_1 */\r
+ yuv2rgb_BT_709_f = 0x3, /* BT.709_f */\r
+};\r
+\r
+enum\r
+{\r
+ rgb2yuv_BT_601_l = 0x0, /* BT.601_1 */\r
+ rgb2yuv_BT_601_f = 0x1, /* BT.601_f */\r
+ rgb2yuv_BT_709_l = 0x2, /* BT.709_1 */\r
+ rgb2yuv_BT_709_f = 0x3, /* BT.709_f */\r
+};\r
+\r
+enum\r
+{\r
+ dein_mode_bypass_dis = 0x0,\r
+ dein_mode_I4O2 = 0x1,\r
+ dein_mode_I4O1B = 0x2,\r
+ dein_mode_I4O1T = 0x3,\r
+ dein_mode_I2O1B = 0x4,\r
+ dein_mode_I2O1T = 0x5,\r
+ dein_mode_bypass = 0x6, \r
+};\r
+\r
+typedef enum IEP_FIELD_ORDER\r
+{\r
+ FIELD_ORDER_TOP_FIRST,\r
+ FIELD_ORDER_BOTTOM_FIRST\r
+} IEP_FIELD_ORDER_t;\r
+\r
+typedef enum IEP_YUV_DEINTERLACE_MODE {\r
+ IEP_DEINTERLACE_MODE_DISABLE,\r
+ IEP_DEINTERLACE_MODE_I2O1,\r
+ IEP_DEINTERLACE_MODE_I4O1,\r
+ IEP_DEINTERLACE_MODE_I4O2,\r
+ IEP_DEINTERLACE_MODE_BYPASS\r
+} IEP_YUV_DEINTERLACE_MODE_t;\r
+\r
+enum\r
+{\r
+ rgb_enhance_bypass = 0x0, \r
+ rgb_enhance_denoise = 0x1,\r
+ rgb_enhance_detail = 0x2,\r
+ rgb_enhance_edge = 0x3,\r
+};//for rgb_enhance_mode\r
+\r
+enum\r
+{\r
+ rgb_contrast_CC_P_DDE = 0x0, //cg prior to dde \r
+ rgb_contrast_DDE_P_CC = 0x1, //dde prior to cg\r
+}; //for rgb_contrast_enhance_mode\r
+\r
+enum\r
+{\r
+ black_screen = 0x0,\r
+ blue_screen = 0x1,\r
+ color_bar = 0x2,\r
+ normal_mode = 0x3,\r
+}; //for video mode\r
+\r
+/*\r
+// Alpha Red Green Blue \r
+{ 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_RGBA }, // IEP_FORMAT_ARGB_8888 \r
+{ 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // IEP_FORMAT_ABGR_8888 \r
+{ 4, 32, {{ 8, 0, 32,24, 24,16, 16, 8 }}, GGL_RGB }, // IEP_FORMAT_RGBA_8888\r
+{ 4, 32, {{ 8, 0, 16, 8, 24,16, 32,24 }}, GGL_BGRA }, // IEP_FORMAT_BGRA_8888\r
+{ 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // IEP_FORMAT_RGB_565 \r
+{ 2, 16, {{ 0, 0, 5, 0, 11, 5, 16,11 }}, GGL_RGB }, // IEP_FORMAT_RGB_565 \r
+*/\r
+enum\r
+{\r
+ IEP_FORMAT_ARGB_8888 = 0x0, \r
+ IEP_FORMAT_ABGR_8888 = 0x1, \r
+ IEP_FORMAT_RGBA_8888 = 0x2, \r
+ IEP_FORMAT_BGRA_8888 = 0x3,\r
+ IEP_FORMAT_RGB_565 = 0x4,\r
+ IEP_FORMAT_BGR_565 = 0x5,\r
+ \r
+ IEP_FORMAT_YCbCr_422_SP = 0x10,\r
+ IEP_FORMAT_YCbCr_422_P = 0x11,\r
+ IEP_FORMAT_YCbCr_420_SP = 0x12,\r
+ IEP_FORMAT_YCbCr_420_P = 0x13,\r
+ IEP_FORMAT_YCrCb_422_SP = 0x14,\r
+ IEP_FORMAT_YCrCb_422_P = 0x15,//same as IEP_FORMAT_YCbCr_422_P\r
+ IEP_FORMAT_YCrCb_420_SP = 0x16,\r
+ IEP_FORMAT_YCrCb_420_P = 0x17,//same as IEP_FORMAT_YCbCr_420_P\r
+ \r
+}; //for format\r
+\r
+typedef struct iep_img\r
+{\r
+ unsigned short act_w; // act_width\r
+ unsigned short act_h; // act_height\r
+ signed short x_off; // x offset for the vir,word unit\r
+ signed short y_off; // y offset for the vir,word unit\r
+\r
+ unsigned short vir_w; //unit :pix \r
+ unsigned short vir_h; //unit :pix\r
+ unsigned int format;\r
+ unsigned int *mem_addr;\r
+ unsigned int *uv_addr;\r
+ unsigned int *v_addr;\r
+ \r
+ unsigned char rb_swap;//not be used\r
+ unsigned char uv_swap;//not be used\r
+ \r
+ unsigned char alpha_swap;//not be used\r
+}\r
+iep_img;\r
+\r
+\r
+typedef struct IEP_MSG\r
+{\r
+ iep_img src; // src active window \r
+ iep_img dst; // src virtual window\r
+\r
+ iep_img src1; \r
+ iep_img dst1;\r
+\r
+ iep_img src_itemp;\r
+ iep_img src_ftemp;\r
+\r
+ iep_img dst_itemp;\r
+ iep_img dst_ftemp;\r
+\r
+ unsigned char dither_up_en;\r
+ unsigned char dither_down_en;//not to be used\r
+\r
+ unsigned char yuv2rgb_mode;\r
+ unsigned char rgb2yuv_mode;\r
+\r
+ unsigned char global_alpha_value;\r
+\r
+ unsigned char rgb2yuv_clip_en;\r
+ unsigned char yuv2rgb_clip_en;\r
+\r
+ unsigned char lcdc_path_en;\r
+ int off_x;\r
+ int off_y;\r
+ int width;\r
+ int height;\r
+ int layer;\r
+\r
+ unsigned char yuv_3D_denoise_en;\r
+ \r
+ /// yuv color enhance\r
+ unsigned char yuv_enhance_en;\r
+ int sat_con_int;\r
+ int contrast_int;\r
+ int cos_hue_int;\r
+ int sin_hue_int;\r
+ signed char yuv_enh_brightness;//-32<brightness<31\r
+ unsigned char video_mode;//0-3 \r
+ unsigned char color_bar_y;//0-127\r
+ unsigned char color_bar_u;//0-127 \r
+ unsigned char color_bar_v;//0-127 \r
+\r
+ \r
+ unsigned char rgb_enhance_en;//i don't konw what is used\r
+ \r
+ unsigned char rgb_color_enhance_en;//sw_rgb_color_enh_en\r
+ unsigned int rgb_enh_coe;\r
+ \r
+ unsigned char rgb_enhance_mode;//sw_rgb_enh_sel,dde sel\r
+ \r
+ unsigned char rgb_cg_en;//sw_rgb_con_gam_en\r
+ unsigned int cg_tab[192];\r
+ \r
+ unsigned char rgb_contrast_enhance_mode;//sw_con_gam_order;0 cg prior to dde,1 dde prior to cg\r
+\r
+ int enh_threshold; \r
+ int enh_alpha;\r
+ int enh_radius;\r
+ \r
+ unsigned char scale_up_mode;\r
+\r
+ unsigned char field_order;\r
+ unsigned char dein_mode;\r
+ //DIL HF\r
+ unsigned char dein_high_fre_en;\r
+ unsigned char dein_high_fre_fct;\r
+ //DIL EI\r
+ unsigned char dein_ei_mode;\r
+ unsigned char dein_ei_smooth;\r
+ unsigned char dein_ei_sel;\r
+ unsigned char dein_ei_radius;//when dein_ei_sel=0 will be used\r
+\r
+ bool vir_addr_enable;\r
+ \r
+ void *base;\r
+}\r
+IEP_MSG;\r
+\r
+#endif\r
--- /dev/null
+#include "iep_api.h"\r
+\r
+\r
+\r
+void\r
+iep_set_act_info(iep_img *img, unsigned int w, unsigned int h, unsigned int x_off, unsigned int y_off)\r
+{\r\r
+ img->act_w = w;\r
+ img->act_h = h;\r
+ img->x_off = x_off;\r
+ img->y_off = y_off;\r
+}\r
+\r
+void\r
+iep_set_vir_info(iep_img *img, unsigned int w, unsigned int h, unsigned int *yrgb, unsigned int *uv, unsigned int *v, unsigned int format )\r
+{\r\r
+ img->vir_w = w;\r
+ img->vir_h = h;\r
+ img->mem_addr = yrgb;\r
+ img->uv_addr = uv;\r
+ img->v_addr = v;\r
+ img->format = format;\r
+}\r
+\r
+void \r
+iep_set_scl_up_mode(IEP_MSG *msg, unsigned char mode)\r
+{\r
+ msg->scale_up_mode = mode;\r
+}\r
+\r
+void\r
+iep_set_color_enhance(IEP_MSG *msg, unsigned char color_enh_en,float color_enh_coe)\r
+{\r
+ msg->rgb_color_enhance_en = color_enh_en;\r
+ msg->rgb_enh_coe = color_enh_coe;\r
+\r
+}\r
+\r
+void\r
+iep_rgb_cg(IEP_MSG *msg,unsigned char cg_en,double cg_rr,double cg_rg,double cg_rb)\r
+{\r
+ msg->rgb_cg_en=cg_en;\r
+ msg->cg_rr=cg_rr;\r
+ msg->cg_rg=cg_rg;\r
+ msg->cg_rb=cg_rb;\r
+}\r
+\r
+void\r
+iep_set_deinterlace(IEP_MSG *msg, unsigned char mode, unsigned char dein_high_fre_en, unsigned char dein_edge_interp_en)\r
+{\r
+ msg->dein_mode = mode;\r
+ msg->dein_high_fre_en = dein_high_fre_en;\r
+ msg->dein_ei_mode = dein_edge_interp_en; \r
+}\r
+void\r
+iep_set_dil_ei_smooth(IEP_MSG *msg,unsigned int en)\r
+{\r
+ msg->dein_ei_smooth = en;\r
+}\r
+void\r
+iep_set_dil_ei(IEP_MSG *msg,unsigned char ei_sel,unsigned char ei_radius,unsigned char ei_smooth_en,unsigned char ei_mode)\r
+{\r
+ msg->dein_ei_sel=ei_sel;\r
+ msg->dein_ei_radius=ei_radius;\r
+ msg->dein_ei_smooth=ei_smooth_en;\r
+ msg->dein_ei_mode=ei_mode;\r
+}\r
+void\r
+iep_set_dil_hf(IEP_MSG *msg,unsigned char dil_hf_en,unsigned char dil_hf_fct)\r
+{\r
+ msg->dein_high_fre_en=dil_hf_en;\r
+ msg->dein_high_fre_fct=dil_hf_fct;\r
+}\r
+\r
+void\r
+iep_set_rgb2yuv(IEP_MSG *msg, unsigned char rgb2yuv_mode, unsigned char rgb2yuv_clip_en)\r
+{\r
+ msg->rgb2yuv_mode = rgb2yuv_mode;\r
+ msg->rgb2yuv_clip_en = rgb2yuv_clip_en; \r
+}\r
+\r
+void\r
+iep_set_yuv2rgb(IEP_MSG *msg, unsigned char yuv2rgb_mode, unsigned char yuv2rgb_clip_en)\r
+{\r
+ msg->yuv2rgb_mode = yuv2rgb_mode;\r
+ msg->yuv2rgb_clip_en = yuv2rgb_clip_en; \r
+}\r
+\r
+void\r
+iep_set_dither_up(IEP_MSG *msg,unsigned int en)\r
+{\r
+ msg->dither_up_en = en;\r
+}\r
+\r
+void\r
+iep_set_lcdc_path(IEP_MSG *msg)\r
+{\r
+ msg->lcdc_path_en = 1;\r
+}\r
+\r
+void\r
+iep_set_3D_denoise(IEP_MSG *msg)\r
+{\r
+ msg->yuv_3D_denoise_en = 1;\r
+}\r
+\r
+void\r
+iep_set_yuv_normal_mode_enh(IEP_MSG *msg,float saturation,float contrast,signed char brightness,signed char angle)\r
+{\r
+ msg->yuv_enhance_en = 1;\r
+ msg->video_mode = normal_mode;\r
+ msg->yuv_enh_saturation = saturation;\r
+ msg->yuv_enh_contrast = contrast;\r
+ msg->yuv_enh_brightness = brightness;\r
+ msg->yuv_enh_hue_angle = angle;\r
+}\r
+\r
+void\r
+iep_set_yuv_black_screen(IEP_MSG *msg)\r
+{\r
+ msg->yuv_enhance_en = 1;\r
+ msg->video_mode = black_screen;\r
+}\r
+\r
+void\r
+iep_set_yuv_blue_screen(IEP_MSG *msg)\r
+{\r
+ msg->yuv_enhance_en = 1;\r
+ msg->video_mode = blue_screen;\r
+}\r
+\r
+void\r
+iep_set_yuv_color_bar(IEP_MSG *msg,unsigned char color_bar_y,unsigned char color_bar_u,unsigned char color_bar_v)\r
+{\r
+ msg->yuv_enhance_en = 1;\r
+ msg->video_mode = color_bar;\r
+ msg->color_bar_y = color_bar_y;\r
+ msg->color_bar_u = color_bar_u;\r
+ msg->color_bar_v = color_bar_v;\r
+}\r
+\r
+\r
+\r
--- /dev/null
+#ifndef __IEP_API_H__\r
+#define __IEP_API_H__\r
+\r
+\r
+#include "iep.h"\r
+//#include "../lcdc/hwapi_lcdc.h"\r
+\r
+void\r
+iep_set_act_info(iep_img *img, unsigned int w, unsigned int h, unsigned int x_off, unsigned int y_off);\r
+\r
+void\r
+iep_set_vir_info(iep_img *img, unsigned int w, unsigned int h, unsigned int *yrgb, unsigned int *uv, unsigned int *v, unsigned int format );\r
+\r
+void \r
+iep_set_scl_up_mode(IEP_MSG *msg, unsigned char mode);\r
+\r
+void\r
+iep_set_color_enhance(IEP_MSG *msg, unsigned char color_enh_en,float color_enh_coe);\r
+\r
+void\r
+iep_rgb_cg(IEP_MSG *msg,unsigned char cg_en,double cg_rr,double cg_rg,double cg_rb);\r
+\r
+void\r
+iep_set_deinterlace(IEP_MSG *msg, unsigned char mode, unsigned char dein_high_fre_en, unsigned char dein_edge_interp_en);\r
+\r
+void\r
+iep_set_dil_ei_smooth(IEP_MSG *msg,unsigned int en);\r
+\r
+void\r
+iep_set_rgb2yuv(IEP_MSG *msg, unsigned char rgb2yuv_mode, unsigned char rgb2yuv_clip_en);\r
+\r
+void\r
+iep_set_yuv2rgb(IEP_MSG *msg, unsigned char yuv2rgb_mode, unsigned char yuv2rgb_clip_en);\r
+\r
+void\r
+iep_set_dither_up(IEP_MSG *msg,unsigned int en);\r
+\r
+void\r
+iep_set_lcdc_path(IEP_MSG *msg);\r
+\r
+void\r
+iep_set_3D_denoise(IEP_MSG *msg);\r
+\r
+void\r
+iep_set_yuv_normal_mode_enh(IEP_MSG *msg,float saturation,float contrast,signed char brightness,signed char angle);\r
+\r
+void\r
+iep_set_yuv_black_screen(IEP_MSG *msg);\r
+\r
+void\r
+iep_set_yuv_blue_screen(IEP_MSG *msg);\r
+\r
+void\r
+iep_set_yuv_color_bar(IEP_MSG *msg,unsigned char color_bar_y,unsigned char color_bar_u,unsigned char color_bar_v);\r
+\r
+#endif\r
--- /dev/null
+/* \r
+ * Copyright (C) 2013 ROCKCHIP, Inc.\r
+ *\r
+ * This software is licensed under the terms of the GNU General Public\r
+ * License version 2, as published by the Free Software Foundation, and\r
+ * may be copied, distributed, and modified under those terms.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ * \r
+ */\r
+\r
+#include <linux/clk.h>\r
+#include <linux/delay.h>\r
+#include <linux/slab.h>\r
+#include <linux/fs.h>\r
+#include <linux/sched.h>\r
+#include <linux/uaccess.h>\r
+#include <linux/platform_device.h>\r
+#include <linux/interrupt.h>\r
+#include <linux/kthread.h>\r
+#include <linux/poll.h>\r
+#include <linux/dma-mapping.h>\r
+#include <linux/fb.h>\r
+#include <linux/rk_fb.h>\r
+#include <linux/wakelock.h>\r
+#include <linux/of.h>\r
+#include <linux/io.h>\r
+#include <linux/module.h>\r
+#include <asm/cacheflush.h>\r
+#include "iep_drv.h"\r
+#if defined(CONFIG_IEP_MMU)\r
+#include "iep_mmu.h"\r
+#endif\r
+#include "hw_iep_reg.h"\r
+\r
+#define IEP_MAJOR 255\r
+//#define IEP_CLK_ENABLE\r
+//#define IEP_TEST_CASE\r
+\r
+//#undef dmac_flush_range\r
+//#define dmac_flush_range dma_cache_wback_inv\r
+\r
+#define RK_IEP_SIZE 0x1000\r
+#define IEP_TIMEOUT_DELAY 2*HZ\r
+#define IEP_POWER_OFF_DELAY 4*HZ\r
+\r
+struct iep_drvdata {\r
+ struct miscdevice miscdev;\r
+ struct device dev;\r
+ void *iep_base;\r
+ int irq0;\r
+\r
+ struct clk *aclk_iep;\r
+ struct clk *hclk_iep;\r
+ struct clk *pd_iep;\r
+ struct clk *aclk_vio1;\r
+\r
+ struct mutex mutex; // task list mutex\r
+\r
+ bool dpi_mode; // direct path interface mode. true: enable, false: disable\r
+\r
+ struct delayed_work power_off_work;\r
+ bool enable; // clk enable or disable\r
+ struct wake_lock wake_lock;\r
+\r
+ atomic_t iep_int;\r
+ atomic_t mmu_page_fault;\r
+ atomic_t mmu_bus_error;\r
+};\r
+\r
+struct iep_drvdata *iep_drvdata1 = NULL;\r
+iep_service_info iep_service;\r
+\r
+static void iep_reg_deinit(struct iep_reg *reg)\r
+{\r
+ list_del_init(®->session_link);\r
+ list_del_init(®->status_link);\r
+ kfree(reg);\r
+}\r
+\r
+static void iep_reg_from_wait_to_ready(struct iep_reg *reg)\r
+{\r
+ list_del_init(®->status_link);\r
+ list_add_tail(®->status_link, &iep_service.ready);\r
+\r
+ list_del_init(®->session_link);\r
+ list_add_tail(®->session_link, ®->session->ready);\r
+}\r
+\r
+static void iep_reg_from_ready_to_running(struct iep_reg *reg)\r
+{\r
+ list_del_init(®->status_link);\r
+ list_add_tail(®->status_link, &iep_service.running);\r
+\r
+ list_del_init(®->session_link);\r
+ list_add_tail(®->session_link, ®->session->running);\r
+}\r
+\r
+static void iep_del_running_list(void)\r
+{\r
+ struct iep_reg *reg;\r
+ int cnt = 0;\r
+\r
+ mutex_lock(&iep_service.lock);\r
+\r
+ while (!list_empty(&iep_service.running)) {\r
+ BUG_ON(cnt != 0);\r
+ reg = list_entry(iep_service.running.next, struct iep_reg, status_link);\r
+\r
+ atomic_dec(®->session->task_running);\r
+ atomic_dec(&iep_service.total_running);\r
+\r
+ if (list_empty(®->session->waiting)) {\r
+ atomic_set(®->session->done, 1);\r
+ atomic_inc(®->session->num_done);\r
+ wake_up(®->session->wait);\r
+ }\r
+\r
+ iep_reg_deinit(reg);\r
+ cnt++;\r
+ }\r
+\r
+ mutex_unlock(&iep_service.lock);\r
+}\r
+\r
+static void iep_dump(void)\r
+{\r
+ struct iep_status sts;\r
+\r
+ sts = iep_get_status(iep_drvdata1->iep_base);\r
+\r
+ IEP_INFO("scl_sts: %u, dil_sts %u, wyuv_sts %u, ryuv_sts %u, wrgb_sts %u, rrgb_sts %u, voi_sts %u\n", \r
+ sts.scl_sts, sts.dil_sts, sts.wyuv_sts, sts.ryuv_sts, sts.wrgb_sts, sts.rrgb_sts, sts.voi_sts);\r
+\r
+ {\r
+ int *reg = (int*)iep_drvdata1->iep_base;\r
+ int i;\r
+\r
+ /* could not read validate data from address after base+0x40 */\r
+ for (i=0; i<0x40; i++) {\r
+ IEP_INFO("%08x ", reg[i]);\r
+\r
+ if ((i+1) % 4 == 0) {\r
+ IEP_INFO("\n");\r
+ }\r
+ }\r
+\r
+ IEP_INFO("\n");\r
+ }\r
+}\r
+\r
+/* Caller must hold iep_service.lock */\r
+static void iep_del_running_list_timeout(void)\r
+{\r
+ struct iep_reg *reg;\r
+\r
+ mutex_lock(&iep_service.lock);\r
+\r
+ while (!list_empty(&iep_service.running)) {\r
+ reg = list_entry(iep_service.running.next, struct iep_reg, status_link);\r
+\r
+ atomic_dec(®->session->task_running);\r
+ atomic_dec(&iep_service.total_running);\r
+\r
+ //iep_soft_rst(iep_drvdata1->iep_base);\r
+\r
+ iep_dump();\r
+\r
+ if (list_empty(®->session->waiting)) {\r
+ atomic_set(®->session->done, 1);\r
+ wake_up(®->session->wait);\r
+ }\r
+\r
+ iep_reg_deinit(reg);\r
+ }\r
+\r
+ mutex_unlock(&iep_service.lock);\r
+}\r
+\r
+static inline void iep_queue_power_off_work(void)\r
+{\r
+ queue_delayed_work(system_nrt_wq, &iep_drvdata1->power_off_work, IEP_POWER_OFF_DELAY);\r
+}\r
+\r
+static void iep_power_on(void)\r
+{\r
+ static ktime_t last;\r
+ ktime_t now = ktime_get();\r
+ if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
+ cancel_delayed_work_sync(&iep_drvdata1->power_off_work);\r
+ iep_queue_power_off_work();\r
+ last = now;\r
+ }\r
+\r
+ if (iep_service.enable) return;\r
+\r
+ IEP_INFO("IEP Power ON\n");\r
+\r
+ //iep_soft_rst(iep_drvdata1->iep_base);\r
+\r
+#ifdef IEP_CLK_ENABLE\r
+ //clk_prepare_enable(iep_drvdata1->pd_iep);\r
+ clk_prepare_enable(iep_drvdata1->aclk_iep);\r
+ clk_prepare_enable(iep_drvdata1->hclk_iep);\r
+ //clk_prepare_enable(iep_drvdata1->aclk_vio1);\r
+#endif\r
+\r
+ wake_lock(&iep_drvdata1->wake_lock);\r
+ iep_service.enable = true;\r
+}\r
+\r
+static void iep_power_off(void)\r
+{\r
+ int total_running;\r
+\r
+ if (!iep_service.enable) {\r
+ return;\r
+ }\r
+\r
+ IEP_INFO("IEP Power OFF\n");\r
+\r
+ total_running = atomic_read(&iep_service.total_running);\r
+ if (total_running) {\r
+ IEP_WARNING("power off when %d task running!!\n", total_running);\r
+ mdelay(50);\r
+ IEP_WARNING("delay 50 ms for running task\n");\r
+ iep_dump();\r
+ }\r
+\r
+#ifdef IEP_CLK_ENABLE\r
+ clk_disable_unprepare(iep_drvdata1->aclk_iep);\r
+ clk_disable_unprepare(iep_drvdata1->hclk_iep);\r
+ //clk_disable(iep_drvdata1->pd_iep);\r
+#endif\r
+\r
+ wake_unlock(&iep_drvdata1->wake_lock);\r
+ iep_service.enable = false;\r
+}\r
+\r
+static void iep_power_off_work(struct work_struct *work)\r
+{\r
+ if (mutex_trylock(&iep_service.lock) && !iep_drvdata1->dpi_mode) {\r
+ IEP_INFO("iep dpi mode inactivity\n");\r
+ iep_power_off();\r
+ mutex_unlock(&iep_service.lock);\r
+ } else {\r
+ /* Come back later if the device is busy... */\r
+ iep_queue_power_off_work();\r
+ }\r
+}\r
+\r
+extern void rk_direct_fb_show(struct fb_info * fbi);\r
+extern struct fb_info * rk_get_fb(int fb_id);\r
+extern bool rk_fb_poll_wait_frame_complete(void);\r
+extern int rk_fb_dpi_open(bool open);\r
+extern int rk_fb_dpi_win_sel(int layer_id);\r
+\r
+static void iep_config_lcdc(struct iep_reg *reg)\r
+{\r
+ struct fb_info *fb;\r
+ int fbi = 0;\r
+ int fmt = 0;\r
+\r
+ fbi = reg->layer == 0 ? 0 : 1;\r
+\r
+ rk_fb_dpi_win_sel(fbi);\r
+\r
+ fb = rk_get_fb(fbi);\r
+#if 1\r
+ switch (reg->format) {\r
+ case IEP_FORMAT_ARGB_8888:\r
+ case IEP_FORMAT_ABGR_8888:\r
+ fmt = HAL_PIXEL_FORMAT_RGBA_8888;\r
+ fb->var.bits_per_pixel = 32;\r
+\r
+ fb->var.red.length = 8;\r
+ fb->var.red.offset = 16;\r
+ fb->var.red.msb_right = 0;\r
+\r
+ fb->var.green.length = 8;\r
+ fb->var.green.offset = 8;\r
+ fb->var.green.msb_right = 0;\r
+\r
+ fb->var.blue.length = 8;\r
+ fb->var.blue.offset = 0;\r
+ fb->var.blue.msb_right = 0;\r
+\r
+ fb->var.transp.length = 8;\r
+ fb->var.transp.offset = 24;\r
+ fb->var.transp.msb_right = 0;\r
+\r
+ break;\r
+ case IEP_FORMAT_BGRA_8888:\r
+ fmt = HAL_PIXEL_FORMAT_BGRA_8888;\r
+ fb->var.bits_per_pixel = 32;\r
+ break;\r
+ case IEP_FORMAT_RGB_565:\r
+ fmt = HAL_PIXEL_FORMAT_RGB_565;\r
+ fb->var.bits_per_pixel = 16;\r
+\r
+ fb->var.red.length = 5;\r
+ fb->var.red.offset = 11;\r
+ fb->var.red.msb_right = 0;\r
+\r
+ fb->var.green.length = 6;\r
+ fb->var.green.offset = 5;\r
+ fb->var.green.msb_right = 0;\r
+\r
+ fb->var.blue.length = 5;\r
+ fb->var.blue.offset = 0;\r
+ fb->var.blue.msb_right = 0;\r
+\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_SP:\r
+ fmt = HAL_PIXEL_FORMAT_YCbCr_422_SP;\r
+ fb->var.bits_per_pixel = 16;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_420_SP:\r
+ fmt = HAL_PIXEL_FORMAT_YCrCb_NV12;\r
+ fb->var.bits_per_pixel = 16;\r
+ break;\r
+ case IEP_FORMAT_YCbCr_422_P:\r
+ case IEP_FORMAT_YCrCb_422_SP:\r
+ case IEP_FORMAT_YCrCb_422_P:\r
+ case IEP_FORMAT_YCrCb_420_SP:\r
+ case IEP_FORMAT_YCbCr_420_P:\r
+ case IEP_FORMAT_YCrCb_420_P:\r
+ case IEP_FORMAT_RGBA_8888:\r
+ case IEP_FORMAT_BGR_565:\r
+ // unsupported format\r
+ IEP_ERR("unsupported format %d\n", reg->format);\r
+ break;\r
+ default:\r
+ ;\r
+ }\r
+\r
+ fb->var.xoffset = 0;\r
+ fb->var.yoffset = 0;\r
+ fb->var.xres = reg->act_width;\r
+ fb->var.yres = reg->act_height;\r
+ fb->var.xres_virtual = reg->act_width;\r
+ fb->var.yres_virtual = reg->act_height;\r
+ fb->var.nonstd = ((reg->off_y&0xFFF)<<20) + ((reg->off_x&0xFFF)<<8) + (fmt&0xFF);\r
+ fb->var.grayscale = ((reg->vir_height&0xFFF)<<20) + ((reg->vir_width&0xFFF)<<8) + 0; //win0 xsize & ysize\r
+#endif\r
+ rk_direct_fb_show(fb);\r
+}\r
+\r
+static int iep_switch_dpi(struct iep_reg *reg) \r
+{\r
+ if (reg->dpi_en) {\r
+ if (!iep_drvdata1->dpi_mode) {\r
+ /// Turn on dpi\r
+ rk_fb_dpi_open(true);\r
+ iep_drvdata1->dpi_mode = true;\r
+ }\r
+ iep_config_lcdc(reg);\r
+ } else {\r
+ if (iep_drvdata1->dpi_mode) {\r
+ /// Turn off dpi\r
+ //wait_lcdc_dpi_close();\r
+ bool status;\r
+ rk_fb_dpi_open(false);\r
+ status = rk_fb_poll_wait_frame_complete();\r
+\r
+ iep_drvdata1->dpi_mode = false;\r
+ IEP_INFO("%s %d, iep dpi inactivated\n", __func__, __LINE__);\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+static void iep_reg_copy_to_hw(struct iep_reg *reg)\r
+{\r
+ int i;\r
+\r
+ uint32_t *pbase = (uint32_t *)iep_drvdata1->iep_base;\r
+\r
+ // config registers\r
+ for (i=0; i<IEP_CNF_REG_LEN; i++) {\r
+ pbase[IEP_CNF_REG_BASE + i] = reg->reg[IEP_CNF_REG_BASE + i];\r
+ }\r
+\r
+ // command registers\r
+ for (i = 0; i < IEP_CMD_REG_LEN; i++) {\r
+ pbase[IEP_CMD_REG_BASE + i] = reg->reg[IEP_CMD_REG_BASE + i];\r
+ }\r
+\r
+ // address registers\r
+ for (i=0; i<IEP_ADD_REG_LEN; i++) {\r
+ pbase[IEP_ADD_REG_BASE + i] = reg->reg[IEP_ADD_REG_BASE + i];\r
+ }\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+ // mmu registers\r
+ for (i=0; i<IEP_MMU_REG_LEN; i++) {\r
+ pbase[IEP_MMU_REG_BASE + i] = reg->reg[IEP_MMU_REG_BASE + i];\r
+ }\r
+#endif\r
+\r
+ //dmac_flush_range(&pbase[0], &pbase[IEP_REG_LEN]);\r
+ //outer_flush_range(virt_to_phys(&pbase[0]),virt_to_phys(&pbase[IEP_REG_LEN]));\r
+\r
+ dsb();\r
+}\r
+\r
+/** switch fields order before the next lcdc frame start\r
+ * coming */\r
+static void iep_switch_fields_order(void) \r
+{\r
+ void *pbase = (void*)iep_drvdata1->iep_base;\r
+ int mode = iep_get_deinterlace_mode(pbase);\r
+ struct fb_info *fb;\r
+\r
+ switch (mode) {\r
+ case dein_mode_I4O1B:\r
+ iep_set_deinterlace_mode(dein_mode_I4O1T, pbase);\r
+ break;\r
+ case dein_mode_I4O1T:\r
+ iep_set_deinterlace_mode(dein_mode_I4O1B, pbase);\r
+ break;\r
+ case dein_mode_I2O1B:\r
+ iep_set_deinterlace_mode(dein_mode_I2O1T, pbase);\r
+ break;\r
+ case dein_mode_I2O1T:\r
+ iep_set_deinterlace_mode(dein_mode_I2O1B, pbase);\r
+ break;\r
+ default:\r
+ ;\r
+ }\r
+\r
+ fb = rk_get_fb(1);\r
+ rk_direct_fb_show(fb);\r
+\r
+ //iep_switch_input_address(pbase);\r
+}\r
+\r
+/* Caller must hold iep_service.lock */\r
+static void iep_try_set_reg(void)\r
+{\r
+ struct iep_reg *reg;\r
+\r
+ mutex_lock(&iep_service.lock);\r
+\r
+ if (list_empty(&iep_service.ready)) {\r
+ if (!list_empty(&iep_service.waiting)) {\r
+ reg = list_entry(iep_service.waiting.next, struct iep_reg, status_link);\r
+\r
+ iep_power_on();\r
+ udelay(1);\r
+\r
+ iep_reg_from_wait_to_ready(reg);\r
+ atomic_dec(&iep_service.waitcnt);\r
+\r
+ //iep_soft_rst(iep_drvdata1->iep_base);\r
+\r
+ iep_reg_copy_to_hw(reg);\r
+ }\r
+ } else {\r
+ if (iep_drvdata1->dpi_mode) {\r
+ iep_switch_fields_order();\r
+ }\r
+ }\r
+\r
+ mutex_unlock(&iep_service.lock);\r
+}\r
+\r
+static void iep_try_start_frm(void)\r
+{\r
+ struct iep_reg *reg;\r
+\r
+ mutex_lock(&iep_service.lock);\r
+\r
+ if (list_empty(&iep_service.running)) {\r
+ if (!list_empty(&iep_service.ready)) {\r
+ reg = list_entry(iep_service.ready.next, struct iep_reg, status_link);\r
+\r
+ iep_switch_dpi(reg);\r
+\r
+ iep_reg_from_ready_to_running(reg);\r
+ iep_config_frame_end_int_en(iep_drvdata1->iep_base);\r
+ iep_config_done(iep_drvdata1->iep_base);\r
+\r
+ /* Start proc */\r
+ atomic_inc(®->session->task_running);\r
+ atomic_inc(&iep_service.total_running);\r
+ iep_config_frm_start(iep_drvdata1->iep_base);\r
+ }\r
+ }\r
+\r
+ mutex_unlock(&iep_service.lock);\r
+}\r
+\r
+static irqreturn_t iep_isr(int irq, void *dev_id)\r
+{\r
+ if (atomic_read(&iep_drvdata1->iep_int) > 0) {\r
+ if (iep_service.enable) {\r
+ if (list_empty(&iep_service.waiting)) {\r
+ if (iep_drvdata1->dpi_mode) {\r
+ iep_switch_fields_order();\r
+ }\r
+ }\r
+ iep_del_running_list();\r
+ }\r
+\r
+ iep_try_set_reg();\r
+ iep_try_start_frm();\r
+\r
+ atomic_dec(&iep_drvdata1->iep_int);\r
+ }\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+ if (atomic_read(&iep_drvdata1->mmu_page_fault) > 0) {\r
+\r
+ if (!list_empty(&iep_service.running)) {\r
+ uint32_t va = iep_probe_mmu_page_fault_addr(iep_drvdata1->iep_base);\r
+ struct iep_reg *reg = list_entry(iep_service.running.next, struct iep_reg, status_link);\r
+ if (0 > rk_mmu_generate_pte_from_va(reg->session, va)) {\r
+ IEP_ERR("Generate PTE from Virtual Address 0x%08x failed\n", va);\r
+ } else {\r
+ iep_config_mmu_cmd(iep_drvdata1->iep_base, MMU_ZAP_CACHE);\r
+ iep_config_mmu_cmd(iep_drvdata1->iep_base, MMU_PAGE_FAULT_DONE);\r
+ }\r
+ } else {\r
+ IEP_ERR("Page Fault occur when IEP IDLE\n");\r
+ }\r
+\r
+ atomic_dec(&iep_drvdata1->mmu_page_fault);\r
+ }\r
+\r
+ if (atomic_read(&iep_drvdata1->mmu_bus_error) > 0) {\r
+ // reset iep mmu module\r
+ IEP_ERR("Bus Error!!!\n");\r
+ iep_config_mmu_cmd(iep_drvdata1->iep_base, MMU_FORCE_RESET);\r
+ atomic_dec(&iep_drvdata1->mmu_bus_error);\r
+ }\r
+#endif\r
+\r
+ return IRQ_HANDLED;\r
+}\r
+\r
+static irqreturn_t iep_irq(int irq, void *dev_id)\r
+{\r
+ /*clear INT */\r
+ void *pbase = (void*)iep_drvdata1->iep_base;\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+ struct iep_mmu_int_status mmu_int_status;\r
+\r
+ mmu_int_status = iep_probe_mmu_int_status(pbase);\r
+ if (mmu_int_status.page_fault) {\r
+ iep_config_mmu_page_fault_int_clr(pbase);\r
+ atomic_inc(&iep_drvdata1->mmu_page_fault);\r
+ }\r
+\r
+ if (mmu_int_status.read_bus_error) {\r
+ iep_config_mmu_read_bus_error_int_clr(pbase);\r
+ atomic_inc(&iep_drvdata1->mmu_bus_error);\r
+ }\r
+#endif\r
+ \r
+ if (iep_probe_int(pbase)) {\r
+ iep_config_frame_end_int_clr(pbase);\r
+ atomic_inc(&iep_drvdata1->iep_int);\r
+ }\r
+\r
+ return IRQ_WAKE_THREAD;\r
+}\r
+\r
+static void iep_service_session_clear(iep_session *session)\r
+{\r
+ struct iep_reg *reg, *n;\r
+\r
+ list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
+ iep_reg_deinit(reg);\r
+ }\r
+\r
+ list_for_each_entry_safe(reg, n, &session->ready, session_link) {\r
+ iep_reg_deinit(reg);\r
+ }\r
+\r
+ list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
+ iep_reg_deinit(reg);\r
+ }\r
+}\r
+\r
+static int iep_open(struct inode *inode, struct file *filp)\r
+{\r
+ //DECLARE_WAITQUEUE(wait, current);\r
+ iep_session *session = (iep_session *)kzalloc(sizeof(iep_session), GFP_KERNEL);\r
+ if (NULL == session) {\r
+ IEP_ERR("unable to allocate memory for iep_session.\n");\r
+ return -ENOMEM;\r
+ }\r
+\r
+ session->pid = current->pid;\r
+ INIT_LIST_HEAD(&session->waiting);\r
+ INIT_LIST_HEAD(&session->ready);\r
+ INIT_LIST_HEAD(&session->running);\r
+ INIT_LIST_HEAD(&session->list_session);\r
+ init_waitqueue_head(&session->wait);\r
+ //add_wait_queue(&session->wait, wait);\r
+ /* no need to protect */\r
+ mutex_lock(&iep_service.lock);\r
+ list_add_tail(&session->list_session, &iep_service.session);\r
+ mutex_unlock(&iep_service.lock);\r
+ atomic_set(&session->task_running, 0);\r
+ atomic_set(&session->num_done, 0);\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+ rk_mmu_init_dte_table(session);\r
+ INIT_LIST_HEAD(&session->pte_list);\r
+#endif\r
+\r
+ filp->private_data = (void *)session;\r
+\r
+ return nonseekable_open(inode, filp);\r
+}\r
+\r
+static int iep_release(struct inode *inode, struct file *filp)\r
+{\r
+ int task_running;\r
+ iep_session *session = (iep_session *)filp->private_data;\r
+\r
+ if (NULL == session) return -EINVAL;\r
+\r
+ task_running = atomic_read(&session->task_running);\r
+\r
+ if (task_running) {\r
+ IEP_ERR("iep_service session %d still has %d task running when closing\n", session->pid, task_running);\r
+ msleep(100);\r
+ /*synchronization*/\r
+ }\r
+\r
+ wake_up(&session->wait);\r
+ mutex_lock(&iep_service.lock);\r
+ list_del(&session->list_session);\r
+ iep_service_session_clear(session);\r
+ kfree(session);\r
+ mutex_unlock(&iep_service.lock);\r
+\r
+ return 0;\r
+}\r
+\r
+static unsigned int iep_poll(struct file *filp, poll_table *wait)\r
+{\r
+ int mask = 0;\r
+ iep_session *session = (iep_session *)filp->private_data;\r
+ if (NULL == session) return POLL_ERR;\r
+ poll_wait(filp, &session->wait, wait);\r
+ if (atomic_read(&session->done)) mask |= POLL_IN | POLLRDNORM;\r
+\r
+ return mask;\r
+}\r
+\r
+static int iep_get_result_sync(iep_session *session)\r
+{\r
+ int ret = 0;\r
+\r
+ iep_try_start_frm();\r
+\r
+ ret = wait_event_timeout(session->wait, atomic_read(&session->done), IEP_TIMEOUT_DELAY);\r
+\r
+ if (unlikely(ret < 0)) {\r
+ IEP_ERR("sync pid %d wait task ret %d\n", session->pid, ret);\r
+ iep_del_running_list();\r
+ ret = ret;\r
+ } else if (0 == ret) {\r
+ IEP_ERR("sync pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
+ iep_del_running_list_timeout();\r
+ iep_try_set_reg();\r
+ iep_try_start_frm();\r
+ ret = -ETIMEDOUT;\r
+ }\r
+\r
+ return ret;\r
+}\r
+\r
+static void iep_get_result_async(iep_session *session)\r
+{\r
+ iep_try_start_frm();\r
+ return;\r
+}\r
+\r
+static long iep_ioctl(struct file *filp, uint32_t cmd, unsigned long arg)\r
+{\r
+ int ret = 0;\r
+ iep_session *session = (iep_session *)filp->private_data;\r
+\r
+ if (NULL == session) {\r
+ IEP_ERR("%s [%d] iep thread session is null\n", __FUNCTION__, __LINE__);\r
+ return -EINVAL;\r
+ }\r
+\r
+ mutex_lock(&iep_service.mutex);\r
+\r
+ switch (cmd) {\r
+ case IEP_SET_PARAMETER:\r
+ {\r
+ IEP_MSG *msg = (IEP_MSG *)kzalloc(sizeof(IEP_MSG), GFP_KERNEL);\r
+ if (msg) {\r
+ if (copy_from_user(msg, (IEP_MSG *)arg, sizeof(IEP_MSG))) {\r
+ IEP_ERR("copy_from_user failure\n");\r
+ ret = -EFAULT;\r
+ }\r
+ }\r
+ \r
+ if (ret == 0) {\r
+ if (atomic_read(&iep_service.waitcnt) < 10) {\r
+ iep_config(session, msg);\r
+ atomic_inc(&iep_service.waitcnt);\r
+ } else {\r
+ IEP_ERR("iep task queue full\n");\r
+ ret = -EFAULT;\r
+ }\r
+ }\r
+\r
+ /** REGISTER CONFIG must accord to Timing When DPI mode\r
+ * enable */\r
+ if (!iep_drvdata1->dpi_mode) {\r
+ iep_try_set_reg();\r
+ }\r
+ kfree(msg);\r
+ }\r
+ break;\r
+ case IEP_GET_RESULT_SYNC:\r
+ if (0 > iep_get_result_sync(session)) {\r
+ ret = -ETIMEDOUT;\r
+ }\r
+ break;\r
+ case IEP_GET_RESULT_ASYNC:\r
+ iep_get_result_async(session);\r
+ break;\r
+ case IEP_RELEASE_CURRENT_TASK:\r
+ iep_del_running_list_timeout();\r
+ iep_try_set_reg();\r
+ iep_try_start_frm();\r
+ break;\r
+ default:\r
+ IEP_ERR("unknown ioctl cmd!\n");\r
+ ret = -EINVAL;\r
+ }\r
+ mutex_unlock(&iep_service.mutex);\r
+\r
+ return ret;\r
+}\r
+\r
+struct file_operations iep_fops = {\r
+ .owner = THIS_MODULE,\r
+ .open = iep_open,\r
+ .release = iep_release,\r
+ .poll = iep_poll,\r
+ .unlocked_ioctl = iep_ioctl,\r
+};\r
+\r
+static struct miscdevice iep_dev = {\r
+ .minor = IEP_MAJOR,\r
+ .name = "iep",\r
+ .fops = &iep_fops,\r
+};\r
+\r
+static int iep_drv_probe(struct platform_device *pdev)\r
+{\r
+ struct iep_drvdata *data;\r
+ int ret = 0;\r
+ struct resource *res = NULL;\r
+\r
+ data = (struct iep_drvdata*)devm_kzalloc(&pdev->dev, sizeof(struct iep_drvdata), GFP_KERNEL);\r
+ if (NULL == data) {\r
+ IEP_ERR("failed to allocate driver data.\n");\r
+ return -ENOMEM;\r
+ }\r
+\r
+ iep_drvdata1 = data;\r
+\r
+ INIT_LIST_HEAD(&iep_service.waiting);\r
+ INIT_LIST_HEAD(&iep_service.ready);\r
+ INIT_LIST_HEAD(&iep_service.running);\r
+ INIT_LIST_HEAD(&iep_service.done);\r
+ INIT_LIST_HEAD(&iep_service.session);\r
+ atomic_set(&iep_service.waitcnt, 0);\r
+ mutex_init(&iep_service.lock);\r
+ atomic_set(&iep_service.total_running, 0);\r
+ iep_service.enable = false;\r
+\r
+#ifdef IEP_CLK_ENABLE\r
+ /*data->pd_iep = clk_get(NULL, "pd_display");\r
+ if (IS_ERR(data->pd_iep)) {\r
+ IEP_ERR("failed to find iep power down clock source.\n");\r
+ goto err_clock;\r
+ }*/\r
+\r
+ data->aclk_iep = devm_clk_get(&pdev->dev, "aclk_iep");\r
+ if (IS_ERR(data->aclk_iep)) {\r
+ IEP_ERR("failed to find iep axi clock source.\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ data->hclk_iep = devm_clk_get(&pdev->dev, "hclk_iep");\r
+ if (IS_ERR(data->hclk_iep)) {\r
+ IEP_ERR("failed to find iep ahb clock source.\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }\r
+\r
+ /*data->aclk_vio1 = clk_get(NULL, "aclk_lcdc1_pre");\r
+ if (IS_ERR(data->aclk_vio1)) {\r
+ IEP_ERR("failed to find vio1 axi clock source.\n");\r
+ ret = -ENOENT;\r
+ goto err_clock;\r
+ }*/\r
+#endif\r
+\r
+ iep_service.enable = false;\r
+ INIT_DELAYED_WORK(&data->power_off_work, iep_power_off_work);\r
+ wake_lock_init(&data->wake_lock, WAKE_LOCK_SUSPEND, "iep");\r
+\r
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
+\r
+ data->iep_base = (void *)devm_ioremap_resource(&pdev->dev, res);\r
+ if (data->iep_base == NULL) {\r
+ IEP_ERR("iep ioremap failed\n");\r
+ ret = -ENOENT;\r
+ goto err_ioremap;\r
+ }\r
+\r
+ atomic_set(&data->iep_int, 0);\r
+ atomic_set(&data->mmu_page_fault, 0);\r
+ atomic_set(&data->mmu_bus_error, 0);\r
+\r
+ /* get the IRQ */\r
+ data->irq0 = platform_get_irq(pdev, 0);\r
+ if (data->irq0 <= 0) {\r
+ IEP_ERR("failed to get iep irq resource (%d).\n", data->irq0);\r
+ ret = data->irq0;\r
+ goto err_irq;\r
+ }\r
+\r
+ /* request the IRQ */\r
+ ret = devm_request_threaded_irq(&pdev->dev, data->irq0, iep_irq, iep_isr, 0, dev_name(&pdev->dev), pdev);\r
+ if (ret) {\r
+ IEP_ERR("iep request_irq failed (%d).\n", ret);\r
+ goto err_irq;\r
+ }\r
+\r
+ mutex_init(&iep_service.mutex);\r
+\r
+ platform_set_drvdata(pdev, data);\r
+\r
+ ret = misc_register(&iep_dev);\r
+ if (ret) {\r
+ IEP_ERR("cannot register miscdev (%d)\n", ret);\r
+ goto err_misc_register;\r
+ }\r
+\r
+ IEP_INFO("IEP Driver loaded succesfully\n");\r
+\r
+ return 0;\r
+\r
+err_misc_register:\r
+ free_irq(data->irq0, pdev);\r
+err_irq:\r
+ if (res) {\r
+ if (data->iep_base) {\r
+ devm_ioremap_release(&pdev->dev, res);\r
+ }\r
+ devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
+ }\r
+err_ioremap:\r
+err_clock:\r
+ wake_lock_destroy(&data->wake_lock);\r
+ kfree(data);\r
+\r
+ return ret;\r
+}\r
+\r
+static int iep_drv_remove(struct platform_device *pdev)\r
+{\r
+ struct iep_drvdata *data = platform_get_drvdata(pdev);\r
+ struct resource *res;\r
+\r
+ wake_lock_destroy(&data->wake_lock);\r
+\r
+ misc_deregister(&(data->miscdev));\r
+ free_irq(data->irq0, &data->miscdev);\r
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
+ devm_ioremap_release(&pdev->dev, res);\r
+ devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
+\r
+#ifdef IEP_CLK_ENABLE\r
+ if (data->aclk_iep) {\r
+ devm_clk_put(&pdev->dev, data->aclk_iep);\r
+ }\r
+\r
+ if (data->hclk_iep) {\r
+ devm_clk_put(&pdev->dev, data->hclk_iep);\r
+ }\r
+\r
+ /*if (data->aclk_vio1) {\r
+ clk_put(data->aclk_vio1);\r
+ }\r
+\r
+ if (data->pd_iep) {\r
+ clk_put(data->pd_iep);\r
+ }*/\r
+#endif\r
+\r
+ //devm_kfree(data);\r
+ return 0;\r
+}\r
+\r
+#if defined(CONFIG_OF)\r
+static const struct of_device_id iep_dt_ids[] = {\r
+ {.compatible = "rockchip,iep",},\r
+ {},\r
+};\r
+#endif\r
+\r
+static struct platform_driver iep_driver = {\r
+ .probe = iep_drv_probe,\r
+ .remove = iep_drv_remove,\r
+ .driver = {\r
+ .owner = THIS_MODULE,\r
+ .name = "iep",\r
+#if defined(CONFIG_OF)\r
+ .of_match_table = of_match_ptr(iep_dt_ids),\r
+#endif\r
+ },\r
+};\r
+\r
+#ifdef CONFIG_PROC_FS\r
+#include <linux/proc_fs.h>\r
+#include <linux/seq_file.h>\r
+\r
+static int proc_iep_show(struct seq_file *s, void *v)\r
+{\r
+ struct iep_status sts;\r
+ //mutex_lock(&iep_service.mutex);\r
+ iep_power_on();\r
+ seq_printf(s, "\nIEP Modules Status:\n");\r
+ sts = iep_get_status(iep_drvdata1->iep_base);\r
+ seq_printf(s, "scl_sts: %u, dil_sts %u, wyuv_sts %u, ryuv_sts %u, wrgb_sts %u, rrgb_sts %u, voi_sts %u\n", \r
+ sts.scl_sts, sts.dil_sts, sts.wyuv_sts, sts.ryuv_sts, sts.wrgb_sts, sts.rrgb_sts, sts.voi_sts);\r
+ {\r
+ int *reg = (int*)iep_drvdata1->iep_base;\r
+ int i;\r
+\r
+ /* could not read validate data from address after base+0x40 */\r
+ for (i=0; i<0x40; i++) {\r
+ seq_printf(s, "%08x ", reg[i]);\r
+\r
+ if ((i+1) % 4 == 0) {\r
+ seq_printf(s, "\n");\r
+ }\r
+ }\r
+\r
+ seq_printf(s, "\n");\r
+ }\r
+\r
+ //mutex_unlock(&iep_service.mutex);\r
+\r
+ return 0;\r
+}\r
+\r
+static int proc_iep_open(struct inode *inode, struct file *file)\r
+{\r
+ return single_open(file, proc_iep_show, NULL);\r
+}\r
+\r
+static const struct file_operations proc_iep_fops = {\r
+ .open = proc_iep_open,\r
+ .read = seq_read,\r
+ .llseek = seq_lseek,\r
+ .release = single_release,\r
+};\r
+\r
+static int __init iep_proc_init(void)\r
+{\r
+ proc_create("iep", 0, NULL, &proc_iep_fops);\r
+ return 0;\r
+}\r
+\r
+static void __exit iep_proc_release(void)\r
+{\r
+ remove_proc_entry("iep", NULL);\r
+}\r
+#endif\r
+\r
+#ifdef IEP_TEST_CASE\r
+void iep_test_case0(void);\r
+#endif\r
+\r
+static int __init iep_init(void)\r
+{\r
+ int ret;\r
+\r
+ if ((ret = platform_driver_register(&iep_driver)) != 0) {\r
+ IEP_ERR("Platform device register failed (%d).\n", ret);\r
+ return ret;\r
+ }\r
+\r
+#ifdef CONFIG_PROC_FS\r
+ iep_proc_init();\r
+#endif\r
+\r
+ IEP_INFO("Module initialized.\n");\r
+\r
+#ifdef IEP_TEST_CASE\r
+ iep_test_case0();\r
+#endif\r
+\r
+ return 0;\r
+}\r
+\r
+static void __exit iep_exit(void)\r
+{\r
+ IEP_ERR("%s IN\n", __func__);\r
+#ifdef CONFIG_PROC_FS\r
+ iep_proc_release();\r
+#endif\r
+\r
+ iep_power_off();\r
+ platform_driver_unregister(&iep_driver);\r
+}\r
+\r
+module_init(iep_init);\r
+module_exit(iep_exit);\r
+\r
+/* Module information */\r
+MODULE_AUTHOR("ljf@rock-chips.com");\r
+MODULE_DESCRIPTION("Driver for iep device");\r
+MODULE_LICENSE("GPL");\r
+\r
+#ifdef IEP_TEST_CASE\r
+\r
+#include "yuv420sp_480x480_interlaced.h"\r
+#include "yuv420sp_480x480_deinterlaced_i2o1.h"\r
+\r
+//unsigned char tmp_buf[480*480*3/2];\r
+\r
+void iep_test_case0(void)\r
+{\r
+ struct IEP_MSG msg;\r
+ iep_session session;\r
+ unsigned int phy_src, phy_dst, phy_tmp;\r
+ int i;\r
+ int ret = 0;\r
+ unsigned char *tmp_buf;\r
+\r
+ tmp_buf = kmalloc(480*480*3/2, GFP_KERNEL);\r
+ \r
+ session.pid = current->pid;\r
+ INIT_LIST_HEAD(&session.waiting);\r
+ INIT_LIST_HEAD(&session.ready);\r
+ INIT_LIST_HEAD(&session.running);\r
+ INIT_LIST_HEAD(&session.list_session);\r
+ init_waitqueue_head(&session.wait);\r
+ list_add_tail(&session.list_session, &iep_service.session);\r
+ atomic_set(&session.task_running, 0);\r
+ atomic_set(&session.num_done, 0);\r
+\r
+ memset(&msg, 0, sizeof(struct IEP_MSG));\r
+ memset(tmp_buf, 0xCC, 480*480*3/2);\r
+\r
+ dmac_flush_range(&tmp_buf[0], &tmp_buf[480*480*3/2]);\r
+ outer_flush_range(virt_to_phys(&tmp_buf[0]),virt_to_phys(&tmp_buf[480*480*3/2]));\r
+\r
+ phy_src = virt_to_phys(&yuv420sp_480x480_interlaced[0]);\r
+ phy_tmp = virt_to_phys(&tmp_buf[0]);\r
+ phy_dst = virt_to_phys(&yuv420sp_480x480_deinterlaced_i2o1[0]);\r
+\r
+ dmac_flush_range(&yuv420sp_480x480_interlaced[0], &yuv420sp_480x480_interlaced[480*480*3/2]);\r
+ outer_flush_range(virt_to_phys(&yuv420sp_480x480_interlaced[0]),virt_to_phys(&yuv420sp_480x480_interlaced[480*480*3/2]));\r
+\r
+ IEP_INFO("*********** IEP MSG GENARATE ************\n");\r
+\r
+ msg.src.act_w = 480;\r
+ msg.src.act_h = 480;\r
+ msg.src.x_off = 0;\r
+ msg.src.y_off = 0;\r
+ msg.src.vir_w = 480;\r
+ msg.src.vir_h = 480;\r
+ msg.src.format = IEP_FORMAT_YCbCr_420_SP;\r
+ msg.src.mem_addr = (uint32_t*)phy_src;\r
+ msg.src.uv_addr = (uint32_t*)(phy_src + 480 * 480);\r
+ msg.src.v_addr = 0;\r
+ \r
+ msg.dst.act_w = 480;\r
+ msg.dst.act_h = 480;\r
+ msg.dst.x_off = 0;\r
+ msg.dst.y_off = 0;\r
+ msg.dst.vir_w = 480;\r
+ msg.dst.vir_h = 480;\r
+ msg.dst.format = IEP_FORMAT_YCbCr_420_SP;\r
+ msg.dst.mem_addr = (uint32_t*)phy_tmp;\r
+ msg.dst.uv_addr = (uint32_t*)(phy_tmp + 480 * 480);\r
+ msg.dst.v_addr = 0;\r
+\r
+ msg.dein_mode = IEP_DEINTERLACE_MODE_I2O1;\r
+ msg.field_order = FIELD_ORDER_BOTTOM_FIRST;\r
+ \r
+ IEP_INFO("*********** IEP TEST CASE 0 ************\n");\r
+\r
+ iep_config(&session, &msg);\r
+ iep_try_set_reg();\r
+ if (0 > iep_get_result_sync(&session)) {\r
+ IEP_INFO("%s failed, timeout\n", __func__);\r
+ ret = -ETIMEDOUT;\r
+ }\r
+\r
+ mdelay(10);\r
+\r
+ dmac_flush_range(&tmp_buf[0], &tmp_buf[480*480*3/2]);\r
+ outer_flush_range(virt_to_phys(&tmp_buf[0]),virt_to_phys(&tmp_buf[480*480*3/2]));\r
+\r
+ IEP_INFO("*********** RESULT CHECKING ************\n");\r
+\r
+ for (i=0; i<480*480*3/2; i++) {\r
+ if (tmp_buf[i] != yuv420sp_480x480_deinterlaced_i2o1[i]) {\r
+ IEP_INFO("diff occur position %d, 0x%02x 0x%02x\n", i, tmp_buf[i], yuv420sp_480x480_deinterlaced_i2o1[i]);\r
+\r
+ if (i > 10) {\r
+ iep_dump();\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (i == 480*480*3/2) {\r
+ IEP_INFO("IEP pass the checking\n");\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+#ifndef IEP_DRV_H_\r
+#define IEP_DRV_H_\r
+\r
+#include <linux/device.h>\r
+#include <linux/miscdevice.h>\r
+#include <linux/mutex.h>\r
+#include "iep.h"\r
+\r
+#define IEP_REG_LEN 0x100\r
+#define IEP_CMD_REG_LEN 0xE\r
+#define IEP_ADD_REG_LEN 0xE0\r
+#define IEP_RAW_REG_LEN 0xA\r
+#define IEP_SYS_REG_LEN 0x6\r
+#define IEP_CNF_REG_LEN 0x2\r
+\r
+#define IEP_CNF_REG_BASE 0x0\r
+#define IEP_SYS_REG_BASE 0x2\r
+#define IEP_CMD_REG_BASE 0x8\r
+#define IEP_ADD_REG_BASE 0x20\r
+#define IEP_RAW_REG_BASE 0x16\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+#define IEP_MMU_REG_BASE 0x200\r
+#define IEP_MMU_REG_LEN 0xA\r
+#endif\r
+\r
+struct iep_parameter_req {\r
+ iep_img src;\r
+ iep_img dst;\r
+};\r
+\r
+struct iep_parameter_deinterlace {\r
+ iep_img src1;\r
+ iep_img dst1;\r
+\r
+ iep_img src_itemp;\r
+ iep_img src_ftemp;\r
+\r
+ iep_img dst_itemp;\r
+ iep_img dst_ftemp;\r
+\r
+ u8 dein_mode;\r
+\r
+ // deinterlace high frequency\r
+ u8 dein_high_fre_en;\r
+ u8 dein_high_fre_fct;\r
+\r
+ // deinterlace edge interpolation\r
+ u8 dein_ei_mode;\r
+ u8 dein_ei_smooth;\r
+ u8 dein_ei_sel;\r
+ u8 dein_ei_radius;\r
+};\r
+\r
+struct iep_parameter_enhance {\r
+ u8 yuv_3D_denoise_en;\r
+\r
+ u8 yuv_enhance_en;\r
+ float yuv_enh_saturation; //0-1.992\r
+ float yuv_enh_contrast; //0-1.992\r
+ s8 yuv_enh_brightness; //-32<brightness<31\r
+ s8 yuv_enh_hue_angle; //0-30¡ã£¬value is 0 - 30\r
+\r
+ u8 video_mode; //0-3\r
+ u8 color_bar_y; //0-127\r
+ u8 color_bar_u; //0-127\r
+ u8 color_bar_v; //0-127\r
+\r
+ u8 rgb_enhance_en;\r
+\r
+ u8 rgb_cg_en; //sw_rgb_con_gam_en\r
+ double cg_rr;\r
+ double cg_rg;\r
+ double cg_rb;\r
+ u8 rgb_color_enhance_en; //sw_rgb_color_enh_en\r
+ float rgb_enh_coe; //0-3.96875\r
+};\r
+\r
+struct iep_parameter_scale {\r
+ u8 scale_up_mode;\r
+};\r
+\r
+struct iep_parameter_convert {\r
+ u8 dither_up_en;\r
+ u8 dither_down_en; //not to be used\r
+\r
+ u8 yuv2rgb_mode;\r
+ u8 rgb2yuv_mode;\r
+\r
+ u8 global_alpha_value;\r
+\r
+ u8 rgb2yuv_clip_en;\r
+ u8 yuv2rgb_clip_en;\r
+};\r
+\r
+typedef struct iep_session {\r
+ /* a linked list of data so we can access them for debugging */\r
+ struct list_head list_session;\r
+ /* a linked list of register data waiting for process */\r
+ struct list_head waiting;\r
+ /* a linked list of register data in ready */\r
+ struct list_head ready;\r
+ /* a linked list of register data in processing */\r
+ struct list_head running;\r
+ /* all coommand this thread done */\r
+ atomic_t done;\r
+ wait_queue_head_t wait;\r
+ pid_t pid;\r
+ atomic_t task_running;\r
+ atomic_t num_done;\r
+\r
+#if defined(CONFIG_IEP_MMU)\r
+ uint32_t* dte_table;\r
+ struct list_head pte_list;\r
+ struct task_struct *tsk;\r
+#endif\r
+} iep_session;\r
+\r
+typedef struct iep_service_info {\r
+ struct mutex lock;\r
+ struct timer_list timer; /* timer for power off */\r
+ struct list_head waiting; /* link to link_reg in struct iep_reg */\r
+ atomic_t waitcnt;\r
+ struct list_head ready; /* link to link_reg in struct iep_reg */\r
+ struct list_head running; /* link to link_reg in struct iep_reg */\r
+ struct list_head done; /* link to link_reg in struct iep_reg */\r
+ struct list_head session; /* link to list_session in struct vpu_session */\r
+ atomic_t total_running;\r
+\r
+ struct iep_reg *reg;\r
+ bool enable;\r
+\r
+ struct mutex mutex; // mutex\r
+} iep_service_info;\r
+\r
+struct iep_reg {\r
+ iep_session *session;\r
+ struct list_head session_link; /* link to rga service session */\r
+ struct list_head status_link; /* link to register set list */\r
+ uint32_t reg[0x300];\r
+ bool dpi_en;\r
+ int off_x;\r
+ int off_y;\r
+ int act_width;\r
+ int act_height;\r
+ int vir_width;\r
+ int vir_height;\r
+ int layer;\r
+ unsigned int format;\r
+};\r
+\r
+#endif\r
+\r
--- /dev/null
+/* \r
+ * Copyright (C) 2013 ROCKCHIP, Inc.\r
+ *\r
+ * This software is licensed under the terms of the GNU General Public\r
+ * License version 2, as published by the Free Software Foundation, and\r
+ * may be copied, distributed, and modified under those terms.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ * \r
+ */\r
+\r
+#include <linux/slab.h>\r
+#include <linux/mm.h>\r
+#include <linux/sched.h>\r
+#include <asm/cacheflush.h>\r
+#include "iep_mmu.h"\r
+\r
+#define RK_MMU_DTE_SHIFT 22\r
+#define RK_MMU_DTE_MASK (~0xFFFL)\r
+#define RK_MMU_PTE_SHIFT 12\r
+#define RK_MMU_PTE_MASK (~0xFFFL)\r
+#define RK_MMU_DTE_ENTRY_CNT ((1) << (32-RK_MMU_DTE_SHIFT))\r
+#define RK_MMU_PTE_ENTRY_CNT ((1) << (RK_MMU_DTE_SHIFT - RK_MMU_PTE_SHIFT))\r
+\r
+#define RK_MMU_PAGE_PRESENT (1<<0)\r
+#define RK_MMU_READ_PERMISSION (1<<1)\r
+#define RK_MMU_WRITE_PERMISSION (1<<2)\r
+#define RK_MMU_OVERRIDE_CACHE_ATTRIBUTES (0<<3)\r
+#define RK_MMU_WRITE_CACHE_ABLE (0<<4)\r
+#define RK_MMU_WRITE_ALLOCABLE (0<<5)\r
+#define RK_MMU_WRITE_BUFFERABLE (0<<6)\r
+#define RK_MMU_READ_CACHE_ABLE (0<<7)\r
+#define RK_MMU_READ_ALLOCABLE (0<<8)\r
+\r
+#define RK_MMU_PTE_CTRL (RK_MMU_PAGE_PRESENT | RK_MMU_READ_PERMISSION | \\r
+ RK_MMU_WRITE_PERMISSION | RK_MMU_OVERRIDE_CACHE_ATTRIBUTES | \\r
+ RK_MMU_WRITE_CACHE_ABLE | RK_MMU_WRITE_ALLOCABLE | \\r
+ RK_MMU_WRITE_BUFFERABLE | RK_MMU_READ_CACHE_ABLE | \\r
+ RK_MMU_READ_ALLOCABLE)\r
+\r
+#define RK_MMU_DTE_CTRL RK_MMU_PAGE_PRESENT\r
+\r
+//#define RK_MMU_DEBUG\r
+\r
+static int map_user_space_addr(struct task_struct *tsk,\r
+ uint32_t *pte_table,\r
+ uint32_t page_index,\r
+ uint32_t page_count)\r
+{\r
+ int result;\r
+ int i;\r
+ int status = 0;\r
+ uint32_t phy_addr = 0;\r
+ struct page **pages;\r
+\r
+ pages = kzalloc((page_count + 1) * sizeof(struct page*), GFP_KERNEL);\r
+\r
+ down_read(&tsk->mm->mmap_sem);\r
+ result = get_user_pages(tsk, \r
+ tsk->mm, \r
+ page_index << PAGE_SHIFT, \r
+ page_count,\r
+ 1, 0, pages, NULL\r
+ );\r
+ up_read(&tsk->mm->mmap_sem);\r
+\r
+ if (result <= 0 || result < page_count) {\r
+ struct vm_area_struct *vma;\r
+\r
+ for(i=0; i<page_count; i++) {\r
+ vma = find_vma(tsk->mm, (page_index + i) << PAGE_SHIFT);\r
+\r
+ if (vma) {\r
+ pte_t *pte;\r
+ spinlock_t *ptl;\r
+ unsigned long pfn;\r
+ pgd_t *pgd;\r
+ pud_t *pud;\r
+ pmd_t *pmd;\r
+\r
+ pgd = pgd_offset(tsk->mm, (page_index + i) << PAGE_SHIFT);\r
+\r
+ if (pgd_none(*pgd) || pgd_bad(*pgd)) {\r
+ IEP_ERR("iep, invalid pgd\n");\r
+ status = -EIO;\r
+ break;\r
+ }\r
+\r
+ pud = pud_offset(pgd, (page_index + i) << PAGE_SHIFT);\r
+ if (pud_none(*pud) || pud_bad(*pud)) {\r
+ IEP_ERR("iep, invalid pud\n");\r
+ status = -EIO;\r
+ break;\r
+ }\r
+\r
+ pmd = pmd_offset(pud, (page_index + i) << PAGE_SHIFT);\r
+ if (pmd_none(*pmd) || pmd_bad(*pmd)) {\r
+ status = -EIO;\r
+ continue;\r
+ }\r
+\r
+ pte = pte_offset_map_lock(tsk->mm, pmd, (page_index + i) << PAGE_SHIFT, &ptl);\r
+ if (pte_none(*pte)) {\r
+ pte_unmap_unlock(pte, ptl);\r
+ status = -EIO;\r
+ continue;\r
+ }\r
+\r
+ pfn = pte_pfn(*pte);\r
+ phy_addr = ((pfn << PAGE_SHIFT) | (((unsigned long)((page_index + i) << PAGE_SHIFT)) & ~PAGE_MASK));\r
+ pte_unmap_unlock(pte, ptl);\r
+\r
+ pte_table[i] = (phy_addr & RK_MMU_PTE_MASK) | RK_MMU_PTE_CTRL;\r
+ } else {\r
+ status = -EIO;\r
+ break;\r
+ }\r
+ }\r
+\r
+ } else {\r
+ /* fill the page table. */\r
+ for(i=0; i<page_count; i++) {\r
+ /* get the physical address from page struct. */\r
+ pte_table[i] = (page_to_phys(pages[i]) & RK_MMU_PTE_MASK) | RK_MMU_PTE_CTRL;\r
+ }\r
+ }\r
+\r
+ kfree(pages);\r
+\r
+ return status;\r
+}\r
+\r
+int rk_mmu_generate_pte_from_va(iep_session *session, uint32_t va) \r
+{\r
+ int i;\r
+ int dte_index = va >> RK_MMU_DTE_SHIFT;\r
+ struct rk_mmu_pte *pte_node = NULL, *n;\r
+\r
+\r
+ if (session->dte_table[dte_index] != 0) {\r
+ list_for_each_entry_safe(pte_node, n, &session->pte_list, session_link) {\r
+ if (pte_node->index == dte_index) {\r
+ // a incomplete pte.\r
+#ifdef RK_MMU_DEBUG\r
+ uint32_t phy_addr;\r
+ uint32_t dte_addr;\r
+ uint32_t *pte_table;\r
+ uint32_t pte_addr;\r
+\r
+ int pte_index = (va >> PAGE_SHIFT) & 0x3FF;\r
+ int page_index = va & 0xFFF;\r
+\r
+ dte_addr = session->dte_table[dte_index];\r
+ IEP_DBG("dte_addr = %08x\n", dte_addr);\r
+\r
+ pte_table = phys_to_virt(dte_addr & RK_MMU_DTE_MASK);\r
+\r
+ pte_addr = pte_table[pte_index];\r
+\r
+ IEP_DBG("pte_addr = %08x\n", pte_addr);\r
+\r
+ phy_addr = (pte_addr & RK_MMU_PTE_MASK) | page_index;\r
+\r
+ IEP_DBG("phy %08x\n", phy_addr);\r
+#endif\r
+ IEP_DBG("Incomplete pte\n");\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (pte_node == NULL || pte_node->index != dte_index) {\r
+ // pte node is absence\r
+ pte_node = (struct rk_mmu_pte*)kzalloc(sizeof(struct rk_mmu_pte), GFP_KERNEL);\r
+ pte_node->pte = (uint32_t*)kzalloc(sizeof(uint32_t) * RK_MMU_PTE_ENTRY_CNT, GFP_KERNEL);\r
+ pte_node->index = dte_index;\r
+ }\r
+ \r
+ IEP_DBG("va = %08x\n", va);\r
+\r
+ if (va < PAGE_OFFSET) {\r
+ map_user_space_addr(session->tsk, pte_node->pte, (va >> PAGE_SHIFT) & (~0x3FFL), RK_MMU_PTE_ENTRY_CNT);\r
+ } else {\r
+ for (i=0; i<RK_MMU_PTE_ENTRY_CNT; i++) {\r
+ pte_node->pte[i] = (uint32_t)(virt_to_phys((uint32_t*)((va + i) << PAGE_SHIFT)) & RK_MMU_PTE_MASK) | RK_MMU_PTE_CTRL;\r
+ }\r
+ }\r
+\r
+ IEP_DBG("pa = %08x\n", (uint32_t)((pte_node->pte[(va>>PAGE_SHIFT) & 0x3FFL] & RK_MMU_PTE_MASK) | (va & 0xFFFL)));\r
+\r
+ INIT_LIST_HEAD(&pte_node->session_link);\r
+ list_add_tail(&pte_node->session_link, &session->pte_list);\r
+\r
+ dmac_flush_range(&pte_node->pte[0], &pte_node->pte[RK_MMU_PTE_ENTRY_CNT-1]);\r
+ outer_flush_range(virt_to_phys(&pte_node->pte[0]),virt_to_phys(&pte_node->pte[RK_MMU_PTE_ENTRY_CNT-1]));\r
+\r
+ session->dte_table[pte_node->index] = (uint32_t)(virt_to_phys((uint32_t*)pte_node->pte) & RK_MMU_DTE_MASK) | RK_MMU_DTE_CTRL;\r
+\r
+ dmac_flush_range(&session->dte_table[pte_node->index], &session->dte_table[pte_node->index+1]);\r
+ outer_flush_range(virt_to_phys(&session->dte_table[pte_node->index]),virt_to_phys(&session->dte_table[pte_node->index+1]));\r
+\r
+ return 0;\r
+}\r
+\r
+void rk_mmu_reclaim_pte_list(iep_session *session)\r
+{\r
+ struct rk_mmu_pte *pte_node, *n;\r
+\r
+ list_for_each_entry_safe(pte_node, n, &session->pte_list, session_link) {\r
+ list_del_init(&pte_node->session_link);\r
+ kfree(pte_node->pte);\r
+ kfree(pte_node);\r
+ }\r
+}\r
+\r
+/// don't call this function in interupt service.\r
+int rk_mmu_init_dte_table(iep_session *session)\r
+{\r
+ session->tsk = current;\r
+ session->dte_table = (uint32_t*)kzalloc(sizeof(uint32_t) * RK_MMU_DTE_ENTRY_CNT, GFP_KERNEL);\r
+\r
+ return 0;\r
+}\r
+\r
+void rk_mmu_deinit_dte_table(iep_session *session)\r
+{\r
+ rk_mmu_reclaim_pte_list(session);\r
+ kfree(session->dte_table);\r
+}\r
+\r
--- /dev/null
+#ifndef _IEP_MMU_H_\r
+#define _IEP_MMU_H_\r
+\r
+#include <linux/types.h>\r
+#include "iep_drv.h"\r
+\r
+struct rk_mmu_pte {\r
+ int index; // dte entry index [0, 1023]\r
+ uint32_t *pte; // point to pte table\r
+ struct list_head session_link; // link to session\r
+};\r
+\r
+int rk_mmu_generate_pte_from_va(iep_session *session, uint32_t va);\r
+void rk_mmu_reclaim_pte_list(iep_session *session);\r
+int rk_mmu_init_dte_table(iep_session *session);\r
+void rk_mmu_deinit_dte_table(iep_session *session);\r
+\r
+#endif\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff