sdmmc

diff --git a/drivers/mmc/host/rk2818-sdmmc.c b/drivers/mmc/host/rk2818-sdmmc.c
index 2761a0c8b25b0aaf3673b5f73fa683ae2b9a4223..f2ab2340e3c278e6ce69c1f8346e6b90456664b2 100644 (file)
--- a/drivers/mmc/host/rk2818-sdmmc.c
+++ b/drivers/mmc/host/rk2818-sdmmc.c
@@ -369,7 +369,10 @@ static int rk2818_sdmmc_submit_data_dma(struct rk2818_sdmmc_host *host, struct m
        unsigned int                    i;
 
        if(host->use_dma == 0)
+       {
+               host->dma_chn = -1;
                return -ENOSYS;
+       }
        if (data->blocks * data->blksz < RK2818_MCI_DMA_THRESHOLD)
                return -EINVAL;
        if (data->blksz & 3)

diff --git a/drivers/mmc/host/rk2818-sdmmc.h b/drivers/mmc/host/rk2818-sdmmc.h
index 444e1e88d9f3010b59be343fc0528021985d21c7..8b06357b90f8c7fb12e676269f7db869c8846fc8 100755 (executable)
--- a/drivers/mmc/host/rk2818-sdmmc.h
+++ b/drivers/mmc/host/rk2818-sdmmc.h
@@ -47,67 +47,67 @@
 
 #define SDMMC_DATA            (0x100)
 
-#define _BIT(n)                                (1<<(n))
+#define RK2818_BIT(n)                          (1<<(n))
 
 /* Control register defines */
-#define SDMMC_CTRL_ABRT_READ_DATA _BIT(8)
-#define SDMMC_CTRL_SEND_IRQ_RESP  _BIT(7)
-#define SDMMC_CTRL_READ_WAIT      _BIT(6)
-#define SDMMC_CTRL_DMA_ENABLE     _BIT(5)
-#define SDMMC_CTRL_INT_ENABLE     _BIT(4)
-#define SDMMC_CTRL_DMA_RESET      _BIT(2)
-#define SDMMC_CTRL_FIFO_RESET     _BIT(1)
-#define SDMMC_CTRL_RESET          _BIT(0)
+#define SDMMC_CTRL_ABRT_READ_DATA RK2818_BIT(8)
+#define SDMMC_CTRL_SEND_IRQ_RESP  RK2818_BIT(7)
+#define SDMMC_CTRL_READ_WAIT      RK2818_BIT(6)
+#define SDMMC_CTRL_DMA_ENABLE     RK2818_BIT(5)
+#define SDMMC_CTRL_INT_ENABLE     RK2818_BIT(4)
+#define SDMMC_CTRL_DMA_RESET      RK2818_BIT(2)
+#define SDMMC_CTRL_FIFO_RESET     RK2818_BIT(1)
+#define SDMMC_CTRL_RESET          RK2818_BIT(0)
 /* Clock Enable register defines */
-#define SDMMC_CLKEN_LOW_PWR      _BIT(16)
-#define SDMMC_CLKEN_ENABLE       _BIT(0)
+#define SDMMC_CLKEN_LOW_PWR      RK2818_BIT(16)
+#define SDMMC_CLKEN_ENABLE       RK2818_BIT(0)
 /* time-out register defines */
 #define SDMMC_TMOUT_DATA(n)      _SBF(8, (n))
 #define SDMMC_TMOUT_DATA_MSK     0xFFFFFF00
 #define SDMMC_TMOUT_RESP(n)      ((n) & 0xFF)
 #define SDMMC_TMOUT_RESP_MSK     0xFF
 /* card-type register defines */
-#define SDMMC_CTYPE_8BIT         _BIT(16)
-#define SDMMC_CTYPE_4BIT         _BIT(0)
+#define SDMMC_CTYPE_8BIT         RK2818_BIT(16)
+#define SDMMC_CTYPE_4BIT         RK2818_BIT(0)
 /* Interrupt status & mask register defines */
-#define SDMMC_INT_SDIO          _BIT(16)
-#define SDMMC_INT_EBE           _BIT(15)
-#define SDMMC_INT_ACD           _BIT(14)
-#define SDMMC_INT_SBE           _BIT(13)
-#define SDMMC_INT_HLE           _BIT(12)
-#define SDMMC_INT_FRUN          _BIT(11)
-#define SDMMC_INT_HTO           _BIT(10)
-#define SDMMC_INT_DRTO          _BIT(9)
-#define SDMMC_INT_RTO           _BIT(8)
-#define SDMMC_INT_DCRC          _BIT(7)
-#define SDMMC_INT_RCRC          _BIT(6)
-#define SDMMC_INT_RXDR          _BIT(5)
-#define SDMMC_INT_TXDR          _BIT(4)
-#define SDMMC_INT_DTO                  _BIT(3)
-#define SDMMC_INT_CMD_DONE             _BIT(2)
-#define SDMMC_INT_RE           _BIT(1)
-#define SDMMC_INT_CD            _BIT(0)
+#define SDMMC_INT_SDIO          RK2818_BIT(16)
+#define SDMMC_INT_EBE           RK2818_BIT(15)
+#define SDMMC_INT_ACD           RK2818_BIT(14)
+#define SDMMC_INT_SBE           RK2818_BIT(13)
+#define SDMMC_INT_HLE           RK2818_BIT(12)
+#define SDMMC_INT_FRUN          RK2818_BIT(11)
+#define SDMMC_INT_HTO           RK2818_BIT(10)
+#define SDMMC_INT_DRTO          RK2818_BIT(9)
+#define SDMMC_INT_RTO           RK2818_BIT(8)
+#define SDMMC_INT_DCRC          RK2818_BIT(7)
+#define SDMMC_INT_RCRC          RK2818_BIT(6)
+#define SDMMC_INT_RXDR          RK2818_BIT(5)
+#define SDMMC_INT_TXDR          RK2818_BIT(4)
+#define SDMMC_INT_DTO                  RK2818_BIT(3)
+#define SDMMC_INT_CMD_DONE             RK2818_BIT(2)
+#define SDMMC_INT_RE           RK2818_BIT(1)
+#define SDMMC_INT_CD            RK2818_BIT(0)
 
 /* Command register defines */
-#define SDMMC_CMD_START         _BIT(31)
-#define SDMMC_CMD_CCS_EXP       _BIT(23)
-#define SDMMC_CMD_CEATA_RD      _BIT(22)
-#define SDMMC_CMD_UPD_CLK       _BIT(21)
-#define SDMMC_CMD_INIT          _BIT(15)
-#define SDMMC_CMD_STOP          _BIT(14)
-#define SDMMC_CMD_PRV_DAT_WAIT  _BIT(13)
-#define SDMMC_CMD_SEND_STOP     _BIT(12)
-#define SDMMC_CMD_STRM_MODE     _BIT(11)
-#define SDMMC_CMD_DAT_WR        _BIT(10)
-#define SDMMC_CMD_DAT_EXP       _BIT(9)
-#define SDMMC_CMD_RESP_CRC      _BIT(8)
-#define SDMMC_CMD_RESP_LONG     _BIT(7)
-#define SDMMC_CMD_RESP_EXP      _BIT(6)
+#define SDMMC_CMD_START         RK2818_BIT(31)
+#define SDMMC_CMD_CCS_EXP       RK2818_BIT(23)
+#define SDMMC_CMD_CEATA_RD      RK2818_BIT(22)
+#define SDMMC_CMD_UPD_CLK       RK2818_BIT(21)
+#define SDMMC_CMD_INIT          RK2818_BIT(15)
+#define SDMMC_CMD_STOP          RK2818_BIT(14)
+#define SDMMC_CMD_PRV_DAT_WAIT  RK2818_BIT(13)
+#define SDMMC_CMD_SEND_STOP     RK2818_BIT(12)
+#define SDMMC_CMD_STRM_MODE     RK2818_BIT(11)
+#define SDMMC_CMD_DAT_WR        RK2818_BIT(10)
+#define SDMMC_CMD_DAT_EXP       RK2818_BIT(9)
+#define SDMMC_CMD_RESP_CRC      RK2818_BIT(8)
+#define SDMMC_CMD_RESP_LONG     RK2818_BIT(7)
+#define SDMMC_CMD_RESP_EXP      RK2818_BIT(6)
 #define SDMMC_CMD_INDX(n)       ((n) & 0x1F)
 /* Status register defines */
 #define SDMMC_GET_FCNT(x)       (((x)>>17) & 0x1FF)
 #define SDMMC_FIFO_SZ           32
 
-#define SDMMC_WRITE_PROTECT            _BIT(0)
-#define SDMMC_CARD_DETECT_N            _BIT(0)
+#define SDMMC_WRITE_PROTECT            RK2818_BIT(0)
+#define SDMMC_CARD_DETECT_N            RK2818_BIT(0)
 #endif