&rk29_device_i2c3,\r
#endif\r
\r
-#ifdef CONFIG_SND_RK29_SOC_I2C_2CH\r
+#ifdef CONFIG_SND_RK29_SOC_I2S_2CH\r
&rk29_device_iis_2ch,\r
#endif\r
#ifdef CONFIG_SND_RK29_SOC_I2S_8CH\r
};
struct platform_device rk29_device_iis_2ch = {
- .name = "rk29-i2s",
+ .name = "rk29_i2s",
.id = 0,
.num_resources = ARRAY_SIZE(rk29_iis_2ch_resource),
.resource = rk29_iis_2ch_resource,
};
struct platform_device rk29_device_iis_8ch = {
- .name = "rk29-i2s",
+ .name = "rk29_i2s",
.id = 1,
.num_resources = ARRAY_SIZE(rk29_iis_8ch_resource),
.resource = rk29_iis_8ch_resource,
ret = request_irq(irq, pl330_irq_handler, 0,
dev_name(&pdev->dev), pl330_info);
- if(pdev->id == 1){
- request_irq(IRQ_DMAC2_1, pl330_irq_handler, 0,
+
+ if(pdev->id == 0){
+ request_irq(IRQ_DMAC0_1, pl330_irq_handler, 0,
+ dev_name(&pdev->dev), pl330_info);
+ request_irq(IRQ_DMAC0_2, pl330_irq_handler, 0,
+ dev_name(&pdev->dev), pl330_info);
+ request_irq(IRQ_DMAC0_3, pl330_irq_handler, 0,
dev_name(&pdev->dev), pl330_info);
- request_irq(IRQ_DMAC2_2, pl330_irq_handler, 0,
+ }
+
+ if(pdev->id == 1){
+ request_irq(IRQ_DMAC2_1, pl330_irq_handler, 0,
+ dev_name(&pdev->dev), pl330_info);
+ request_irq(IRQ_DMAC2_2, pl330_irq_handler, 0,
dev_name(&pdev->dev), pl330_info);
request_irq(IRQ_DMAC2_3, pl330_irq_handler, 0,
dev_name(&pdev->dev), pl330_info);
- request_irq(IRQ_DMAC2_4, pl330_irq_handler, 0,
+ request_irq(IRQ_DMAC2_4, pl330_irq_handler, 0,
dev_name(&pdev->dev), pl330_info);
- }
+ }
+
if (ret)
goto probe_err4;
struct i2c_client *client = codec->control_data;
/* Read register */
- xfer[0].addr = (client->addr& 0x60)|(reg+1);
+ xfer[0].addr = (client->addr& 0x60)|(reg);
xfer[0].flags = I2C_M_RD;
xfer[0].len = 1;
xfer[0].buf = ®
{
u8 data[2];
struct i2c_client *i2c;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ DBG("Enter::%s, %d, reg=0x%02X, value=0x%02X\n",__FUNCTION__,__LINE__, reg, value);
data[0] = value & 0x00ff;
rk1000_codec_write_reg_cache (codec, reg, value);
i2c = (struct i2c_client *)codec->control_data;
i2c->addr = (i2c->addr & 0x60)|reg;
- if (codec->hw_write(codec->control_data, data, 1) == 2){
+ if (codec->hw_write(codec->control_data, data, 1) == 1){
DBG("================%s Run OK================\n",__FUNCTION__,__LINE__);
return 0;
}else{
struct snd_soc_codec *codec = codec_dai->codec;
struct rk1000_codec_priv *rk1000_codec = codec->private_data;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
switch (freq) {
case 11289600:
DBG("Enter::%s----%d iface=%x srate =%x rate=%d\n",__FUNCTION__,__LINE__,iface,srate,params_rate(params));
rk1000_codec_write(codec,ACCELCODEC_R0C, 0x17);
- rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF); //soft mute
- //±ØÐëÏȽ«clkºÍEN_INT¶¼disableµô£¬·ñÔòÇл»bclk·ÖƵֵ¿ÉÄܵ¼ÖÂcodecÄÚ²¿Ê±Ðò»ìÂÒµô£¬
- //±íÏÖ³öÀ´µÄÏÖÏóÊÇ£¬ÒÔºóµÄÒôÀÖ¶¼±ä³ÉÁËÔëÒô£¬¶øÇÒ¾ÍËã°ÑÊäÈëcodecµÄI2S_DATAOUT¶Ï¿ªÒ²Ò»Ñù³öÔëÒô
- rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE); //0x00
+ rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF); //soft mute
+ //±ØÐëÏȽ«clkºÍEN_INT¶¼disableµô£¬·ñÔòÇл»bclk·ÖƵֵ¿ÉÄܵ¼ÖÂcodecÄÚ²¿Ê±Ðò»ìÂÒµô£¬
+ //±íÏÖ³öÀ´µÄÏÖÏóÊÇ£¬ÒÔºóµÄÒôÀÖ¶¼±ä³ÉÁËÔëÒô£¬¶øÇÒ¾ÍËã°ÑÊäÈëcodecµÄI2S_DATAOUT¶Ï¿ªÒ²Ò»Ñù³öÔëÒô
+ rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE); //0x00
/* set iface & srate */
rk1000_codec_write(codec, ACCELCODEC_R09, iface);
if (coeff >= 0){
rk1000_codec_write(codec, ACCELCODEC_R0A, (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb|ASC_CLKNODIV|ASC_CLK_ENABLE);
- rk1000_codec_write(codec, ACCELCODEC_R00, srate|coeff_div[coeff].bclk);
+ rk1000_codec_write(codec, ACCELCODEC_R00, srate|coeff_div[coeff].bclk);
}
- rk1000_codec_write(codec,ACCELCODEC_R0B, gR0BReg);
+ rk1000_codec_write(codec,ACCELCODEC_R0B, gR0BReg);
return 0;
}
void PhaseOut(struct snd_soc_codec *codec,u32 nStep, u32 us)
{
- DBG("%s[%d]\n",__FUNCTION__,__LINE__);
- rk1000_codec_write(codec,ACCELCODEC_R17, 0x0F|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL
- rk1000_codec_write(codec,ACCELCODEC_R18, 0x0F|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOR
- udelay(us);
+ DBG("%s[%d]\n",__FUNCTION__,__LINE__);
+ rk1000_codec_write(codec,ACCELCODEC_R17, 0x0F|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL
+ rk1000_codec_write(codec,ACCELCODEC_R18, 0x0F|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOR
+ udelay(us);
}
void PhaseIn(struct snd_soc_codec *codec,u32 nStep, u32 us)
{
- DBG("%s[%d]\n",__FUNCTION__,__LINE__);
- rk1000_codec_write(codec,ACCELCODEC_R17, 0x0f|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL
- rk1000_codec_write(codec,ACCELCODEC_R18, 0x0f|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOR
- udelay(us);
+ DBG("%s[%d]\n",__FUNCTION__,__LINE__);
+ rk1000_codec_write(codec,ACCELCODEC_R17, 0x0f|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL
+ rk1000_codec_write(codec,ACCELCODEC_R18, 0x0f|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOR
+ udelay(us);
}
static int rk1000_codec_mute(struct snd_soc_dai *dai, int mute)
{
- struct snd_soc_codec *codec = dai->codec;
-
- DBG("Enter::%s----%d--mute=%d\n",__FUNCTION__,__LINE__,mute);
- if (mute){
- PhaseOut(codec,1, 5000);
- rk1000_codec_write(codec,ACCELCODEC_R19, 0xFF); //AOM
- rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF); //soft mute
- }else{
- rk1000_codec_write(codec,ACCELCODEC_R1D, 0x2a); //setup Vmid and Vref, other module power down
- rk1000_codec_write(codec,ACCELCODEC_R1E, 0x40); ///|ASC_PDASDML_ENABLE);
- rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE); ///|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE);
- PhaseIn(codec,1, 5000);
- ///if(gCodecVol != 0){
- rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_ACTIVE_L|ASC_INT_ACTIVE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);
- //}
- rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F); //AOM
- #if 0
- /*disable speaker */
- rockchip_mux_api_set(SPK_IOMUX_PIN_NAME, SPK_IOMUX_PIN_DIR);
- GPIOSetPinDirection(SPK_CTRL_PIN,GPIO_OUT);
- GPIOSetPinLevel(SPK_CTRL_PIN,GPIO_HIGH);
- #endif
- }
- return 0;
+ struct snd_soc_codec *codec = dai->codec;
+
+ DBG("Enter::%s----%d--mute=%d\n",__FUNCTION__,__LINE__,mute);
+
+ if (mute){
+ PhaseOut(codec,1, 5000);
+ rk1000_codec_write(codec,ACCELCODEC_R19, 0xFF); //AOM
+ rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF); //soft mute
+ }else{
+ rk1000_codec_write(codec,ACCELCODEC_R1D, 0x2a); //setup Vmid and Vref, other module power down
+ rk1000_codec_write(codec,ACCELCODEC_R1E, 0x40); ///|ASC_PDASDML_ENABLE);
+ rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE); ///|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE);
+ PhaseIn(codec,1, 5000);
+ ///if(gCodecVol != 0){
+ rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_ACTIVE_L|ASC_INT_ACTIVE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);
+ //}
+ rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F); //AOM
+ #if 0
+ /*disable speaker */
+ rockchip_mux_api_set(SPK_IOMUX_PIN_NAME, SPK_IOMUX_PIN_DIR);
+ GPIOSetPinDirection(SPK_CTRL_PIN,GPIO_OUT);
+ GPIOSetPinLevel(SPK_CTRL_PIN,GPIO_HIGH);
+ #endif
+ }
+ return 0;
}
static int rk1000_codec_set_bias_level(struct snd_soc_codec *codec,
#if 0
-#define DBG(x...) printk(KERN_INFO x)
+#define I2S_DBG(x...) printk(KERN_INFO x)
#else
-#define DBG(x...) do { } while (0)
+#define I2S_DBG(x...) do { } while (0)
#endif
#define pheadi2s ((pI2S_REG)(i2s->regs))
*/
static void rockchip_snd_txctrl(struct rk29_i2s_info *i2s, int on)
{
- //struct rk29_i2s_info *i2s = &rockchip_i2s;
- u32 opr,fifosts;
+ u32 opr,xfer,fifosts;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
-
- opr = readl(&(pheadi2s->I2S_OPR));
- fifosts = readl(&(pheadi2s->I2S_FIFOSTS));
- fifosts = (fifosts & (~(0x0f<<16))) | TX_HALF_FULL | RX_HALF_FULL;
- writel(fifosts, &(pheadi2s->I2S_FIFOSTS));
+ I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
+
+ opr = readl(pheadi2s->I2S_DMACR);
+ xfer = readl(pheadi2s->I2S_XFER);
+
+ opr &= ~I2S_TRAN_DMA_ENABLE;
+ xfer &= ~I2S_TX_TRAN_START;
if (on)
- {
- opr = (opr & (~(RESET_RX | I2S_DMA_REQ2_DISABLE | TX_START | RX_START))) | (RESET_TX | I2S_DMA_REQ1_DISABLE);
- writel(opr, &(pheadi2s->I2S_OPR));
+ {
+ writel(opr, &(pheadi2s->I2S_DMACR));
+ writel(xfer, &(pheadi2s->I2S_XFER));
udelay(5);
- opr = (opr & (~(I2S_DMA_REQ1_DISABLE | I2S_DMA_REQ1_RX_ENABLE | RX_START))) | I2S_DMA_REQ1_ENABLE | I2S_DMA_REQ1_TX_ENABLE | TX_START;
- writel(opr, &(pheadi2s->I2S_OPR));
+
+ opr |= I2S_TRAN_DMA_ENABLE;
+ xfer |= I2S_TX_TRAN_START;
+ writel(opr, &(pheadi2s->I2S_DMACR));
+ writel(xfer, &(pheadi2s->I2S_XFER));
}
else
- {
- opr = (opr & (~TX_START)) | I2S_DMA_REQ1_DISABLE;
- writel(opr, &(pheadi2s->I2S_OPR));
- }
+ {
+ writel(opr, &(pheadi2s->I2S_DMACR));
+ writel(xfer, &(pheadi2s->I2S_XFER));
+ }
}
static void rockchip_snd_rxctrl(struct rk29_i2s_info *i2s, int on)
{
- //struct rk29_i2s_info *i2s = &rockchip_i2s;
- u32 opr,fifosts;
+ u32 opr,xfer,fifosts;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
- opr = readl(&(pheadi2s->I2S_OPR));
- fifosts = readl(&(pheadi2s->I2S_FIFOSTS));
- fifosts = (fifosts & (~(0x0f<<16))) | TX_HALF_FULL | RX_HALF_FULL;
- writel(fifosts, &(pheadi2s->I2S_FIFOSTS));
+ I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
+
+ opr = readl(pheadi2s->I2S_DMACR);
+ xfer = readl(pheadi2s->I2S_XFER);
+
+ opr &= ~I2S_RECE_DMA_ENABLE;
+ xfer &= ~I2S_RX_TRAN_START;
+
if (on)
- {
- opr = (opr & (~(RESET_TX | I2S_DMA_REQ1_DISABLE| TX_START | RX_START))) | (RESET_RX | I2S_DMA_REQ2_DISABLE);
- writel(opr, &(pheadi2s->I2S_OPR));
+ {
+ writel(opr, &(pheadi2s->I2S_DMACR));
+ writel(xfer, &(pheadi2s->I2S_XFER));
udelay(5);
- opr = (opr & (~(I2S_DMA_REQ2_DISABLE | I2S_DMA_REQ2_TX_ENABLE | TX_START))) | I2S_DMA_REQ2_ENABLE | I2S_DMA_REQ2_RX_ENABLE | RX_START;
- writel(opr, &(pheadi2s->I2S_OPR));
+
+ opr |= I2S_RECE_DMA_ENABLE;
+ xfer |= I2S_RX_TRAN_START;
+ writel(opr, &(pheadi2s->I2S_DMACR));
+ writel(xfer, &(pheadi2s->I2S_XFER));
}
else
{
- opr = (opr & (~RX_START)) | I2S_DMA_REQ2_DISABLE;
- writel(opr, &(pheadi2s->I2S_OPR));
- }
+ writel(opr, &(pheadi2s->I2S_DMACR));
+ writel(xfer, &(pheadi2s->I2S_XFER));
+ }
}
/*
struct rk29_i2s_info *i2s = to_info(cpu_dai);
u32 tx_ctl,rx_ctl;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
- tx_ctl = readl(&(pheadi2s->I2S_TXCTL));
- tx_ctl &= (~MASTER_MODE);
+ tx_ctl = readl(&(pheadi2s->I2S_TXCR));
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
- tx_ctl |= MASTER_MODE;
+ tx_ctl &= ~I2S_MODE_MASK;
+ tx_ctl |= I2S_MASTER_MODE;
break;
case SND_SOC_DAIFMT_CBS_CFS:
- tx_ctl |= SLAVE_MODE;
+ tx_ctl &= ~I2S_MODE_MASK;
+ tx_ctl |= I2S_SLAVE_MODE;
break;
default:
- DBG("unknwon master/slave format\n");
+ I2S_DBG("unknwon master/slave format\n");
return -EINVAL;
- }
- tx_ctl &= ~IISMOD_SDF_MASK;
+ }
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
- tx_ctl |= RIGHT_JUSTIFIED;
+ tx_ctl &= ~I2S_BUS_MODE_MASK; //I2S Bus Mode
+ tx_ctl |= I2S_BUS_MODE_RSJM;
break;
case SND_SOC_DAIFMT_LEFT_J:
- tx_ctl |= LEFT_JUSTIFIED;
+ tx_ctl &= ~I2S_BUS_MODE_MASK; //I2S Bus Mode
+ tx_ctl |= I2S_BUS_MODE_LSJM;
break;
case SND_SOC_DAIFMT_I2S:
- tx_ctl |= I2S_MODE;
+ tx_ctl &= ~I2S_BUS_MODE_MASK; //I2S Bus Mode
+ tx_ctl |= I2S_BUS_MODE_NOR;
break;
default:
- DBG("Unknown data format\n");
+ I2S_DBG("Unknown data format\n");
return -EINVAL;
}
- tx_ctl = tx_ctl & (~(0xff<<8)) & (~(0x03<<16)) & (~(1<<3));
- tx_ctl = tx_ctl | OVERSAMPLING_RATE_64FS | SCK_RATE4 | STEREO_MODE;
- writel(tx_ctl, &(pheadi2s->I2S_TXCTL));
- rx_ctl = tx_ctl | CLEAR_RXFIFO;
- writel(rx_ctl, &(pheadi2s->I2S_RXCTL));
+ I2S_DBG("Enter::%s----%d, I2S_TXCR=0x%X\n",__FUNCTION__,__LINE__,tx_ctl);
+ writel(tx_ctl, &(pheadi2s->I2S_TXCR));
+ rx_ctl = tx_ctl & 0x00007FFF;
+ writel(rx_ctl, &(pheadi2s->I2S_RXCR));
return 0;
}
struct rk29_i2s_info *i2s = to_info(dai->cpu_dai);
u32 iismod;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
/*by Vincent Hsiung for EQ Vol Change*/
#define HW_PARAMS_FLAG_EQVOL_ON 0x21
#define HW_PARAMS_FLAG_EQVOL_OFF 0x22
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
- dai->cpu_dai->dma_data = i2s->dma_playback->client;
+ dai->cpu_dai->dma_data = i2s->dma_playback;
else
- dai->cpu_dai->dma_data = i2s->dma_capture->client;
+ dai->cpu_dai->dma_data = i2s->dma_capture;
/* Working copies of register */
- iismod = readl(&(pheadi2s->I2S_TXCTL));
- iismod &= (~SAMPLE_DATA_MASK);
+ iismod = readl(&(pheadi2s->I2S_TXCR));
+ //iismod &= (~((1<<5)-1));
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
iismod |= SAMPLE_DATA_8bit;
break;
case SNDRV_PCM_FORMAT_S16_LE:
- iismod |= SAMPLE_DATA_16bit;
+ iismod |= I2S_DATA_WIDTH(15);
break;
}
- /*stereo mode MCLK/SCK=4*/
- iismod = iismod & (~(0xff<<8)) & (~(0x03<<16)) & (~(1<<3));
- iismod = iismod | OVERSAMPLING_RATE_64FS | SCK_RATE4 | STEREO_MODE;
-
- writel(iismod, &(pheadi2s->I2S_TXCTL));
- iismod = iismod | CLEAR_RXFIFO;
- writel(iismod, &(pheadi2s->I2S_RXCTL));
+
+ iismod |= I2S_SLAVE_MODE;
+
+ writel((16<<24) |(16<<18)|(16<<12)|(16<<6)|16, &(pheadi2s->I2S_FIFOLR));
+
+ I2S_DBG("Enter %s, %d I2S_TXCR=0x%08X\n", __func__, __LINE__, iismod);
+ writel(iismod, &(pheadi2s->I2S_TXCR));
+ iismod = iismod & 0x00007FFF;
+ writel(iismod, &(pheadi2s->I2S_RXCR));
+
+ /*stereo mode MCLK/SCK=4*/
+
+ iismod = I2S_TX_SCLK_DIV(63) | I2S_MCLK_DIV(7);
+
+ //iismod = (3<<16) | 63;
+ I2S_DBG("Enter %s, %d I2S_TXCKR=0x%08X\n", __func__, __LINE__, iismod);
+ writel(iismod, &(pheadi2s->I2S_TXCKR));
+ writel(iismod, &(pheadi2s->I2S_RXCKR));
+
return 0;
}
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct rk29_i2s_info *i2s = to_info(rtd->dai->cpu_dai);
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
/*add scu clk source and enable clk*/
return 0;
{
//u32 reg;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
/*when i2s in master mode ,must set codec pll div*/
switch (div_id) {
case ROCKCHIP_DIV_BCLK:
*/
u32 rockchip_i2s_get_clockrate(void)
{
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
return 0; ///clk_get_rate(s3c24xx_i2s.iis_clk);
}
EXPORT_SYMBOL_GPL(rockchip_i2s_get_clockrate);
#ifdef CONFIG_PM
int rockchip_i2s_suspend(struct snd_soc_dai *cpu_dai)
{
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
- //clk_disable(clk);
- return 0;
+ I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ //clk_disable(clk);
+ return 0;
}
int rockchip_i2s_resume(struct snd_soc_dai *cpu_dai)
{
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
- //clk_enable(clk);
- return 0;
+ I2S_DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ //clk_enable(clk);
+ return 0;
}
#else
#define rockchip_i2s_suspend NULL
static int rockchip_i2s_dai_probe(struct platform_device *pdev, struct snd_soc_dai *dai)
{
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
return 0;
}
unsigned long base)
{
struct device *dev = &pdev->dev;
- unsigned int iismod;
struct resource *res;
+ I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
+
i2s->dev = dev;
/* record our i2s structure for later use in the callbacks */
}
if (!request_mem_region(res->start, resource_size(res),
- "rk29-i2s")) {
+ "rk29_i2s")) {
dev_err(dev, "Unable to request register region\n");
return -EBUSY;
}
/* Mark ourselves as in TXRX mode so we can run through our cleanup
* process without warnings. */
-
rockchip_snd_txctrl(i2s, 0);
rockchip_snd_rxctrl(i2s, 0);
struct snd_soc_dai *dai;
int ret;
+ I2S_DBG("Enter %s, %d pdev->id = %d >>>>>>>>>>>\n", __func__, __LINE__, pdev->id);
+
if(pdev->id >= MAX_I2S) {
dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
return -EINVAL;
i2s = &rk29_i2s[pdev->id];
dai = &rk29_i2s_dai[pdev->id];
dai->dev = &pdev->dev;
- dai->name = "rk29-i2s";
+ dai->name = "rk29_i2s";
dai->id = pdev->id;
dai->symmetric_rates = 1;
- dai->playback.channels_min = 2;
- dai->playback.channels_max = 2;
+ if(pdev->id == 0) {
+ dai->playback.channels_min = 2;
+ dai->playback.channels_max = 8;
+ }else{
+ dai->playback.channels_min = 2;
+ dai->playback.channels_max = 2;
+ }
dai->playback.rates = ROCKCHIP_I2S_RATES;
dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE;
dai->capture.channels_min = 2;
i2s->dma_capture = &rk29_i2s_pcm_stereo_in[pdev->id];
i2s->dma_playback = &rk29_i2s_pcm_stereo_out[pdev->id];
- if (pdev->id == 0) {
+ if (pdev->id == 1) {
i2s->dma_capture->channel = DMACH_I2S_2CH_RX;
i2s->dma_capture->dma_addr = RK29_I2S_2CH_PHYS + I2S_RXR_BUFF;
i2s->dma_playback->channel = DMACH_I2S_2CH_TX;
.probe = rockchip_i2s_probe,
.remove = __devexit_p(rockchip_i2s_remove),
.driver = {
- .name = "rk29-i2s",
+ .name = "rk29_i2s",
.owner = THIS_MODULE,
},
};
static int __init rockchip_i2s_init(void)
{
- printk(KERN_INFO
- "Enter Func = %s\n", __func__);
+ I2S_DBG("Enter %s, %d >>>>>>>>>>>\n", __func__, __LINE__);
+
return platform_driver_register(&rockchip_i2s_driver);
}
module_init(rockchip_i2s_init);
#ifndef _ROCKCHIP_IIS_H
#define _ROCKCHIP_IIS_H
-//I2S_OPR
+//I2S_TXCR
+
+#define PCM_2DATA (0<<18)
+#define PCM_4DATA (1<<18)
+#define PCM_6DATA (2<<18)
+#define PCM_8DATA (3<<18)
+
+#define CHANNEL_1_EN (0<<15)
+#define CHANNEL_2_EN (1<<15)
+#define CHANNEL_3_EN (2<<15)
+#define CHANNLE_4_EN (3<<15)
+
+#define TX_MODE_MASTER (0<<13)
+#define TX_MODE_SLAVE (1<<13)
+
+
#define RESET_TX (1<<17)
#define RESET_RX (1<<16)
#define I2S_DMA_REQ1_DISABLE (1<<6)
#define TX_HALF_FULL (1<<18)
#define RX_HALF_FULL (1<<16)
-#define I2S_TXR_BUFF 0x04
-#define I2S_RXR_BUFF 0x08
-
/* Clock dividers */
#define ROCKCHIP_DIV_MCLK 0
#define ROCKCHIP_DIV_BCLK 1
#define ROCKCHIP_DIV_PRESCALER 2
+
+/* I2S_TXCR */
+#define I2S_RSTL_SCLK(c) ((c&0x3F)<<26)
+#define I2S_RSTR_SCLK(c) ((c&0x3F)<<20)
+
+#define I2S_PCM_2DATA (0<<18)
+#define I2S_PCM_4DATA (1<<18)
+#define I2S_PCM_6DATA (2<<18)
+#define I2S_PCM_8DATA (3<<18)
+#define I2S_PCM_DATA_MASK (3<<18)
+
+#define I2S_CSR_CH2 (0<<15)
+#define I2S_CSR_CH4 (1<<15)
+#define I2S_CRS_CH6 (2<<15)
+#define I2S_CRS_CH8 (3<<15)
+#define I2S_CRS_CH_MASK (3<<15)
+
+#define I2S_HWT_16BIT (0<<14)
+#define I2S_HWT_32BIT (1<<14)
+
+#define I2S_MASTER_MODE (0<<13)
+#define I2S_SLAVE_MODE (1<<13)
+#define I2S_MODE_MASK (1<<13)
+
+#define I2S_JUSTIFIED_RIGHT (0<<12)
+#define I2S_JUSTIFIED_LEFT (1<<12)
+
+#define I2S_FIRST_BIT_MSB (0<<11)
+#define I2S_FIRST_BIT_LSB (1<<11)
+
+#define I2S_BUS_MODE_NOR (0<<9)
+#define I2S_BUS_MODE_LSJM (1<<9)
+#define I2S_BUS_MODE_RSJM (2<<9)
+#define I2S_BUS_MODE_MASK (3<<9)
+
+#define I2S_PCM_NO_DELAY (0<<7)
+#define I2S_PCM_DELAY_1MODE (1<<7)
+#define I2S_PCM_DELAY_2MODE (2<<7)
+#define I2S_PCM_DELAY_3MODE (3<<7)
+#define I2S_PCM_DELAY_MASK (3<<7)
+
+#define I2S_TX_LRCK_OUT_BT_DISABLE (0<<6)
+#define I2S_TX_LRCK_OUT_BT_ENABLE (1<<6)
+
+#define I2S_TX_LRCK_OUT_I2S (0<<5)
+#define I2S_TX_LRCK_OUT_PCM (1<<5)
+
+#define I2S_DATA_WIDTH(w) ((&0x1F)<<0)
+
+/* */
+
+
+/* I2S_TXCKR */
+#define I2S_TSP_POSEDGE (0<<25)
+#define I2S_TSP_NEGEDGE (1<<25)
+#define I2S_TLP_NORMAL (0<<24)
+#define I2S_TLP_OPPSITE (1<<24)
+
+#define I2S_MCLK_DIV(x) ((0xFF&x)<<16)
+
+#define I2S_TSD_FIXED (0<<12)
+#define I2S_TSD_CHANGED (1<<12)
+
+#define I2S_TX_LRCK_NO_DELAY (0<<10)
+#define I2S_TX_LRCK_DELAY_ONE (1<<10)
+#define I2S_TX_LRCK_DELAY_TWO (2<<10)
+#define I2S_TX_LRCK_DELAY_THREE (3<<10)
+#define I2S_TX_LRCK_DELAY_MASK (3<<10)
+
+#define I2S_TX_SCLK_DIV(x) (x&0x3FF)
+
+
+/* I2S_DMACR */
+#define I2S_RECE_DMA_DISABLE (0<<24)
+#define I2S_RECE_DMA_ENABLE (1<<24)
+#define I2S_DMARDL(x) ((x&0x1f)<<16)
+
+#define I2S_TRAN_DMA_DISABLE (0<<8)
+#define I2S_TRAN_DMA_ENABLE (1<<8)
+#define I2S_DMATDL(x) ((x&0x1f)<<0)
+
+/* I2S_INTCR */
+#define I2S_RXOV_INT_DISABLE (0<<17)
+#define I2S_RXOV_INT_ENABLE (1<<17)
+#define I2S_RXFU_INT_DISABLE (0<<16)
+#define I2S_RXFU_INT_ENABLE (1<<16)
+
+#define I2S_TXUND_INT_DISABLE (0<<1)
+#define I2S_TXUND_INT_ENABLE (1<<1)
+#define I2S_TXEMP_INT_DISABLE (0<<0)
+#define I2S_TXEMP_INT_ENABLE (1<<0)
+
+/* I2S_XFER */
+#define I2S_RX_TRAN_STOP (0<<1)
+#define I2S_RX_TRAN_START (1<<1)
+#define I2S_TX_TRAN_STOP (0<<0)
+#define I2S_TX_TRAN_START (1<<0)
+
+
+#define I2S_TXR_BUFF 0x20
+#define I2S_RXR_BUFF 0x24
+
//I2S Registers
typedef volatile struct tagIIS_STRUCT
{
- unsigned int I2S_OPR;
- unsigned int I2S_TXR;
- unsigned int I2S_RXR;
- unsigned int I2S_TXCTL;
- unsigned int I2S_RXCTL;
- unsigned int I2S_FIFOSTS;
- unsigned int I2S_IER;
- unsigned int I2S_ISR;
+ unsigned int I2S_TXCR;
+ unsigned int I2S_RXCR;
+ unsigned int I2S_TXCKR;
+ unsigned int I2S_RXCKR;
+ unsigned int I2S_FIFOLR;
+ unsigned int I2S_DMACR;
+ unsigned int I2S_INTCR;
+ unsigned int I2S_INTSR;
+ unsigned int I2S_TXDR;
+ unsigned int I2S_RXDR;
+ unsigned int I2S_XFER;
+ unsigned int I2S_TXRST;
+ unsigned int I2S_RXRST;
}I2S_REG,*pI2S_REG;
extern struct snd_soc_dai rk29_i2s_dai[];
{
struct rockchip_dma_buf_set *sg_buf;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
sg_buf = kzalloc(sizeof(struct rockchip_dma_buf_set), GFP_ATOMIC);/* ddl@rock-chips.com:GFP_KERNEL->GFP_ATOMIC */
if (sg_buf == NULL) {
void rockchip_pcm_dma_irq(s32 ch, void *data);
-
-
void audio_start_dma(struct snd_pcm_substream *substream, int mode)
{
struct rockchip_runtime_data *prtd;
unsigned long flags;
struct rockchip_dma_buf_set *sg_buf;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
prtd = substream->runtime->private_data;
struct rockchip_runtime_data *prtd = substream->runtime->private_data;
dma_addr_t pos = prtd->dma_pos;
int ret;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ char* vpos;
+ int i;
+
+
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
- while (prtd->dma_loaded < prtd->dma_limit) {
+ while (prtd->dma_loaded < prtd->dma_limit) {
unsigned long len = prtd->dma_period;
- DBG("dma_loaded: %d\n", prtd->dma_loaded);
+ DBG("dma_loaded: %d\n", prtd->dma_loaded);
if ((pos + len) > prtd->dma_end) {
len = prtd->dma_end - pos;
}
- //ret = rockchip_dma_buffer_set_enqueue(prtd, pos, len);
+ //ret = rockchip_dma_buffer_set_enqueue(prtd, pos, len);
ret = rk29_dma_enqueue(prtd->params->channel,
substream, pos, len);
+
+ DBG("Enter::%s, %d, ret=%d, Channel=%d, Addr=0x%X, Len=%d\n",
+ __FUNCTION__,__LINE__, ret, prtd->params->channel, pos, len);
if (ret == 0) {
prtd->dma_loaded++;
pos += prtd->dma_period;
void rockchip_pcm_dma_irq(s32 ch, void *data)
{
- struct snd_pcm_substream *substream = data;
+ struct snd_pcm_substream *substream = data;
struct rockchip_runtime_data *prtd;
unsigned long flags;
if (prtd->state & ST_RUNNING) {
rockchip_pcm_enqueue(substream);
}
- spin_unlock(&prtd->lock);
- local_irq_save(flags);
+ spin_unlock(&prtd->lock);
+ local_irq_save(flags);
if (prtd->state & ST_RUNNING) {
if (prtd->dma_loaded) {
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
}
-void rk29_audio_buffdone(struct rk29_dma_chan *ch,
- void *dev_id, int size,
+void rk29_audio_buffdone(void *dev_id, int size,
enum rk29_dma_buffresult result)
{
struct snd_pcm_substream *substream = dev_id;
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
prtd = substream->runtime->private_data;
- if (substream)
+ DBG("Enter::%s----%d, substream=0x%08X, prtd=0x%08X\n",__FUNCTION__,__LINE__, substream, prtd);
+ if (substream){
snd_pcm_period_elapsed(substream);
+ }
spin_lock(&prtd->lock);
prtd->dma_loaded--;
if (prtd->state & ST_RUNNING) {
/*by Vincent Hsiung for EQ Vol Change*/
#define HW_PARAMS_FLAG_EQVOL_ON 0x21
#define HW_PARAMS_FLAG_EQVOL_OFF 0x22
- if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
+
+ if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
{
return 0;
}
//ret = request_dma(prtd->params->channel, "i2s"); ///prtd->params->client->name);
ret = rk29_dma_request(prtd->params->channel, prtd->params->client, NULL);
+ DBG("Enter::%s, %d, ret=%d, Channel=%d\n", __FUNCTION__, __LINE__, ret, prtd->params->channel);
/*
if(ret){
for(prtd->params->channel=5;prtd->params->channel>0;prtd->params->channel--){
return 0;
if(substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- rk29_dma_devconfig(prtd->params->channel,
+ ret = rk29_dma_devconfig(prtd->params->channel,
RK29_DMASRC_MEM,
prtd->params->dma_addr);
}else{
- rk29_dma_devconfig(prtd->params->channel,
+ ret = rk29_dma_devconfig(prtd->params->channel,
RK29_DMASRC_HW,
prtd->params->dma_addr);
}
+ DBG("Enter::%s, %d, ret=%d, Channel=%d, Addr=0x%X\n", __FUNCTION__, __LINE__, ret, prtd->params->channel, prtd->params->dma_addr);
+ ret = rk29_dma_config(prtd->params->channel,
+ prtd->params->dma_size);
- rk29_dma_config(prtd->params->channel,
+ DBG("Enter:%s, %d, ret = %d, Channel=%d, Size=%d\n",
+ __FUNCTION__, __LINE__, ret, prtd->params->channel,
prtd->params->dma_size);
- rk29_dma_ctrl(prtd->params, RK29_DMAOP_FLUSH);
+
+ ret= rk29_dma_ctrl(prtd->params->channel, RK29_DMAOP_FLUSH);
+ DBG("Enter:%s, %d, ret = %d, Channel=%d\n",
+ __FUNCTION__, __LINE__, ret, prtd->params->channel);
prtd->dma_loaded = 0;
prtd->dma_pos = prtd->dma_start;
{
struct snd_pcm_runtime *runtime = substream->runtime;
struct rockchip_runtime_data *prtd = runtime->private_data;
- struct rockchip_dma_buf_set *sg_buf = NULL;
+ struct rockchip_dma_buf_set *sg_buf = NULL;
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
if (!prtd)
DBG("rockchip_pcm_close called with prtd == NULL\n");
- if (prtd)
+ if (prtd)
sg_buf = prtd->curr;
while (sg_buf != NULL) {
static int __init rockchip_soc_platform_init(void)
{
+ DBG("Enter::%s, %d\n", __FUNCTION__, __LINE__);
return snd_soc_register_platform(&rk29_soc_platform);
}
module_init(rockchip_soc_platform_init);
static int rk29_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
- struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
int ret;
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
/*by Vincent Hsiung for EQ Vol Change*/
#define HW_PARAMS_FLAG_EQVOL_ON 0x21
#define HW_PARAMS_FLAG_EQVOL_OFF 0x22
- if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
- {
- ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
- }
- else
- {
- /* set codec DAI configuration */
- #if defined (CONFIG_SND_CODEC_SOC_SLAVE)
- ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
- SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
- #endif
- #if defined (CONFIG_SND_CODEC_SOC_MASTER)
- ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
- SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM );
- #endif
- if (ret < 0)
- return ret;
- /* set cpu DAI configuration */
- #if defined (CONFIG_SND_CODEC_SOC_SLAVE)
- ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
- SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
- #endif
- #if defined (CONFIG_SND_CODEC_SOC_MASTER)
- ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
- SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
- #endif
- if (ret < 0)
- return ret;
+ if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
+ {
+ ret = codec_dai->ops->hw_params(substream, params, codec_dai); //by Vincent
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+ }
+ else
+ {
+ /* set codec DAI configuration */
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
+ ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ #endif
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
+ ret = codec_dai->ops->set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM );
+ #endif
+ if (ret < 0)
+ return ret;
+ /* set cpu DAI configuration */
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
+ ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+ #endif
+ #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
+ ret = cpu_dai->ops->set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+ #endif
+ if (ret < 0)
+ return ret;
}
return 0;
*/
static int rk29_rk1000_codec_init(struct snd_soc_codec *codec)
{
- struct snd_soc_dai *codec_dai = &codec->dai[0];
- int ret;
-
- DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
-
- ret = snd_soc_dai_set_sysclk(codec_dai, 0,
- 12000000, SND_SOC_CLOCK_IN);
- if (ret < 0) {
- printk(KERN_ERR "Failed to set WM8988 SYSCLK: %d\n", ret);
- return ret;
- }
-
- /* Add specific widgets */
- snd_soc_dapm_new_controls(codec, rk29_dapm_widgets,
- ARRAY_SIZE(rk29_dapm_widgets));
-
- /* Set up specific audio path audio_mapnects */
- snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
-
- snd_soc_dapm_sync(codec);
-
- return 0;
+ struct snd_soc_dai *codec_dai = &codec->dai[0];
+ int ret;
+
+ DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0,
+ 12000000, SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ printk(KERN_ERR "Failed to set WM8988 SYSCLK: %d\n", ret);
+ return ret;
+ }
+
+ /* Add specific widgets */
+ snd_soc_dapm_new_controls(codec, rk29_dapm_widgets,
+ ARRAY_SIZE(rk29_dapm_widgets));
+
+ /* Set up specific audio path audio_mapnects */
+ snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+
+ snd_soc_dapm_sync(codec);
+
+ return 0;
}
static struct snd_soc_ops rk29_ops = {
ret = platform_device_add(rk29_snd_device);
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
if (ret) {
- DBG("platform device add failed\n");
- platform_device_put(rk29_snd_device);
+ DBG("platform device add failed\n");
+ platform_device_put(rk29_snd_device);
}
return ret;
}
projects / firefly-linux-kernel-4.4.55.git / commitdiff