rk3188: Priority setting i2s under cpll to fix i2s frac div do not effect, let axi_cp...

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index 4d0f734e608b8d23d9ede3a8fbcbb22519621fea..10ddea3c72ea6f70f81bbbb6efc580bb175c5115 100755 (executable)
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -3413,10 +3413,14 @@ void rk30_clock_common_i2s_init(void)
                i2s_rate = 49152000;
        }
 
-       if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
-               clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
-       } else if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
+       /*
+        * Priority setting i2s under cpll to fix i2s frac div do not effect, let
+        * axi_cpu's pll different with i2s's
+        * */
+       if(((i2s_rate * 20) <= codec_pll_clk.rate) || !(codec_pll_clk.rate % i2s_rate)) {
                clk_set_parent_nolock(&clk_i2s_pll, &codec_pll_clk);
+       } else if(((i2s_rate * 20) <= general_pll_clk.rate) || !(general_pll_clk.rate % i2s_rate)) {
+               clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);
        } else {
                if(general_pll_clk.rate > codec_pll_clk.rate)
                        clk_set_parent_nolock(&clk_i2s_pll, &general_pll_clk);