#ifndef LLVM_CODEGEN_ASMPRINTER_H
#define LLVM_CODEGEN_ASMPRINTER_H
+#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Support/DataTypes.h"
-#include "llvm/ADT/DenseMap.h"
+#include "llvm/Target/TargetMachine.h"
#include <set>
namespace llvm {
std::set<const GlobalValue*> ExtWeakSymbols;
/// OptLevel - Generating code at a specific optimization level.
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
public:
/// Output stream on which we're printing assembly code.
///
protected:
explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V);
+ const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V);
public:
virtual ~AsmPrinter();
#define LLVM_CODEGEN_DWARFWRITER_H
#include "llvm/Pass.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
void EndFunction(MachineFunction *MF);
/// ValidDebugInfo - Return true if V represents valid debug info value.
- bool ValidDebugInfo(Value *V, unsigned OptLevel);
+ bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
/// RecordSourceLine - Register a source line with debug info. Returns a
/// unique label ID used to generate a label and provide correspondence to
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/GCs.h"
+#include "llvm/Target/TargetMachine.h"
namespace {
struct ForceCodegenLinking {
llvm::linkOcamlGC();
llvm::linkShadowStackGC();
- (void) llvm::createBURRListDAGScheduler(NULL, 3);
- (void) llvm::createTDRRListDAGScheduler(NULL, 3);
- (void) llvm::createTDListDAGScheduler(NULL, 3);
- (void) llvm::createFastDAGScheduler(NULL, 3);
- (void) llvm::createDefaultScheduler(NULL, 3);
+ (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
+ (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
}
} ForceCodegenLinking; // Force link by creating a global definition.
#define LLVM_CODEGENSCHEDULERREGISTRY_H
#include "llvm/CodeGen/MachinePassRegistry.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
class RegisterScheduler : public MachinePassRegistryNode {
public:
- typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
+ typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
+ CodeGenOpt::Level);
static MachinePassRegistry Registry;
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createFastDAGScheduler - This creates a "fast" scheduler.
///
ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
} // end namespace llvm
#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
-
+#include "llvm/Target/TargetMachine.h"
#include <cassert>
#include <vector>
#include <map>
class AliasAnalysis;
class TargetLowering;
-class TargetMachine;
class MachineModuleInfo;
class DwarfWriter;
class MachineFunction;
/// certain types of nodes together, or eliminating superfluous nodes. The
/// Level argument controls whether Combine is allowed to produce nodes and
/// types that are illegal on the target.
- void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
+ void Combine(CombineLevel Level, AliasAnalysis &AA,
+ CodeGenOpt::Level OptLevel);
/// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
/// only uses types natively supported by the target. Returns "true" if it
///
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
- void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
+ void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel);
/// RemoveDeadNodes - This method deletes all unreachable nodes in the
/// SelectionDAG.
MachineBasicBlock *BB;
AliasAnalysis *AA;
GCFunctionInfo *GFI;
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
static char ID;
- explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
+ explicit SelectionDAGISel(TargetMachine &tm,
+ CodeGenOpt::Level OL = CodeGenOpt::Default);
virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; }
#include <vector>
#include <map>
#include <string>
-#include "llvm/System/Mutex.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/System/Mutex.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
// libraries, the JIT and Interpreter set these functions to ctor pointers
// at startup time if they are linked in.
typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
static EECtorFn JITCtor, InterpCtor;
/// LazyFunctionCreator - If an unknown function is needed, this function
static ExecutionEngine *create(ModuleProvider *MP,
bool ForceInterpreter = false,
std::string *ErrorStr = 0,
- unsigned OptLevel = 3);
+ CodeGenOpt::Level OptLevel =
+ CodeGenOpt::Default);
/// create - This is the factory method for creating an execution engine which
/// is appropriate for the current machine. This takes ownership of the
static ExecutionEngine *createJIT(ModuleProvider *MP,
std::string *ErrorStr = 0,
JITMemoryManager *JMM = 0,
- unsigned OptLevel = 3);
-
-
-
+ CodeGenOpt::Level OptLevel =
+ CodeGenOpt::Default);
+
/// addModuleProvider - Add a ModuleProvider to the list of modules that we
/// can JIT from. Note that this takes ownership of the ModuleProvider: when
/// the ExecutionEngine is destroyed, it destroys the MP as well.
};
}
+// Code generation optimization level.
+namespace CodeGenOpt {
+ enum Level {
+ Default,
+ None,
+ One,
+ Two,
+ Size,
+ Aggressive,
+ LTO
+ };
+}
+
//===----------------------------------------------------------------------===//
///
/// TargetMachine - Primary interface to the complete machine description for
virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
raw_ostream &,
CodeGenFileType,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return FileModel::None;
}
///
virtual bool addPassesToEmitFileFinish(PassManagerBase &,
MachineCodeEmitter *,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return true;
}
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &,
MachineCodeEmitter &,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return true;
}
virtual bool WantsWholeFile() const { return false; }
virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
CodeGenFileType,
- unsigned /* OptLevel */) {
+ CodeGenOpt::Level) {
return true;
}
};
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
/// both emitting to assembly files or machine code output.
///
- bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
+ bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
public:
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
- /// generation. If OptLevel is 0, the code generator should emit code as fast
+ /// generation. If OptLevel is None, the code generator should emit code as fast
/// as possible, though the generated code may be less efficient. This method
/// should return FileModel::Error if emission of this file type is not
/// supported.
virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level);
/// addPassesToEmitFileFinish - If the passes to emit the specified file had
/// to be split up (e.g., to add an object writer pass), this method can be
///
virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
MachineCodeEmitter *MCE,
- unsigned OptLevel);
+ CodeGenOpt::Level);
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
/// get machine code emitted. This uses a MachineCodeEmitter object to handle
///
virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
MachineCodeEmitter &MCE,
- unsigned OptLevel);
+ CodeGenOpt::Level);
/// Target-Independent Code Generator Pass Configuration Options.
/// addInstSelector - This method should add any "last minute" LLVM->LLVM
/// passes, then install an instruction selector pass, which converts from
/// LLVM code to machine instructions.
- virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
return true;
}
/// addPreRegAllocPasses - This method may be implemented by targets that want
/// to run passes immediately before register allocation. This should return
/// true if -print-machineinstrs should print after these passes.
- virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
/// want to run passes after register allocation but before prolog-epilog
/// insertion. This should return true if -print-machineinstrs should print
/// after these passes.
- virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
- virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
+ virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
return false;
}
/// addAssemblyEmitter - This pass should be overridden by the target to add
/// the asmprinter, if asm emission is supported. If this is not supported,
/// 'true' should be returned.
- virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
+ virtual bool addAssemblyEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /* VerboseAsmDefault */, raw_ostream &) {
return true;
}
/// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be
/// returned. If DumpAsm is true, the generated assembly is printed to cerr.
- virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+ virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /*DumpAsm*/, MachineCodeEmitter &) {
return true;
}
/// a code emitter (without setting flags), if supported. If this is not
/// supported, 'true' should be returned. If DumpAsm is true, the generated
/// assembly is printed to cerr.
- virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
+ virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
bool /*DumpAsm*/, MachineCodeEmitter &) {
return true;
}
#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/SmallPtrSet.h"
char AsmPrinter::ID = 0;
AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
- const TargetAsmInfo *T, unsigned OL, bool VDef)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef)
: MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
IsInTextSection(false)
}
/// ValidDebugInfo - Return true if V represents valid debug info value.
- bool ValidDebugInfo(Value *V, unsigned OptLevel) {
+ bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
if (!V)
return false;
case DW_TAG_lexical_block:
/// FIXME. This interfers with the qualitfy of generated code when
/// during optimization.
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
return false;
default:
break;
}
/// ValidDebugInfo - Return true if V represents valid debug info value.
-bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
+bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
return DD && DD->ValidDebugInfo(V, OptLevel);
}
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
// Add common CodeGen passes.
if (addCommonCodeGenPasses(PM, OptLevel))
return FileModel::Error;
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
PM.add(createLoopAlignerPass());
switch (FileType) {
/// finish up adding passes to emit the file, if necessary.
bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
MachineCodeEmitter *MCE,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
if (MCE)
addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
///
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
MachineCodeEmitter &MCE,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
// Add common CodeGen passes.
if (addCommonCodeGenPasses(PM, OptLevel))
return true;
return false; // success!
}
-/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
-/// both emitting to assembly files or machine code output.
+/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
+/// emitting to assembly files or machine code output.
///
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
// Standard LLVM-Level Passes.
// Run loop strength reduction before anything else.
- if (OptLevel != 0) {
+ if (OptLevel != CodeGenOpt::None) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
// Enable FastISel with -fast, but allow that to be overridden.
if (EnableFastISelOption == cl::BOU_TRUE ||
- (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
+ (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
EnableFastISel = true;
// Ask the target for an isel.
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
- if (OptLevel != 0) {
+ if (OptLevel != CodeGenOpt::None) {
PM.add(createMachineLICMPass());
PM.add(createMachineSinkingPass());
}
PM.add(createRegisterAllocator());
// Perform stack slot coloring.
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
PM.add(createStackSlotColoringPass());
if (PrintMachineCode) // Print the register-allocated code
PM.add(createMachineFunctionPrinterPass(cerr));
// Second pass scheduler.
- if (OptLevel != 0 && !DisablePostRAScheduler) {
+ if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
PM.add(createPostRAScheduler());
if (PrintMachineCode)
}
// Branch folding must be run after regalloc and prolog/epilog insertion.
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
if (PrintMachineCode)
SelectionDAG &DAG;
const TargetLowering &TLI;
CombineLevel Level;
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
bool LegalOperations;
bool LegalTypes;
}
public:
- DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
+ DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
: DAG(D),
TLI(D.getTargetLoweringInfo()),
Level(Unrestricted),
SDValue Ptr = LD->getBasePtr();
// Try to infer better alignment information than the load already has.
- if (OptLevel != 0 && LD->isUnindexed()) {
+ if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
if (unsigned Align = InferAlignment(Ptr, DAG)) {
if (Align > LD->getAlignment())
return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
SDValue Ptr = ST->getBasePtr();
// Try to infer better alignment information than the store already has.
- if (OptLevel != 0 && ST->isUnindexed()) {
+ if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
if (unsigned Align = InferAlignment(Ptr, DAG)) {
if (Align > ST->getAlignment())
return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
// SelectionDAG::Combine - This is the entry point for the file.
//
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
/// run - This is the main entry point to this class.
///
DAGCombiner(*this, AA, OptLevel).Run(Level);
default: break;
case Intrinsic::dbg_stoppoint: {
DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
- if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
+ if (DW && DW->ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
std::string Dir, FN;
unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
}
case Intrinsic::dbg_region_start: {
DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
- if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
+ if (DW && DW->ValidDebugInfo(RSI->getContext(), CodeGenOpt::None)) {
unsigned ID =
DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
}
case Intrinsic::dbg_region_end: {
DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
- if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
+ if (DW && DW->ValidDebugInfo(REI->getContext(), CodeGenOpt::None)) {
unsigned ID = 0;
DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
Value *SP = FSI->getSubprogram();
- if (DW->ValidDebugInfo(SP, 0)) {
+ if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) {
// llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
// (most?) gdb expects.
DebugLoc PrevLoc = DL;
case Intrinsic::dbg_declare: {
DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
Value *Variable = DI->getVariable();
- if (DW && DW->ValidDebugInfo(Variable, 0)) {
+ if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) {
// Determine the address of the declared object.
Value *Address = DI->getAddress();
if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
class VISIBILITY_HIDDEN SelectionDAGLegalize {
TargetLowering &TLI;
SelectionDAG &DAG;
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
bool TypesNeedLegalizing;
// Libcall insertion helpers.
public:
explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
- unsigned ol);
+ CodeGenOpt::Level ol);
/// getTypeAction - Return how we should legalize values of this type, either
/// it is already legal or we need to expand it into multiple registers of
}
SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
- bool types, unsigned ol)
+ bool types, CodeGenOpt::Level ol)
: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
assert(MVT::LAST_VALUETYPE <= 32 &&
unsigned Line = DSP->getLine();
unsigned Col = DSP->getColumn();
- if (OptLevel == 0) {
+ if (OptLevel == CodeGenOpt::None) {
// A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
// won't hurt anything.
if (useDEBUG_LOC) {
// SelectionDAG::Legalize - This is the entry point for the file.
//
-void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
+void SelectionDAG::Legalize(bool TypesNeedLegalizing,
+ CodeGenOpt::Level OptLevel) {
/// run - This is the main entry point to this class.
///
SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
//===----------------------------------------------------------------------===//
llvm::ScheduleDAGSDNodes *
-llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
return new ScheduleDAGFast(*IS->MF);
}
/// new hazard recognizer. This scheduler takes ownership of the hazard
/// recognizer and deletes it when done.
ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
return new ScheduleDAGList(*IS->MF,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());
//===----------------------------------------------------------------------===//
llvm::ScheduleDAGSDNodes *
-llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
}
llvm::ScheduleDAGSDNodes *
-llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
+llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetMachine &TM = IS->TM;
const TargetInstrInfo *TII = TM.getInstrInfo();
const TargetRegisterInfo *TRI = TM.getRegisterInfo();
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetIntrinsicInfo.h"
#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
DwarfWriter *DW = DAG.getDwarfWriter();
DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
- if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
+ if (DW && DW->ValidDebugInfo(SPI->getContext(),
+ CodeGenOpt::Default)) {
DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
std::string Dir, FN;
unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
Value *SP = FSI->getSubprogram();
- if (DW->ValidDebugInfo(SP, false)) {
+ if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) {
DISubprogram Subprogram(cast<GlobalVariable>(SP));
DICompileUnit CU(Subprogram.getCompileUnit());
std::string Dir, FN;
DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
MachineFunction &MF = DAG.getMachineFunction();
- if (OptLevel == 0)
+ if (OptLevel == CodeGenOpt::None)
DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
SPI.getLine(),
SPI.getColumn(),
&& strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
// This is end of inlined function. Debugging information for
// inlined function is not handled yet (only supported by FastISel).
- if (OptLevel == 0) {
+ if (OptLevel == CodeGenOpt::None) {
unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
if (ID != 0)
// Returned ID is 0 if this is unbalanced "end of inlined
Value *SP = FSI.getSubprogram();
if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
MachineFunction &MF = DAG.getMachineFunction();
- if (OptLevel == 0) {
+ if (OptLevel == CodeGenOpt::None) {
// llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
// (most?) gdb expects.
DebugLoc PrevLoc = CurDebugLoc;
return 0;
}
case Intrinsic::dbg_declare: {
- if (OptLevel == 0) {
+ if (OptLevel == CodeGenOpt::None) {
DwarfWriter *DW = DAG.getDwarfWriter();
DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
Value *Variable = DI.getVariable();
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/Support/CallSite.h"
+#include "llvm/Target/TargetMachine.h"
#include <vector>
#include <set>
/// OptLevel - What optimization level we're generating code for.
///
- unsigned OptLevel;
+ CodeGenOpt::Level OptLevel;
/// GFI - Garbage collection metadata for the function.
GCFunctionInfo *GFI;
SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
- FunctionLoweringInfo &funcinfo, unsigned ol)
+ FunctionLoweringInfo &funcinfo,
+ CodeGenOpt::Level ol)
: CurDebugLoc(DebugLoc::getUnknownLoc()),
TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
}
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
const TargetLowering &TLI = IS->getTargetLowering();
- if (OptLevel == 0)
+ if (OptLevel == CodeGenOpt::None)
return createFastDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
return createTDListDAGScheduler(IS, OptLevel);
// SelectionDAGISel code
//===----------------------------------------------------------------------===//
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
FuncInfo(new FunctionLoweringInfo(TLI)),
CurDAG(new SelectionDAG(TLI, *FuncInfo)),
if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
ComputeLiveOutVRegInfo();
// Third, instruction select all of the operations to machine code, adding the
ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
bool ForceInterpreter,
std::string *ErrorStr,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
ExecutionEngine *EE = 0;
// Make sure we can resolve symbols in the program as well. The zero arg
int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
LLVMModuleProviderRef MP,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
char **OutError) {
std::string Error;
if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP), &Error, 0,
/// create - Create a new interpreter object. This can never fail.
///
ExecutionEngine *Interpreter::create(ModuleProvider *MP, std::string* ErrStr,
- unsigned OptLevel /*unused*/) {
+ CodeGenOpt::Level OptLevel /*unused*/) {
// Tell this ModuleProvide to materialize and release the module
if (!MP->materializeModule(ErrStr))
// We got an error, just return 0
/// create - Create an interpreter ExecutionEngine. This can never fail.
///
static ExecutionEngine *create(ModuleProvider *M, std::string *ErrorStr = 0,
- unsigned OptLevel /*unused*/ = 3);
+ CodeGenOpt::Level = CodeGenOpt::Default);
/// run - Start execution with the specified function and arguments.
///
ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
std::string *ErrorStr,
JITMemoryManager *JMM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel);
if (!EE) return 0;
}
JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
- JITMemoryManager *JMM, unsigned OptLevel)
+ JITMemoryManager *JMM, CodeGenOpt::Level OptLevel)
: ExecutionEngine(MP), TM(tm), TJI(tji) {
setTargetData(TM.getTargetData());
// Turn the machine code intermediate representation into bytes in memory
// that may be executed.
- if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
+ if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
cerr << "Target does not support machine code emission!\n";
abort();
}
// Turn the machine code intermediate representation into bytes in memory
// that may be executed.
- if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
+ if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
cerr << "Target does not support machine code emission!\n";
abort();
}
// Turn the machine code intermediate representation into bytes in memory
// that may be executed.
- if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
+ if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
cerr << "Target does not support machine code emission!\n";
abort();
}
JITState *jitstate;
JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
- JITMemoryManager *JMM, unsigned OptLevel);
+ JITMemoryManager *JMM, CodeGenOpt::Level OptLevel);
public:
~JIT();
/// for the current target. Otherwise, return null.
///
static ExecutionEngine *create(ModuleProvider *MP, std::string *Err,
- unsigned OptLevel = 3) {
+ CodeGenOpt::Level OptLevel =
+ CodeGenOpt::Default) {
return createJIT(MP, Err, 0, OptLevel);
}
MachineCodeEmitter *getCodeEmitter() const { return MCE; }
static ExecutionEngine *createJIT(ModuleProvider *MP, std::string *Err,
- JITMemoryManager *JMM, unsigned OptLevel);
+ JITMemoryManager *JMM,
+ CodeGenOpt::Level OptLevel);
private:
static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM);
/// available for the current target. Otherwise, return null.
///
ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string *ErrorStr,
- JITMemoryManager *JMM, unsigned OptLevel) {
+ JITMemoryManager *JMM,
+ CodeGenOpt::Level OptLevel) {
const TargetMachineRegistry::entry *TheArch = MArch;
if (TheArch == 0) {
std::string Error;
#ifndef TARGET_ARM_H
#define TARGET_ARM_H
+#include "llvm/Target/TargetMachine.h"
#include <cassert>
namespace llvm {
FunctionPass *createARMISelDag(ARMTargetMachine &TM);
FunctionPass *createARMCodePrinterPass(raw_ostream &O,
ARMTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
MachineCodeEmitter &MCE);
FunctionPass *createARMLoadStoreOptimizationPass();
// Pass Pipeline Configuration
-bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
PM.add(createARMISelDag(*this));
return false;
}
-bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
- if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
+ if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
PM.add(createARMLoadStoreOptimizationPass());
- if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
+ if (OptLevel != CodeGenOpt::None &&
+ !DisableIfConversion && !Subtarget.isThumb())
PM.add(createIfConverterPass());
PM.add(createARMConstantIslandPass());
}
bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.
}
-bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE) {
+bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
if (DefRelocModel == Reloc::Default)
setRelocationModel(Reloc::Static);
}
bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm,
MachineCodeEmitter &MCE) {
// Machine code emitter pass for ARM.
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
ARMTargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
virtual const TargetAsmInfo *createTargetAsmInfo() const;
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE);
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ MachineCodeEmitter &MCE);
};
/// ThumbTargetMachine - Thumb target machine.
bool InCPMode;
public:
explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
InCPMode(false) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
///
FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
ARMTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
#ifndef TARGET_ALPHA_H
#define TARGET_ALPHA_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class AlphaTargetMachine;
class FunctionPass;
- class TargetMachine;
class MachineCodeEmitter;
class raw_ostream;
FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
TargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
MachineCodeEmitter &MCE);
//===----------------------------------------------------------------------===//
bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
PM.add(createAlphaISelDag(*this));
return false;
}
bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer
PM.add(createAlphaBranchSelectionPass());
return false;
}
bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createAlphaLLRPPass(*this));
PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
return false;
}
-bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
PM.add(createAlphaCodeEmitterPass(*this, MCE));
if (DumpAsm)
return false;
}
bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- unsigned OptLevel, bool DumpAsm,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
MachineCodeEmitter &MCE) {
return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
}
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE);
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
+ MachineCodeEmitter &MCE);
};
} // end namespace llvm
///
explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(o, tm, T, OL, V) {}
virtual const char *getPassName() const {
///
FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
raw_ostream &o,
CodeGenFileType FileType,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
if (FileType != TargetMachine::AssemblyFile) return true;
PM.add(createGCLoweringPass());
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
// This class always works, but must be requested explicitly on
// llc command line.
std::set<std::string> FnStubs, GVStubs;
public:
explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V) :
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V) :
AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
DwarfWriter *DW;
MachineModuleInfo *MMI;
public:
- LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
- const TargetAsmInfo *T, bool F, bool V)
+ explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
+ const TargetAsmInfo *T, CodeGenOpt::Level F,
+ bool V)
: SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
virtual const char *getPassName() const {
///
FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
SPUTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
#define LLVM_TARGET_IBMCELLSPU_H
#include "llvm/Support/DataTypes.h"
+#include "llvm/Target/TargetMachine.h"
namespace llvm {
class SPUTargetMachine;
FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
SPUTargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
/*--== Utility functions/predicates/etc used all over the place: --==*/
//! Predicate test for a signed 10-bit value
//===----------------------------------------------------------------------===//
bool
-SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
+SPUTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel)
{
// Install an instruction selector.
PM.add(createSPUISelDag(*this));
}
bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
raw_ostream &o,
CodeGenFileType FileType,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
if (FileType != TargetMachine::AssemblyFile) return true;
PM.add(new CppWriter(o));
return false;
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
// This class always works, but shouldn't be the default in most cases.
static unsigned getModuleMatchQuality(const Module &M) { return 1; }
#include "llvm/CodeGen/DwarfWriter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetAsmInfo.h"
-#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Mangler.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/ADT/Statistic.h"
std::set<std::string> ExternalFunctionNames, ExternalObjectNames;
public:
explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
///
FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
IA64TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
#ifndef TARGET_IA64_H
#define TARGET_IA64_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class IA64TargetMachine;
///
FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
IA64TargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
} // End llvm namespace
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
+bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel){
PM.add(createIA64DAGToDAGInstructionSelector(*this));
return false;
}
-bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
+bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Make sure everything is bundled happily
PM.add(createIA64BundlingPass(*this));
return true;
}
bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
} // End llvm namespace
virtual bool WantsWholeFile() const { return true; }
virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
CodeGenFileType FileType,
- unsigned OptLevel);
+ CodeGenOpt::Level OptLevel);
// This class always works, but shouldn't be the default in most cases.
static unsigned getModuleMatchQuality(const Module &M) { return 1; }
bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
CodeGenFileType FileType,
- unsigned OptLevel)
+ CodeGenOpt::Level OptLevel)
{
if (FileType != TargetMachine::AssemblyFile) return true;
MSILWriter* Writer = new MSILWriter(o);
const MipsSubtarget *Subtarget;
public:
explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {
Subtarget = &TM.getSubtarget<MipsSubtarget>();
}
/// regardless of whether the function is in SSA form.
FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
MipsTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
#ifndef TARGET_MIPS_H
#define TARGET_MIPS_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class MipsTargetMachine;
class FunctionPass;
FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
MipsTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
} // end namespace llvm;
// Defines symbolic names for Mips registers. This defines a mapping from
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsTargetMachine::
-addInstSelector(PassManagerBase &PM, unsigned OptLevel)
+addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
{
PM.add(createMipsISelDag(*this));
return false;
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
bool MipsTargetMachine::
-addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
+addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
{
PM.add(createMipsDelaySlotFillerPass(*this));
return true;
// Implements the AssemblyEmitter for the target. Must return
// true if AssemblyEmitter is supported
bool MipsTargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out)
{
// Output assembly language.
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
#ifndef LLVM_TARGET_PIC16_H
#define LLVM_TARGET_PIC16_H
+#include "llvm/Target/TargetMachine.h"
#include <iosfwd>
#include <cassert>
FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
PIC16TargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
} // end namespace llvm;
// Defines symbolic names for PIC16 registers. This defines a mapping from
///
FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
PIC16TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
namespace llvm {
struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {
CurBank = "";
FunctionLabelBegin = '@';
}
bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createPIC16ISelDag(*this));
return false;
}
bool PIC16TargetMachine::
-addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
- raw_ostream &Out) {
+addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
+ bool Verbose, raw_ostream &Out) {
// Output assembly language.
PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
return false;
return const_cast<PIC16TargetLowering*>(&TLInfo);
}
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
}; // PIC16TargetMachine.
const PPCSubtarget &Subtarget;
public:
explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V),
Subtarget(TM.getSubtarget<PPCSubtarget>()) {}
MachineModuleInfo *MMI;
public:
explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
virtual const char *getPassName() const {
raw_ostream &OS;
public:
explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
virtual const char *getPassName() const {
///
FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
PPCTargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>();
if (Subtarget->isDarwin()) {
// GCC #defines PPC on Linux but we use it as our namespace name
#undef PPC
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class PPCTargetMachine;
class FunctionPass;
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
PPCTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel, bool Verbose);
FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
MachineCodeEmitter &MCE);
} // end namespace llvm;
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createPPCISelDag(*this));
return false;
}
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
-
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Must run branch selection immediately preceding the asm printer.
PM.add(createPPCBranchSelectionPass());
return false;
}
bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
assert(AsmPrinterCtor && "AsmPrinter was not linked in");
return false;
}
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
// FIXME: This should be moved to TargetJITInfo!!
return false;
}
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// Machine code emitter pass for PowerPC.
PM.add(createPPCCodeEmitterPass(*this, MCE));
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
PPCTargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
}
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
virtual bool getEnableTailMergeDefault() const;
};
ValueMapTy NumberForBB;
public:
explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
///
FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
TargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
#ifndef TARGET_SPARC_H
#define TARGET_SPARC_H
+#include "llvm/Target/TargetMachine.h"
#include <cassert>
namespace llvm {
class FunctionPass;
- class TargetMachine;
class SparcTargetMachine;
class raw_ostream;
FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
} // end namespace llvm;
}
bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
PM.add(createSparcISelDag(*this));
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.
-bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
+bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel){
PM.add(createSparcFPMoverPass(*this));
PM.add(createSparcDelaySlotFillerPass(*this));
return true;
}
bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
const X86Subtarget *Subtarget;
public:
explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
}
///
FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
if (Subtarget->isFlavorIntel()) {
struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
#ifndef TARGET_X86_H
#define TARGET_X86_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class X86TargetMachine;
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel);
/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into
///
FunctionPass *createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified MCE object.
bool OptForSize;
public:
- explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
+ explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(tm, OptLevel),
TM(tm), X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget<X86Subtarget>()),
bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
SDNode *Root) const {
- if (OptLevel == 0) return false;
+ if (OptLevel == CodeGenOpt::None) return false;
if (U == Root)
switch (U->getOpcode()) {
OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
DEBUG(BB->dump());
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
PreprocessForRMW();
// FIXME: This should only happen when not compiled with -O0.
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
+ llvm::CodeGenOpt::Level OptLevel) {
return new X86DAGToDAGISel(TM, OptLevel);
}
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel));
return false;
}
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Calculate and set max stack object alignment early, so we can decide
// whether we will need stack realignment (and thus FP).
PM.add(createX86MaxStackAlignmentCalculatorPass());
return false; // -print-machineinstr shouldn't print after this.
}
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
PM.add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
assert(AsmPrinterCtor && "AsmPrinter was not linked in");
return false;
}
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
// On Darwin, do not override 64-bit setting made in X86TargetMachine().
}
bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- unsigned OptLevel, bool DumpAsm,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
MachineCodeEmitter &MCE) {
PM.add(createX86CodeEmitterPass(*this, MCE));
if (DumpAsm) {
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
}
// Set up the pass pipeline.
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
/// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
#ifndef TARGET_XCORE_H
#define TARGET_XCORE_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class FunctionPass;
class TargetMachine;
FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
XCoreTargetMachine &TM,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
} // end namespace llvm;
// Defines symbolic names for XCore registers. This defines a mapping from
DwarfWriter *DW;
const XCoreSubtarget &Subtarget;
public:
- XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ explicit XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0),
Subtarget(*TM.getSubtargetImpl()) {}
///
FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
XCoreTargetMachine &tm,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool verbose) {
return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
}
}
bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
- unsigned OptLevel) {
+ CodeGenOpt::Level OptLevel) {
PM.add(createXCoreISelDag(*this));
return false;
}
bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
// Output assembly language.
static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
};
static cl::opt<bool> Force("f", cl::desc("Overwrite output files"));
// Determine optimization level. Level -O0 is equivalent to "fast" code gen.
-static cl::opt<unsigned>
+static cl::opt<char>
OptLevel("O",
- cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
+ cl::desc("Optimization level. Similar to llvm-gcc -O."),
cl::Prefix,
cl::ZeroOrMore,
- cl::init(3));
+ cl::init(' '));
static cl::opt<std::string>
TargetTriple("mtriple", cl::desc("Override target triple for module"));
raw_ostream *Out = GetOutputStream(argv[0]);
if (Out == 0) return 1;
+ CodeGenOpt::Level OLvl = CodeGenOpt::Aggressive;
+
+ switch (OptLevel) {
+ default:
+ case ' ': break;
+ case '0': OLvl = CodeGenOpt::None; break;
+ case '1': OLvl = CodeGenOpt::One; break;
+ case '2': OLvl = CodeGenOpt::Two; break;
+ case 's': OLvl = CodeGenOpt::Size; break;
+ case '3': OLvl = CodeGenOpt::Aggressive; break;
+ case '4': OLvl = CodeGenOpt::LTO; break;
+ }
+
// If this target requires addPassesToEmitWholeFile, do it now. This is
// used by strange things like the C backend.
if (Target.WantsWholeFile()) {
PM.add(createVerifierPass());
// Ask the target to add backend passes as necessary.
- if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
+ if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OLvl)) {
std::cerr << argv[0] << ": target does not support generation of this"
<< " file type!\n";
if (Out != &outs()) delete Out;
// Override default to generate verbose assembly.
Target.setAsmVerbosityDefault(true);
- switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
+ switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OLvl)) {
default:
assert(0 && "Invalid file model!");
return 1;
break;
}
- if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
+ if (Target.addPassesToEmitFileFinish(Passes, MCE, OLvl)) {
std::cerr << argv[0] << ": target does not support generation of this"
<< " file type!\n";
if (Out != &outs()) delete Out;
if (!TargetTriple.empty())
Mod->setTargetTriple(TargetTriple);
- EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg, Fast);
+ EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg,
+ Fast ?
+ CodeGenOpt::None : CodeGenOpt::Aggressive);
if (!EE && !ErrorMsg.empty()) {
std::cerr << argv[0] << ":error creating EE: " << ErrorMsg << "\n";
exit(1);
MachineCodeEmitter* mce = NULL;
switch (_target->addPassesToEmitFile(*codeGenPasses, out,
- TargetMachine::AssemblyFile, 3)) {
+ TargetMachine::AssemblyFile,
+ CodeGenOpt::Default)) {
case FileModel::MachOFile:
mce = AddMachOWriter(*codeGenPasses, out, *_target);
break;
return true;
}
- if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, 3)) {
+ if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce,
+ CodeGenOpt::Default)) {
errMsg = "target does not support generation of this file type";
return true;
}
O << "\";\n\n";
O << " if (TAI->doesSupportDebugInformation() &&\n"
- << " DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
+ << " DW->ShouldEmitDwarfDebug() && OptLevel != CodeGenOpt::None) {\n"
<< " DebugLoc CurDL = MI->getDebugLoc();\n\n"
<< " if (!CurDL.isUnknown()) {\n"
<< " static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"
NumInputRootOps = N->getNumChildren();
if (DisablePatternForFastISel(N, CGP))
- emitCheck("OptLevel != 0");
+ emitCheck("OptLevel != CodeGenOpt::None");
emitCheck(PredicateCheck);
}
projects / oota-llvm.git / commitdiff