Make LowerSubregs' debug output for EXTRACT_SUBREG consistent with

that of INSERT_SUBREG and SUBREG_TO_REG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61218 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 0cb6aab6db5d249809af27cb9a06e3210c4bd2c6..77e8d65f590ce7a6bf4c46546d80af77d5daa590 100644 (file)
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -80,7 +80,11 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
          
   DOUT << "subreg: CONVERTING: " << *MI;
 
-  if (SrcReg != DstReg) {
+  if (SrcReg == DstReg) {
+    // No need to insert an identify copy instruction.
+    DOUT << "subreg: eliminated!";
+  } else {
+    // Insert copy
     const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
     assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
             "Extract subreg and Dst must be of same register class");
@@ -177,6 +181,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
     TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+
 #ifndef NDEBUG
     MachineBasicBlock::iterator dMI = MI;
     DOUT << "subreg: " << *(--dMI);