/// FIXME: This should obviously be autogenerated by tablegen when patterns
/// are available!
- MachineBasicBlock& MBB = *MI->getParent();
if (i == 0) {
switch(MI->getOpcode()) {
case X86::XCHG8rr: return MakeMRInst(X86::XCHG8mr ,FrameIndex, MI);
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
- virtual X86TargetLowering *getTargetLowering() { return &TLInfo; }
+ virtual X86TargetLowering *getTargetLowering() const {
+ return const_cast<X86TargetLowering*>(&TLInfo);
+ }
virtual const MRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}