rk3066b: add loader config dump support

diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c
index 5a244dff2e3001edcb41aa83f8f1a1ffa49d919f..fa91dcfb6ba4eb39b114f71cd7cb111ef460d7ac 100644 (file)
--- a/arch/arm/mach-rk30/clock_data-rk3066b.c
+++ b/arch/arm/mach-rk30/clock_data-rk3066b.c
@@ -3156,6 +3156,7 @@ static struct clk def_ops_clk = {
 #ifdef CONFIG_PROC_FS
 struct clk_dump_ops dump_ops;
 #endif
+void rk_dump_clock_info(void);
 
 void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int flags)
 {
@@ -3181,7 +3182,11 @@ void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int fl
         * enable other clocks as necessary
         */
        rk30_init_enable_clocks();
-
+#if 0
+       // print loader config
+       rk_dump_clock_info();
+       while(1);
+#endif
        /*
         * Disable any unused clocks left on by the bootloader
         */
@@ -3220,6 +3225,84 @@ early_param("armclk", armclk_setup);
 #endif
 
 
+static void rk_dump_clock(struct clk *clk, int deep, const struct list_head *root_clocks)
+{
+       struct clk *ck;
+       int i;
+       unsigned long rate = clk->rate;
+       //CLKDATA_DBG("dump_clock %s\n",clk->name);
+       for (i = 0; i < deep; i++)
+               printk("    ");
+
+       printk("%-11s ", clk->name);
+#ifndef RK30_CLK_OFFBOARD_TEST
+       if (clk->flags & IS_PD) {
+               printk("%s ", pmu_power_domain_is_on(clk->gate_idx) ? "on " : "off");
+       }
+#endif
+       if ((clk->mode == gate_mode) && (clk->gate_idx < CLK_GATE_MAX)) {
+               int idx = clk->gate_idx;
+               u32 v;
+               v = cru_readl(CLK_GATE_CLKID_CONS(idx)) & ((0x1) << (idx % 16));
+               printk("%s ", v ? "off" : "on ");
+       }
+
+       if (clk->pll) {
+               u32 pll_mode;
+               u32 pll_id = clk->pll->id;
+               pll_mode = cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id);
+               if (pll_mode == (PLL_MODE_SLOW(pll_id) & PLL_MODE_MSK(pll_id)))
+                       printk("slow   ");
+               else if (pll_mode == (PLL_MODE_NORM(pll_id) & PLL_MODE_MSK(pll_id)))
+                       printk("normal ");
+               else if (pll_mode == (PLL_MODE_DEEP(pll_id) & PLL_MODE_MSK(pll_id)))
+                       printk("deep   ");
+
+               if(cru_readl(PLL_CONS(pll_id, 3)) & PLL_BYPASS)
+                       printk("bypass ");
+       } else if(clk == &clk_ddr) {
+               rate = clk->recalc(clk);
+       }
+
+       if (rate >= MHZ) {
+               if (rate % MHZ)
+                       printk("%ld.%06ld MHz", rate / MHZ, rate % MHZ);
+               else
+                       printk("%ld MHz", rate / MHZ);
+       } else if (rate >= KHZ) {
+               if (rate % KHZ)
+                       printk("%ld.%03ld KHz", rate / KHZ, rate % KHZ);
+               else
+                       printk("%ld KHz", rate / KHZ);
+       } else {
+               printk("%ld Hz", rate);
+       }
+
+       printk(" usecount = %d", clk->usecount);
+
+       if (clk->parent)
+               printk(" parent = %s", clk->parent->name);
+
+       printk("\n");
+
+       list_for_each_entry(ck, root_clocks, node) {
+               if (ck->parent == clk)
+                       rk_dump_clock(ck, deep + 1, root_clocks);
+       }
+}
+
+#if 1
+struct list_head *get_rk_clocks_head(void);
+
+void rk_dump_clock_info(void)
+{
+       struct clk* clk;
+       list_for_each_entry(clk, get_rk_clocks_head(), node) {
+               if (!clk->parent)
+               rk_dump_clock(clk, 0,get_rk_clocks_head());
+       }
+}
+#endif
 
 #ifdef CONFIG_PROC_FS