ath9k_hw: Configure xpa bias level for AR9485
authorVasanthakumar Thiagarajan <vasanth@atheros.com>
Mon, 6 Dec 2010 12:27:48 +0000 (04:27 -0800)
committerJohn W. Linville <linville@tuxdriver.com>
Tue, 7 Dec 2010 21:34:56 +0000 (16:34 -0500)
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
drivers/net/wireless/ath/ath9k/ar9003_phy.h

index 372831dc94bd58e2c09c676c4dccf84e7b158c73..819b0a6cb83eabdb5a1ef73e6d9fc64398b4376b 100644 (file)
@@ -3450,9 +3450,15 @@ static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 {
        int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
-       REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
-       REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
-       REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
+
+       if (AR_SREV_9485(ah))
+               REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+       else {
+               REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
+               REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
+                             bias >> 2);
+               REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
+       }
 }
 
 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
index 3394dfe52b42052657208f46361e4a082b2954ce..b7720819872bdc0b809b9f6db415518966ce261f 100644 (file)
 #define AR_PHY_65NM_CH2_RXTX1       0x16900
 #define AR_PHY_65NM_CH2_RXTX2       0x16904
 
+#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
+#define AR_CH0_TOP2_XPABIASLVL         0xf000
+#define AR_CH0_TOP2_XPABIASLVL_S       12
+
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT         0x00380000
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S       19
 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT         0x00c00000