Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI

I looked into adding a warning / error for this to FileCheck, but there doesn't
seem to be a good way to avoid it triggering on the instances of it in RUN lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244481 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Analysis/BasicAA/noalias-bugs.ll b/test/Analysis/BasicAA/noalias-bugs.ll
index acb230c45de45576d130ae5644eb1478d9cf1a9d..71b3c443f5427fb8748325af698f1348e2a5bad7 100644 (file)
--- a/test/Analysis/BasicAA/noalias-bugs.ll
+++ b/test/Analysis/BasicAA/noalias-bugs.ll
@@ -24,7 +24,7 @@ define i64 @testcase(%nested * noalias %p1, %nested * noalias %p2,
 
 ; CHECK: store i64 2
 ; CHECK: load
-; CHECK; store i64 1
+; CHECK: store i64 1
 
   store i64 2, i64* %ptr.64, align 8
   %r = load i64, i64* %either_ptr.64, align 8

diff --git a/test/CodeGen/AArch64/arm64-addr-type-promotion.ll b/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
index 4703d25a6016be03d671bb2564a8b8f7a17eeaf7..1a9074beb406e098dd3d51bc9efadc78a74a0052 100644 (file)
--- a/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
+++ b/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
@@ -13,8 +13,8 @@ define zeroext i8 @fullGtU(i32 %i1, i32 %i2) {
 ; CHECK-NEXT: ldr [[BLOCKBASE:x[0-9]+]], {{\[}}[[ADDR]]]
 ; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]],  w0, sxtw]
 ; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], w1, sxtw]
-; CHECK-NEXT cmp [[BLOCKVAL1]], [[BLOCKVAL2]]
-; CHECK-NEXT b.ne
+; CHECK-NEXT: cmp [[BLOCKVAL1]], [[BLOCKVAL2]]
+; CHECK-NEXT: b.ne
 ; Next BB
 ; CHECK: add [[BLOCKBASE2:x[0-9]+]], [[BLOCKBASE]], w1, sxtw
 ; CHECK-NEXT: add [[BLOCKBASE1:x[0-9]+]], [[BLOCKBASE]], w0, sxtw

diff --git a/test/CodeGen/AArch64/arm64-popcnt.ll b/test/CodeGen/AArch64/arm64-popcnt.ll
index d6c9471b7a19a0724aaa7ca4ba14ff5ce74fe6c6..9ee53a0f92e6bec52d999bb395705f278a919cab 100644 (file)
--- a/test/CodeGen/AArch64/arm64-popcnt.ll
+++ b/test/CodeGen/AArch64/arm64-popcnt.ll
@@ -59,7 +59,7 @@ define i32 @cnt32(i32 %x) nounwind readnone noimplicitfloat {
   %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %cnt
 ; CHECK-LABEL: cnt32:
-; CHECK-NOT 16b
+; CHECK-NOT: 16b
 ; CHECK: ret
 }
 
@@ -67,7 +67,7 @@ define i64 @cnt64(i64 %x) nounwind readnone noimplicitfloat {
   %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
   ret i64 %cnt
 ; CHECK-LABEL: cnt64:
-; CHECK-NOT 16b
+; CHECK-NOT: 16b
 ; CHECK: ret
 }
 

diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll
index 991742135623ff0efe7acb2a8e030bd854304d34..614966d402478d8b4fbf28192a0f1532cb5247e4 100644 (file)
--- a/test/CodeGen/ARM/fold-stack-adjust.ll
+++ b/test/CodeGen/ARM/fold-stack-adjust.ll
@@ -62,7 +62,7 @@ define void @check_vfp_fold() minsize {
 ; ...
 ; CHECK-NOT: add sp,
 ; CHECK: vpop {d6, d7, d8, d9}
-; CHECKL pop {r[[GLOBREG]], pc}
+; CHECK: pop {r[[GLOBREG]], pc}
 
   ; iOS uses aligned NEON stores here, which is convenient since we
   ; want to make sure that works too.

diff --git a/test/CodeGen/NVPTX/vector-call.ll b/test/CodeGen/NVPTX/vector-call.ll
index a03d7fd41914e9dc1582c509e94479e40ab6a586..968d1d4a5f51a7eaa3f56dd6b32f2d6548366264 100644 (file)
--- a/test/CodeGen/NVPTX/vector-call.ll
+++ b/test/CodeGen/NVPTX/vector-call.ll
@@ -4,7 +4,7 @@ target triple = "nvptx-unknown-cuda"
 
 declare void @bar(<4 x i32>)
 
-; CHECK-LABEL @foo
+; CHECK-LABEL: @foo
 define void @foo(<4 x i32> %a) {
 ; CHECK: st.param.v4.b32
   tail call void @bar(<4 x i32> %a)

diff --git a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
index ad8ed38da7fa823b7847372f523bed29e950b9f1..028006320cb526b7e380db44cd17a25c97466e87 100644 (file)
--- a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
+++ b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
@@ -10,7 +10,7 @@ define void @main() {
 }
 
 ; CHECK-LABEL: @main
-; CHECK-DAG li 4, 0
+; CHECK-DAG: li 4, 0
 ; CHECK-DAG: crxor 6, 6, 6
 ; CHECK: bl printf
 

diff --git a/test/CodeGen/PowerPC/rm-zext.ll b/test/CodeGen/PowerPC/rm-zext.ll
index 97c546c0145fe4600119769a54e2c966344172e0..df5fe4f7a154a2893cd249ef75e9ff2631295b8c 100644 (file)
--- a/test/CodeGen/PowerPC/rm-zext.ll
+++ b/test/CodeGen/PowerPC/rm-zext.ll
@@ -9,7 +9,7 @@ entry:
   %shr2 = lshr i32 %mul, 5
   ret i32 %shr2
 
-; CHECK-LABEL @foo
+; CHECK-LABEL: @foo
 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
 ; CHECK: blr
 }
@@ -23,7 +23,7 @@ entry:
   %or = or i32 %shr, %shl
   ret i32 %or
 
-; CHECK-LABEL @test6
+; CHECK-LABEL: @test6
 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
 ; CHECK: blr
 }
@@ -34,7 +34,7 @@ entry:
   %cond = select i1 %cmp, i32 %a, i32 %b
   ret i32 %cond
 
-; CHECK-LABEL @min
+; CHECK-LABEL: @min
 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
 ; CHECK: blr
 }

diff --git a/test/CodeGen/PowerPC/sdiv-pow2.ll b/test/CodeGen/PowerPC/sdiv-pow2.ll
index 5ec019dfb4af10e603548666392dbd150830f1f9..d1f60da6c740ba04c2e4da288385bf803975e98a 100644 (file)
--- a/test/CodeGen/PowerPC/sdiv-pow2.ll
+++ b/test/CodeGen/PowerPC/sdiv-pow2.ll
@@ -9,7 +9,7 @@ entry:
   %div = sdiv i32 %a, 8
   ret i32 %div
 
-; CHECK-LABEL @foo4
+; CHECK-LABEL: @foo4
 ; CHECK: srawi [[REG1:[0-9]+]], 3, 3
 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
 ; CHECK: extsw 3, [[REG2]]
@@ -22,12 +22,12 @@ entry:
   %div = sdiv i64 %a, 8
   ret i64 %div
 
-; CHECK-LABEL @foo8
+; CHECK-LABEL: @foo8
 ; CHECK: sradi [[REG1:[0-9]+]], 3, 3
 ; CHECK: addze 3, [[REG1]]
 ; CHECK: blr
 
-; CHECK-32-LABEL @foo8
+; CHECK-32-LABEL: @foo8
 ; CHECK-32-NOT: sradi
 ; CHECK-32: blr
 }
@@ -58,7 +58,7 @@ entry:
 ; CHECK: neg 3, [[REG2]]
 ; CHECK: blr
 
-; CHECK-32-LABEL @foo8n
+; CHECK-32-LABEL: @foo8n
 ; CHECK-32-NOT: sradi
 ; CHECK-32: blr
 }

diff --git a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
index f7ebf479755cda42f31dcf834c5fc5d721e5bfdf..9e79b52c404965fe678bb04fa08ff033ae2c6cda 100644 (file)
--- a/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
+++ b/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
@@ -14,7 +14,7 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
        %result = add <1 x i128> %x, <i128 1>
        ret <1 x i128> %result
 ; CHECK-LABEL: @increment_by_one
-; CHECK vadduqm 2, 2, 3
+; CHECK: vadduqm 2, 2, 3
 }
 
 define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
@@ -37,7 +37,7 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
        %result = sub <1 x i128> %x, <i128 1>
        ret <1 x i128> %result
 ; CHECK-LABEL: @decrement_by_one
-; CHECK vsubuqm 2, 2, 3
+; CHECK: vsubuqm 2, 2, 3
 }
 
 define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
@@ -46,7 +46,7 @@ define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
        %result = sub <1 x i128> %x, %tmpvec2
        ret <1 x i128> %result
 ; CHECK-LABEL: @decrement_by_val
-; CHECK vsubuqm   2, 2, 3
+; CHECK: vsubuqm   2, 2, 3
 }
 
 declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, 

diff --git a/test/CodeGen/X86/GC/dynamic-frame-size.ll b/test/CodeGen/X86/GC/dynamic-frame-size.ll
index a3583d46a29a22e78a849a24f7caf6fe3d8c53f9..9ec9b8b085076aa8a45e48920fe2ef68eea13218 100644 (file)
--- a/test/CodeGen/X86/GC/dynamic-frame-size.ll
+++ b/test/CodeGen/X86/GC/dynamic-frame-size.ll
@@ -17,12 +17,12 @@ define void @test(i8* %ptr) gc "erlang" {
 ; CHECK: .note.gc
 ; CHECK-NEXT: .align 8
 ; safe point count
-; CHECK .short 1
-; CHECK .long  .Ltmp0
+; CHECK: .short        1
+; CHECK: .long .Ltmp0
 ; stack frame size (in words)
-; CHECK .short -1
+; CHECK: .short        -1
 ; stack arity (arguments on the stack)
-; CHECK .short 0
+; CHECK: .short        0
 ; live root count
-; CHECK .short 0
+; CHECK: .short        0
 

diff --git a/test/CodeGen/X86/codegen-prepare-cast.ll b/test/CodeGen/X86/codegen-prepare-cast.ll
index 1ab8017e8858fd38b9c3d04a10a64cb25fe302cd..c5c2d64f63d827b9dc461900a78aab6eb3035624 100644 (file)
--- a/test/CodeGen/X86/codegen-prepare-cast.ll
+++ b/test/CodeGen/X86/codegen-prepare-cast.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 ; CHECK-LABEL: @_Dmain
 ; CHECK: load i8, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0)
-; CHECK ret
+; CHECK: ret
 define fastcc i32 @_Dmain(%"char[][]" %unnamed) {
 entry:
         %tmp = getelementptr [7 x i8], [7 x i8]* @.str, i32 0, i32 0              ; <i8*> [#uses=1]

diff --git a/test/CodeGen/X86/fma-do-not-commute.ll b/test/CodeGen/X86/fma-do-not-commute.ll
index 1f6a19cfff83cb5d51418a83401e6bb03a380bde..89be0795d2067fc94c8361441875cc09f3e24e5d 100644 (file)
--- a/test/CodeGen/X86/fma-do-not-commute.ll
+++ b/test/CodeGen/X86/fma-do-not-commute.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-macosx"
 
 ; CHECK-LABEL: test1:
 ; %arg lives in xmm0 and it shouldn't be redefined until it is used in the FMA.
-; CHECK-NOT {{.*}}, %xmm0
+; CHECK-NOT: {{.*}}, %xmm0
 ; %addr lives in rdi.
 ; %addr2 lives in rsi.
 ; CHECK: vmovss (%rsi), [[ADDR2:%xmm[0-9]+]]

diff --git a/test/CodeGen/X86/machine-cp.ll b/test/CodeGen/X86/machine-cp.ll
index aaed0f0a23dcab312e955aa82512c83e28f56b33..768b9cab6f6d46dc2bd6a03467356ac942e3b8e9 100644 (file)
--- a/test/CodeGen/X86/machine-cp.ll
+++ b/test/CodeGen/X86/machine-cp.ll
@@ -83,12 +83,12 @@ while.end:                                        ; preds = %while.body, %entry
 ; CHECK-NOT: , [[CPY1]]
 ; CHECK: punpcklbw [[CPY2]], [[CPY2]]
 ; CHECK-NEXT: punpckhwd [[CPY2]], [[CPY2]]
-; CHECK-NEXT pslld $31, [[CPY2]]
+; CHECK-NEXT: pslld $31, [[CPY2]]
 ; Check that CPY1 is not redefined.
 ; CHECK-NOT: , [[CPY1]]
 ; CHECK: punpcklbw [[CPY1]], [[CPY1]]
 ; CHECK-NEXT: punpcklwd [[CPY1]], [[CPY1]]
-; CHECK-NEXT pslld $31, [[CPY1]]
+; CHECK-NEXT: pslld $31, [[CPY1]]
 define <16 x float> @foo(<16 x float> %x) {
 bb:
   %v3 = icmp slt <16 x i32> undef, zeroinitializer

diff --git a/test/CodeGen/X86/statepoint-invoke.ll b/test/CodeGen/X86/statepoint-invoke.ll
index 81b9ab89ebca535151a74086c2c2d13fa9c5043f..7e35d4f4d38ee6c8c65bdbbda63b126f3a0ed6d3 100644 (file)
--- a/test/CodeGen/X86/statepoint-invoke.ll
+++ b/test/CodeGen/X86/statepoint-invoke.ll
@@ -113,7 +113,7 @@ right.relocs:
 normal_return:
   ; CHECK-LABEL: %normal_return
   ; CHECK: cmoveq {{.*}}[[REGVAL2]]{{.*}}
-  ; CHECK retq
+  ; CHECK: retq
   %a1 = phi i64 addrspace(1)* [%val1.relocated, %left.relocs], [%val3.relocated, %right.relocs]
   %a2 = phi i64 addrspace(1)* [%val2.relocated_left, %left.relocs], [%val2.relocated_right, %right.relocs]
   %ret = select i1 %cond, i64 addrspace(1)* %a1, i64 addrspace(1)* %a2

diff --git a/test/DebugInfo/dwarfdump-accel.test b/test/DebugInfo/dwarfdump-accel.test
index c5c3b0154c118fbb3400e51c3d3c17feb7469d40..7c1838829562f29845d700b2fd9fa9bab7ee2ca9 100644 (file)
--- a/test/DebugInfo/dwarfdump-accel.test
+++ b/test/DebugInfo/dwarfdump-accel.test
@@ -57,7 +57,7 @@ CHECK-NOT: Magic
 Check ObjC specific accelerators.
 CHECK: .apple_objc contents:
 CHECK:     Name{{.*}}"TestInterface"
-CHECK-NOT Name
+CHECK-NOT: Name
 CHECK:     {Atom[0]: [[READONLY]]}
 CHECK:     {Atom[0]: [[ASSIGN]]}
 CHECK:     {Atom[0]: [[SETASSIGN]]}

diff --git a/test/MC/ARM/basic-arm-instructions-v8.1a.s b/test/MC/ARM/basic-arm-instructions-v8.1a.s
index 005f27bb3983c83994683dec96d4c0566d6d9f41..9b764c18448a11e60f149d502026a97c5186b5cf 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions-v8.1a.s
+++ b/test/MC/ARM/basic-arm-instructions-v8.1a.s
@@ -37,7 +37,7 @@
 //CHECK-V8:   vqrdmlsh.f32  q3, q4, q5
 //CHECK-V8:           ^
 //CHECK-V8: error: invalid operand for instruction
-//CHECK-V8   vqrdmlsh.f64  d3, d5, d5
+//CHECK-V8:  vqrdmlsh.f64  d3, d5, d5
 //CHECK-V8:           ^
 
   vqrdmlah.s16    d0, d1, d2

diff --git a/test/MC/AsmParser/macros-darwin-vararg.s b/test/MC/AsmParser/macros-darwin-vararg.s
index 4aa2f4c1d9b6dc547a000048c143217bc69f2358..1c3ff69180f032cdd1257996b124eb27611bc3de 100644 (file)
--- a/test/MC/AsmParser/macros-darwin-vararg.s
+++ b/test/MC/AsmParser/macros-darwin-vararg.s
@@ -54,7 +54,7 @@ abc zed0, zed1, zed2
   ifcc4 %eax, %ecx  ## test
   ifcc4 %ecx, %eax ## test
 
-// CHECK-NOT movl
+// CHECK-NOT: movl
 // CHECK: subl $1, %esp
 .set cc,0
   ifcc  movl,    %esp, %ebp

diff --git a/test/MC/AsmParser/vararg.s b/test/MC/AsmParser/vararg.s
index e3236b072d12f91f9dd317e61ad0609fc714b0d1..dae81dfb78cee44e974fa21f4b189ca173e95302 100644 (file)
--- a/test/MC/AsmParser/vararg.s
+++ b/test/MC/AsmParser/vararg.s
@@ -44,7 +44,7 @@
   ifcc4 %eax %ecx  ## test
   ifcc4 %ecx, %eax ## test
 
-// CHECK-NOT movl
+// CHECK-NOT: movl
 // CHECK: subl $1, %esp
 .set cc,0
   ifcc  movl    %esp, %ebp

diff --git a/test/Transforms/InstCombine/cast-set.ll b/test/Transforms/InstCombine/cast-set.ll
index 47ba920d9286197556609198085ec5b1d0f91276..8f19bdcdfde31bc734071c5a6d6a467e4430bce1 100644 (file)
--- a/test/Transforms/InstCombine/cast-set.ll
+++ b/test/Transforms/InstCombine/cast-set.ll
@@ -10,7 +10,7 @@ define i1 @test1(i32 %X) {
         ; Convert to setne int %X, 12
         %c = icmp ne i32 %A, 12         ; <i1> [#uses=1]
         ret i1 %c
-; CHECK-LABEL @test1(
+; CHECK-LABEL: @test1(
 ; CHECK: %c = icmp ne i32 %X, 12
 ; CHECK: ret i1 %c
 }
@@ -21,7 +21,7 @@ define i1 @test2(i32 %X, i32 %Y) {
         ; Convert to setne int %X, %Y
         %c = icmp ne i32 %A, %B         ; <i1> [#uses=1]
         ret i1 %c
-; CHECK-LABEL @test2(
+; CHECK-LABEL: @test2(
 ; CHECK: %c = icmp ne i32 %X, %Y
 ; CHECK: ret i1 %c
 }

diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll
index e0ff07baae7cc3635889b9c183785070c62ee8e6..933d9ec4b0d74f8004cc8b354684491faba8a5b7 100644 (file)
--- a/test/Transforms/InstCombine/div.ll
+++ b/test/Transforms/InstCombine/div.ll
@@ -163,7 +163,7 @@ define i32 @test19(i32 %x) {
 ; CHECK-LABEL: @test19(
 ; CHECK-NEXT: icmp eq i32 %x, 1
 ; CHECK-NEXT: zext i1 %{{.*}} to i32
-; CHECK-NEXT ret i32
+; CHECK-NEXT: ret i32
 }
 
 define i32 @test20(i32 %x) {

diff --git a/test/Transforms/InstSimplify/apint-or.ll b/test/Transforms/InstSimplify/apint-or.ll
index 5d314db7133dd0aae900e70ed82a18c863d054ed..ebbc7be98b09c1c526891daee988bb5a6e435696 100644 (file)
--- a/test/Transforms/InstSimplify/apint-or.ll
+++ b/test/Transforms/InstSimplify/apint-or.ll
@@ -12,7 +12,7 @@ define i39 @test1(i39 %V, i39 %M) {
     %D = and i39 %V, 274877906943
     %R = or i39 %B, %D
     ret i39 %R
-; CHECK-LABEL @test1
+; CHECK-LABEL: @test1
 ; CHECK-NEXT: and {{.*}}, -274877906944
 ; CHECK-NEXT: add
 ; CHECK-NEXT: ret
@@ -30,7 +30,7 @@ define i399 @test2(i399 %V, i399 %M) {
     %D = and i399 %V, 274877906943
     %R = or i399 %B, %D
     ret i399 %R
-; CHECK-LABEL @test2
+; CHECK-LABEL: @test2
 ; CHECK-NEXT: and {{.*}}, 18446742974197923840
 ; CHECK-NEXT: add
 ; CHECK-NEXT: ret

diff --git a/test/Transforms/MergeFunc/ranges.ll b/test/Transforms/MergeFunc/ranges.ll
index 46a0c76cc7d175944c527695ccf8d75d20bdf731..44e71300703ba7dc3b57813c3c0b02afcbc5e292 100644 (file)
--- a/test/Transforms/MergeFunc/ranges.ll
+++ b/test/Transforms/MergeFunc/ranges.ll
@@ -8,10 +8,10 @@ define i1 @cmp_with_range(i8*, i8*) {
 
 define i1 @cmp_no_range(i8*, i8*) {
 ; CHECK-LABEL: @cmp_no_range
-; CHECK-NEXT  %v1 = load i8, i8* %0
-; CHECK-NEXT  %v2 = load i8, i8* %1
-; CHECK-NEXT  %out = icmp eq i8 %v1, %v2
-; CHECK-NEXT  ret i1 %out
+; CHECK-NEXT: %v1 = load i8, i8* %0
+; CHECK-NEXT:  %v2 = load i8, i8* %1
+; CHECK-NEXT:  %out = icmp eq i8 %v1, %v2
+; CHECK-NEXT:  ret i1 %out
   %v1 = load i8, i8* %0
   %v2 = load i8, i8* %1
   %out = icmp eq i8 %v1, %v2

diff --git a/test/Transforms/Reassociate/vaarg_movable.ll b/test/Transforms/Reassociate/vaarg_movable.ll
index 4581bc15c67827c7af44d3d63b9beb591d5f8117..be4fe121fae9d350ad344344180d662d2f50e6cb 100644 (file)
--- a/test/Transforms/Reassociate/vaarg_movable.ll
+++ b/test/Transforms/Reassociate/vaarg_movable.ll
@@ -3,7 +3,7 @@
 ; The two va_arg instructions depend on the memory/context, are therfore not
 ; identical and the sub should not be optimized to 0 by reassociate.
 ;
-; CHECK-LABEL @func(
+; CHECK-LABEL: @func(
 ; ...
 ; CHECK: %v0 = va_arg i8** %varargs, i32
 ; CHECK: %v1 = va_arg i8** %varargs, i32

diff --git a/test/Transforms/RewriteStatepointsForGC/relocation.ll b/test/Transforms/RewriteStatepointsForGC/relocation.ll
index d7a84e5820c8fb5dd7d87b6db5ce68956a94a62f..10ee08c25a4a5aee4446f429527cb720702a59d0 100644 (file)
--- a/test/Transforms/RewriteStatepointsForGC/relocation.ll
+++ b/test/Transforms/RewriteStatepointsForGC/relocation.ll
@@ -232,7 +232,7 @@ inner-loop:
 ; CHECK: phi i8 addrspace(1)* 
 ; CHECK-DAG: %outer-loop ]
 ; CHECK-DAG: [ %arg2.relocated, %inner-loop ]
-; CHECKL phi i8 addrspace(1)* 
+; CHECK: phi i8 addrspace(1)* 
 ; CHECK-DAG: %outer-loop ]
 ; CHECK-DAG: [ %arg1.relocated, %inner-loop ]
 ; CHECK: gc.statepoint

diff --git a/test/Transforms/TailCallElim/basic.ll b/test/Transforms/TailCallElim/basic.ll
index 2488b552d8f3513488bae4b36dbd86d77d465637..fe8bbe9ad03f065dee69f681d51ad33e228259b8 100644 (file)
--- a/test/Transforms/TailCallElim/basic.ll
+++ b/test/Transforms/TailCallElim/basic.ll
@@ -156,7 +156,7 @@ define void @test9(i32* byval %a) {
 
 declare void @ctor(%struct.X*)
 define void @test10(%struct.X* noalias sret %agg.result, i1 zeroext %b) {
-; CHECK-LABEL @test10
+; CHECK-LABEL: @test10
 entry:
   %x = alloca %struct.X, align 8
   br i1 %b, label %if.then, label %if.end

diff --git a/test/tools/dsymutil/X86/basic-lto-linking-x86.test b/test/tools/dsymutil/X86/basic-lto-linking-x86.test
index 81744273c6bcc2c1de38fe6a68c4d9132f087309..5e9185d92b5ded4e85c6399dbeb70b5dd66516bd 100644 (file)
--- a/test/tools/dsymutil/X86/basic-lto-linking-x86.test
+++ b/test/tools/dsymutil/X86/basic-lto-linking-x86.test
@@ -117,7 +117,7 @@ CHECK:        DW_AT_type [DW_FORM_ref_addr] (0x0000000000000063)
 CHECK:        DW_AT_location [DW_FORM_data4]        (0x00000025)
 CHECK:      DW_TAG_lexical_block [14] *
 CHECK:        DW_AT_low_pc [DW_FORM_addr]   (0x0000000100000f94)
-CHECK         DW_AT_high_pc [DW_FORM_addr]  (0x0000000100000fa7)
+CHECK:        DW_AT_high_pc [DW_FORM_addr]  (0x0000000100000fa7)
 CHECK:        DW_TAG_inlined_subroutine [15]
 CHECK:          DW_AT_abstract_origin [DW_FORM_ref4]        (cu + 0x009a => {0x000001d4} "inc")
 CHECK:          DW_AT_ranges [DW_FORM_data4]        (0x00000000