don't bother making x&-1 only to simplify it in dag combine. This commonly occurs...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46383 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index efbaa5a7f6dca6a95f6cbb72463d90192e6444e9..ad6cd1ba3db7414c9136eee5d663862432f620f9 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1877,6 +1877,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     // worth handling here.
     if (N2C && N2C->getValue() == 0)
       return N2;
+    if (N2C && N2C->isAllOnesValue())  // X & -1 -> X
+      return N1;
     break;
   case ISD::OR:
   case ISD::XOR: