Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
- Inst.addOperand(MCOperand::CreateReg(ARM::SP));
CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
+ Inst.addOperand(MCOperand::CreateReg(ARM::SP));
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
0xd1 0x18
0x42 0x44
+#------------------------------------------------------------------------------
+# ADD (SP plus immediate)
+#------------------------------------------------------------------------------
+# CHECK: add sp, #508
+# CHECK: add sp, #4
+# CHECK: add r2, sp, #8
+# CHECK: add r2, sp, #1020
+
+0x7f 0xb0
+0x01 0xb0
+0x02 0xaa
+0xff 0xaa
+
+
+#------------------------------------------------------------------------------
+# ADD (SP plus register)
+#------------------------------------------------------------------------------
+# CHECK: add sp, r3
+# CHECK: add r2, sp, r2
+
+0x9d 0x44
+0x6a 0x44
+
#------------------------------------------------------------------------------
# ASR (immediate)
#------------------------------------------------------------------------------
0xd1 0x1a
+#------------------------------------------------------------------------------
+# SUB (SP minus immediate)
+#------------------------------------------------------------------------------
+# CHECK: sub sp, #12
+# CHECK: sub sp, #508
+
+0x83 0xb0
+0xff 0xb0
#------------------------------------------------------------------------------
# SVC