Remove some special-case logic in ScheduleDAGSDNodes's

latency computation code that is no longer needed with the
new method for handling latencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61074 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 21df142ff34583554f4d5481af91922ffa0dcabf..08d6702fc81b8215e6607ff44d587c4481ed79ed 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -196,12 +196,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
   
   // Compute the latency for the node.  We use the sum of the latencies for
   // all nodes flagged together into this SUnit.
-  if (InstrItins.isEmpty()) {
-    // No latency information.
-    SU->Latency = 1;
-    return;
-  }
-
   SU->Latency = 0;
   bool SawMachineOpcode = false;
   for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
@@ -210,10 +204,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
       SU->Latency +=
         InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
     }
-
-  // Ensure that CopyToReg and similar nodes have a non-zero latency.
-  if (!SawMachineOpcode)
-    SU->Latency = 1;
 }
 
 /// CountResults - The results of target nodes have register or immediate