Verify that one of the ranges produced by region splitting is allocatable.
authorJakob Stoklund Olesen <stoklund@2pi.dk>
Fri, 4 Feb 2011 19:33:07 +0000 (19:33 +0000)
committerJakob Stoklund Olesen <stoklund@2pi.dk>
Fri, 4 Feb 2011 19:33:07 +0000 (19:33 +0000)
We should not be attempting a region split if it won't lead to at least one
directly allocatable interval. That could cause infinite splitting loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124893 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/RegAllocGreedy.cpp

index 2c772a209757c0ba1191e0e42fa92b35d96607b8..f478d76bf792530c6cc955b5f99f0a6cf08b6ad8 100644 (file)
@@ -812,8 +812,22 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg,
   // separate into connected components. Some components may be allocatable.
   SE.finish();
 
-  if (VerifyEnabled)
+  if (VerifyEnabled) {
     MF->verify(this, "After splitting live range around region");
+
+#ifndef NDEBUG
+    // Make sure that at least one of the new intervals can allocate to PhysReg.
+    // That was the whole point of splitting the live range.
+    bool found = false;
+    for (LiveRangeEdit::iterator I = LREdit.begin(), E = LREdit.end(); I != E;
+         ++I)
+      if (!checkUncachedInterference(**I, PhysReg)) {
+        found = true;
+        break;
+      }
+    assert(found && "No allocatable intervals after pointless splitting");
+#endif
+  }
 }
 
 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,