Remove the wrapper macros IRQ_DEST_MODE and IRQ_DELIVERY_MODE.
The typical 32-bit and the 64-bit build all dereference via the genapic,
so it's pointless to hide that indirection via these ugly macros.
Furthermore, it also obscures subarchitecture details.
So replace it with apic->irq_dest_mode / etc. accesses.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
#undef APIC_DEST_LOGICAL
#define APIC_DEST_LOGICAL 0
#define APIC_DFR_VALUE (APIC_DFR_FLAT)
-#define IRQ_DELIVERY_MODE (dest_Fixed)
-#define IRQ_DEST_MODE (0) /* phys delivery to target proc */
+#define BIGSMP_IRQ_DELIVERY_MODE (dest_Fixed)
+#define BIGSMP_IRQ_DEST_MODE (0) /* phys delivery to target proc */
#define NO_BALANCE_IRQ (0)
static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
#define NO_BALANCE_IRQ_CLUSTER (1)
#define APIC_DFR_VALUE (APIC_DFR_FLAT)
-#define IRQ_DELIVERY_MODE (dest_Fixed)
-#define IRQ_DEST_MODE (0) /* phys delivery to target procs */
+#define ES7000_IRQ_DELIVERY_MODE (dest_Fixed)
+#define ES7000_IRQ_DEST_MODE (0) /* phys delivery to target procs */
#define NO_BALANCE_IRQ (0)
#undef APIC_DEST_LOGICAL
#define APIC_DEST_LOGICAL 0x0
#ifdef CONFIG_X86_64
#include <asm/genapic.h>
-#define IRQ_DELIVERY_MODE (apic->irq_delivery_mode)
#define IRQ_DEST_MODE (apic->irq_dest_mode)
#define TARGET_CPUS (apic->target_cpus())
#define init_apic_ldr (apic->init_apic_ldr)
#define wakeup_secondary_cpu (apic->wakeup_cpu)
extern void setup_apic_routing(void);
#else
-#define IRQ_DELIVERY_MODE dest_LowestPrio
-#define IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */
+#define DEFAULT_IRQ_DELIVERY_MODE dest_LowestPrio
+#define DEFAULT_IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */
#define TARGET_CPUS (target_cpus())
#define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
/*
#define esr_disable (apic->ESR_DISABLE)
#define NO_BALANCE_IRQ (apic->no_balance_irq)
-#define IRQ_DELIVERY_MODE (apic->irq_delivery_mode)
-#define IRQ_DEST_MODE (apic->irq_dest_mode)
#undef APIC_DEST_LOGICAL
#define APIC_DEST_LOGICAL (apic->apic_destination_logical)
#define TARGET_CPUS (apic->target_cpus())
#define NO_BALANCE_IRQ (1)
#define esr_disable (1)
-#define IRQ_DELIVERY_MODE dest_LowestPrio
-#define IRQ_DEST_MODE 0 /* physical delivery on LOCAL quad */
+#define NUMAQ_IRQ_DELIVERY_MODE dest_LowestPrio
+#define NUMAQ_IRQ_DEST_MODE 0 /* physical delivery on LOCAL quad */
static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
{
return &cpumask_of_cpu(0);
}
-#define IRQ_DELIVERY_MODE (dest_LowestPrio)
-#define IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */
+#define SUMMIT_IRQ_DELIVERY_MODE (dest_LowestPrio)
+#define SUMMIT_IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */
static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
{
memset(&irte, 0, sizeof(irte));
irte.present = 1;
- irte.dst_mode = IRQ_DEST_MODE;
+ irte.dst_mode = apic->irq_dest_mode;
irte.trigger_mode = trigger;
- irte.dlvry_mode = IRQ_DELIVERY_MODE;
+ irte.dlvry_mode = apic->irq_delivery_mode;
irte.vector = vector;
irte.dest_id = IRTE_DEST(destination);
} else
#endif
{
- entry->delivery_mode = IRQ_DELIVERY_MODE;
- entry->dest_mode = IRQ_DEST_MODE;
+ entry->delivery_mode = apic->irq_delivery_mode;
+ entry->dest_mode = apic->irq_dest_mode;
entry->dest = destination;
}
* We use logical delivery to get the timer IRQ
* to the first CPU.
*/
- entry.dest_mode = IRQ_DEST_MODE;
+ entry.dest_mode = apic->irq_dest_mode;
entry.mask = 1; /* mask IRQ now */
entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
- entry.delivery_mode = IRQ_DELIVERY_MODE;
+ entry.delivery_mode = apic->irq_delivery_mode;
entry.polarity = 0;
entry.trigger = 0;
entry.vector = vector;
memset (&irte, 0, sizeof(irte));
irte.present = 1;
- irte.dst_mode = IRQ_DEST_MODE;
+ irte.dst_mode = apic->irq_dest_mode;
irte.trigger_mode = 0; /* edge */
- irte.dlvry_mode = IRQ_DELIVERY_MODE;
+ irte.dlvry_mode = apic->irq_delivery_mode;
irte.vector = cfg->vector;
irte.dest_id = IRTE_DEST(dest);
msg->address_hi = MSI_ADDR_BASE_HI;
msg->address_lo =
MSI_ADDR_BASE_LO |
- ((IRQ_DEST_MODE == 0) ?
+ ((apic->irq_dest_mode == 0) ?
MSI_ADDR_DEST_MODE_PHYSICAL:
MSI_ADDR_DEST_MODE_LOGICAL) |
- ((IRQ_DELIVERY_MODE != dest_LowestPrio) ?
+ ((apic->irq_delivery_mode != dest_LowestPrio) ?
MSI_ADDR_REDIRECTION_CPU:
MSI_ADDR_REDIRECTION_LOWPRI) |
MSI_ADDR_DEST_ID(dest);
msg->data =
MSI_DATA_TRIGGER_EDGE |
MSI_DATA_LEVEL_ASSERT |
- ((IRQ_DELIVERY_MODE != dest_LowestPrio) ?
+ ((apic->irq_delivery_mode != dest_LowestPrio) ?
MSI_DATA_DELIVERY_FIXED:
MSI_DATA_DELIVERY_LOWPRI) |
MSI_DATA_VECTOR(cfg->vector);
HT_IRQ_LOW_BASE |
HT_IRQ_LOW_DEST_ID(dest) |
HT_IRQ_LOW_VECTOR(cfg->vector) |
- ((IRQ_DEST_MODE == 0) ?
+ ((apic->irq_dest_mode == 0) ?
HT_IRQ_LOW_DM_PHYSICAL :
HT_IRQ_LOW_DM_LOGICAL) |
HT_IRQ_LOW_RQEOI_EDGE |
- ((IRQ_DELIVERY_MODE != dest_LowestPrio) ?
+ ((apic->irq_delivery_mode != dest_LowestPrio) ?
HT_IRQ_LOW_MT_FIXED :
HT_IRQ_LOW_MT_ARBITRATED) |
HT_IRQ_LOW_IRQ_MASKED;
BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
entry->vector = cfg->vector;
- entry->delivery_mode = IRQ_DELIVERY_MODE;
- entry->dest_mode = IRQ_DEST_MODE;
+ entry->delivery_mode = apic->irq_delivery_mode;
+ entry->dest_mode = apic->irq_dest_mode;
entry->polarity = 0;
entry->trigger = 0;
entry->mask = 0;
.acpi_madt_oem_check = NULL,
.apic_id_registered = bigsmp_apic_id_registered,
- .irq_delivery_mode = IRQ_DELIVERY_MODE,
- .irq_dest_mode = IRQ_DEST_MODE,
+ .irq_delivery_mode = BIGSMP_IRQ_DELIVERY_MODE,
+ .irq_dest_mode = BIGSMP_IRQ_DEST_MODE,
.target_cpus = target_cpus,
.ESR_DISABLE = esr_disable,
.acpi_madt_oem_check = NULL,
.apic_id_registered = default_apic_id_registered,
- .irq_delivery_mode = IRQ_DELIVERY_MODE,
- .irq_dest_mode = IRQ_DEST_MODE,
+ .irq_delivery_mode = DEFAULT_IRQ_DELIVERY_MODE,
+ .irq_dest_mode = DEFAULT_IRQ_DEST_MODE,
.target_cpus = target_cpus,
.ESR_DISABLE = esr_disable,
.acpi_madt_oem_check = es7000_acpi_madt_oem_check,
.apic_id_registered = es7000_apic_id_registered,
- .irq_delivery_mode = IRQ_DELIVERY_MODE,
- .irq_dest_mode = IRQ_DEST_MODE,
+ .irq_delivery_mode = ES7000_IRQ_DELIVERY_MODE,
+ .irq_dest_mode = ES7000_IRQ_DEST_MODE,
.target_cpus = target_cpus,
.ESR_DISABLE = esr_disable,
.acpi_madt_oem_check = NULL,
.apic_id_registered = numaq_apic_id_registered,
- .irq_delivery_mode = IRQ_DELIVERY_MODE,
- .irq_dest_mode = IRQ_DEST_MODE,
+ .irq_delivery_mode = NUMAQ_IRQ_DELIVERY_MODE,
+ .irq_dest_mode = NUMAQ_IRQ_DEST_MODE,
.target_cpus = target_cpus,
.ESR_DISABLE = esr_disable,
.acpi_madt_oem_check = summit_acpi_madt_oem_check,
.apic_id_registered = summit_apic_id_registered,
- .irq_delivery_mode = IRQ_DELIVERY_MODE,
- .irq_dest_mode = IRQ_DEST_MODE,
+ .irq_delivery_mode = SUMMIT_IRQ_DELIVERY_MODE,
+ .irq_dest_mode = SUMMIT_IRQ_DEST_MODE,
.target_cpus = target_cpus,
.ESR_DISABLE = esr_disable,