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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31719 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/README.txt b/lib/Target/README.txt
index 18cd4f66f263a583e08e6a1a800f5332f77cf54c..23874b7be882a942ff1cd195d02b9150158b23ae 100644 (file)
--- a/lib/Target/README.txt
+++ b/lib/Target/README.txt
@@ -16,6 +16,22 @@ We should make the following changes to clean up MachineInstr:
 
 //===---------------------------------------------------------------------===//
 
+With the recent changes to make the implicit def/use set explicit in
+machineinstrs, we should change the target descriptions for 'call' instructions
+so that the .td files don't list all the call-clobbered registers as implicit
+defs.  Instead, these should be added by the code generator (e.g. on the dag).
+
+This has a number of uses:
+
+1. PPC32/64 and X86 32/64 can avoid having multiple copies of call instructions
+   for their different impdef sets.
+2. Targets with multiple calling convs (e.g. x86) which have different clobber
+   sets don't need copies of call instructions.
+3. 'Interprocedural register allocation' can be done to reduce the clobber sets
+   of calls.
+
+//===---------------------------------------------------------------------===//
+
 FreeBench/mason contains code like this:
 
 static p_type m0u(p_type p) {