llvm::linkOcamlGC();
llvm::linkShadowStackGC();
- (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createFastDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createDefaultScheduler(NULL, NULL, NULL, false);
+ (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createFastDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createDefaultScheduler(NULL, NULL, NULL, NULL, false);
}
} ForceCodegenLinking; // Force link by creating a global definition.
/// reduction list scheduler.
ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
/// reduction list scheduler.
ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
/// a hazard recognizer.
ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
///
ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
public:
typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
+ const TargetMachine *,
MachineBasicBlock*, bool);
static MachinePassRegistry Registry;
llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB, bool) {
- return new ScheduleDAGFast(*DAG, BB, DAG->getTarget());
+ return new ScheduleDAGFast(*DAG, BB, *TM);
}
/// recognizer and deletes it when done.
ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB, bool Fast) {
- return new ScheduleDAGList(*DAG, BB, DAG->getTarget(),
+ return new ScheduleDAGList(*DAG, BB, *TM,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());
}
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
if (Fast)
- return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true,
+ return new ScheduleDAGRRList(*DAG, BB, *TM, true, true,
new BURegReductionFastPriorityQueue());
- const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
- const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
+ const TargetInstrInfo *TII = TM->getInstrInfo();
+ const TargetRegisterInfo *TRI = TM->getRegisterInfo();
BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
ScheduleDAGRRList *SD =
- new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ);
+ new ScheduleDAGRRList(*DAG, BB, *TM, true, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
}
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
- return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast,
+ return new ScheduleDAGRRList(*DAG, BB, *TM, false, Fast,
new TDRegReductionPriorityQueue());
}
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
TargetLowering &TLI = IS->getTargetLowering();
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
- return createTDListDAGScheduler(IS, DAG, BB, Fast);
+ return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
} else {
assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
- return createBURRListDAGScheduler(IS, DAG, BB, Fast);
+ return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
}
}
}
RegisterScheduler::setDefault(Ctor);
}
- ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
+ TargetMachine &TM = getTargetLowering().getTargetMachine();
+ ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
Scheduler->Run();
return Scheduler;