serial: of: add a PORT_RT2880 definition

The Ralink RT2880 SoC and its successors have an internal 8250 core. This core
needs the same quirks applied as the AMD AU1xxx uart. In addition to these
quirks, the ports memory region is only 0x100 unlike the AU1xxx which has a
size of 0x1000.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 7e78f3077b5dd7a1ff9a63f64397d21c096ab9a9..223503299e99a4b3a38cfe771a1d2f158a8d0c70 100644 (file)
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -2640,8 +2640,11 @@ serial8250_pm(struct uart_port *port, unsigned int state,
 
 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
 {
-       if (pt->port.iotype == UPIO_AU)
+       if (pt->port.iotype == UPIO_AU) {
+               if (pt->port.type == PORT_RT2880)
+                       return 0x100;
                return 0x1000;
+       }
        if (is_omap1_8250(pt))
                return 0x16 << pt->port.regshift;
 

diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 9c64ad2ac1a8ba5ba2ee4ac217d10aa06bebd3cf..8749fb849803cc5f3df042edb0aff5258ad333ec 100644 (file)
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -130,8 +130,15 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
 
        port->dev = &ofdev->dev;
 
-       if (type == PORT_TEGRA)
+       switch (type) {
+       case PORT_TEGRA:
                port->handle_break = tegra_serial_handle_break;
+               break;
+
+       case PORT_RT2880:
+               port->iotype = UPIO_AU;
+               break;
+       }
 
        return 0;
 out:
@@ -317,6 +324,7 @@ static struct of_device_id of_platform_serial_table[] = {
        { .compatible = "ns16850",  .data = (void *)PORT_16850, },
        { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
        { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
+       { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
        { .compatible = "altr,16550-FIFO32",
                .data = (void *)PORT_ALTR_16550_F32, },
        { .compatible = "altr,16550-FIFO64",

diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 16ad8521af6ad757427868c89be083ca99187e7e..c17218094f187511710d4f25f341216c531ca111 100644 (file)
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -54,7 +54,8 @@
 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
-#define PORT_MAX_8250  28      /* max port ID */
+#define PORT_RT2880    29      /* Ralink RT2880 internal UART */
+#define PORT_MAX_8250  29      /* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed