update rk29sdk config and sdmmc
authorlhh <lhh@rock-chips.com>
Sun, 5 Dec 2010 06:06:11 +0000 (14:06 +0800)
committerlhh <lhh@rock-chips.com>
Sun, 5 Dec 2010 06:06:11 +0000 (14:06 +0800)
arch/arm/configs/rk29_sdk_defconfig
arch/arm/mach-rk29/board-rk29sdk.c
drivers/mmc/host/rk29_sdmmc.c

index 16c6efb59b7ab1f26a6572169ce23778ef0a689b..3406bb9381ddaeb0fe6d37d625edcb21e937a643 100755 (executable)
@@ -649,7 +649,35 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 # CONFIG_DCC_TTY is not set
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_RK29=y
+
+#
+# Now, there are four I2C interfaces selected by developer.
+#
+CONFIG_I2C0_RK29=y
+# CONFIG_I2C1_RK29 is not set
+# CONFIG_I2C2_RK29 is not set
+# CONFIG_I2C3_RK29 is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_PCA963X is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
 CONFIG_ADC=y
 # CONFIG_ADC_RK28 is not set
@@ -810,7 +838,7 @@ CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_MMC=y
 CONFIG_MMC_DEBUG=y
 # CONFIG_MMC_UNSAFE_RESUME is not set
-# CONFIG_MMC_EMBEDDED_SDIO is not set
+CONFIG_MMC_EMBEDDED_SDIO=y
 # CONFIG_MMC_PARANOID_SD_INIT is not set
 
 #
@@ -818,7 +846,7 @@ CONFIG_MMC_DEBUG=y
 #
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
 # CONFIG_SDIO_UART is not set
 # CONFIG_MMC_TEST is not set
 
@@ -831,7 +859,7 @@ CONFIG_SDMMC_RK29=y
 # Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
 #
 CONFIG_SDMMC0_RK29=y
-CONFIG_EMMC_RK29=y
+# CONFIG_EMMC_RK29 is not set
 CONFIG_SDMMC1_RK29=y
 # CONFIG_MMC_SDHCI is not set
 # CONFIG_MMC_AT91 is not set
@@ -858,6 +886,26 @@ CONFIG_RTC_INTF_ALARM=y
 CONFIG_RTC_INTF_ALARM_DEV=y
 # CONFIG_RTC_DRV_TEST is not set
 
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_HYM8563=y
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_S35392A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
 #
 # SPI RTC drivers
 #
index 79e712e0a2b9b3f27899ed99e3e9bb452f8e65c9..934626a29c924c5637b45ce4aa61f69c25da05b3 100755 (executable)
@@ -657,12 +657,13 @@ static int rk29_sdmmc0_cfg_gpio(void)
        rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);\r
        rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);\r
        rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);\r
+       rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);\r
        return 0;\r
 }\r
 \r
-#define CONFIG_SDMMC0_USE_DMA\r
+//#define CONFIG_SDMMC0_USE_DMA\r
 struct rk29_sdmmc_platform_data default_sdmmc0_data = {\r
-       .host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|\r
+       .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|\r
                                           MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|\r
                                           MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),\r
        .host_caps      = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),\r
@@ -690,7 +691,7 @@ static int rk29_sdmmc1_cfg_gpio(void)
 }\r
 \r
 struct rk29_sdmmc_platform_data default_sdmmc1_data = {\r
-       .host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|\r
+       .host_ocr_avail = (MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|\r
                                           MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|\r
                                           MMC_VDD_32_33|MMC_VDD_33_34),\r
        .host_caps      = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|\r
index 7c24cb0d753166903771c8eb7244abcc9c36db6e..4b348d0e68a40590e6ba61cdd6fb8c89273eefc3 100644 (file)
@@ -300,8 +300,8 @@ static void rk29_sdmmc_set_timeout(struct rk29_sdmmc *host,struct mmc_data *data
        unsigned timeout;
 
        timeout = ns_to_clocks(host->clock, data->timeout_ns) + data->timeout_clks;
-       rk29_sdmmc_write(host->regs, SDMMC_TMOUT, 0xffffffff);
-       ///rk29_sdmmc_write(host->regs, SDMMC_TMOUT, (timeout << 8) | (70));
+       ///rk29_sdmmc_write(host->regs, SDMMC_TMOUT, 0xffffffff);
+       rk29_sdmmc_write(host->regs, SDMMC_TMOUT, (timeout << 8) | (70));
 }
 
 static u32 rk29_sdmmc_prepare_command(struct mmc_host *mmc,
@@ -1186,11 +1186,9 @@ static int rk29_sdmmc_probe(struct platform_device *pdev)
        irq = platform_get_irq(pdev, 0);
        if (irq < 0)
                return irq;
-
        mmc = mmc_alloc_host(sizeof(struct rk29_sdmmc), &pdev->dev);
        if (!mmc)
-               return -ENOMEM;
-               
+               return -ENOMEM; 
        host = mmc_priv(mmc);
        host->mmc = mmc;
        host->pdev = pdev;
@@ -1200,10 +1198,10 @@ static int rk29_sdmmc_probe(struct platform_device *pdev)
                ret = -ENODEV;
                goto err_freehost;
        }
-
+       if(pdata->io_init)
+               pdata->io_init();
        spin_lock_init(&host->lock);
        INIT_LIST_HEAD(&host->queue);
-
        ret = -ENOMEM;
        host->regs = ioremap(regs->start, regs->end - regs->start);
        if (!host->regs)
@@ -1222,38 +1220,36 @@ static int rk29_sdmmc_probe(struct platform_device *pdev)
                rk29_dma_config(host->dma_chn, 16);
                rk29_dma_set_buffdone_fn(host->dma_chn, rk29_sdmmc_dma_complete);       
                host->dma_addr = regs->start + SDMMC_DATA;
-       }
-       host->bus_hz = 40000000;  ////cgu_get_clk_freq(CGU_SB_SD_MMC_CCLK_IN_ID); 
+       }       
+       host->clk = clk_get(&pdev->dev, "sdmmc");
+       clk_enable(host->clk);
+       clk_enable(clk_get(&pdev->dev, "sdmmc_ahb"));
+       host->bus_hz = clk_get_rate(host->clk);  ///40000000;  ////cgu_get_clk_freq(CGU_SB_SD_MMC_CCLK_IN_ID); 
 
        /* reset all blocks */
        rk29_sdmmc_write(host->regs, SDMMC_CTRL,(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET));
        /* wait till resets clear */
        while (rk29_sdmmc_read(host->regs, SDMMC_CTRL) & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET));
-
         /* Clear the interrupts for the host controller */
        rk29_sdmmc_write(host->regs, SDMMC_RINTSTS, 0xFFFFFFFF);
        rk29_sdmmc_write(host->regs, SDMMC_INTMASK, 0); // disable all mmc interrupt first
-
        /* Put in max timeout */
        rk29_sdmmc_write(host->regs, SDMMC_TMOUT, 0xFFFFFFFF);
 
        /* FIFO threshold settings  */
        rk29_sdmmc_write(host->regs, SDMMC_FIFOTH, ((0x3 << 28) | (0x0f << 16) | (0x10 << 0))); // RXMark = 15, TXMark = 16, DMA Size = 16
-
        /* disable clock to CIU */
        rk29_sdmmc_write(host->regs, SDMMC_CLKENA,0);
        rk29_sdmmc_write(host->regs, SDMMC_CLKSRC,0);
        rk29_sdmmc_write(host->regs, SDMMC_PWREN, 1);
        tasklet_init(&host->tasklet, rk29_sdmmc_tasklet_func, (unsigned long)host);
-       
        ret = request_irq(irq, rk29_sdmmc_interrupt, 0, dev_name(&pdev->dev), host);
        if (ret)
            goto err_dmaunmap;
-
        platform_set_drvdata(pdev, host);       
        mmc->ops = &rk29_sdmmc_ops[pdev->id];
        mmc->f_min = host->bus_hz/510;
-       mmc->f_max = host->bus_hz/20; //max f is clock to mmc_clk/2
+       mmc->f_max = host->bus_hz/4;  //2;  ///20; //max f is clock to mmc_clk/2
        mmc->ocr_avail = pdata->host_ocr_avail;
        mmc->caps = pdata->host_caps;
        mmc->max_phys_segs = 64;
@@ -1262,7 +1258,6 @@ static int rk29_sdmmc_probe(struct platform_device *pdev)
        mmc->max_blk_count = 512;
        mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
        mmc->max_seg_size = mmc->max_req_size;  
-       
        /* Assume card is present initially */
        if(rk29_sdmmc_get_cd(host->mmc))
                set_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
@@ -1270,14 +1265,11 @@ static int rk29_sdmmc_probe(struct platform_device *pdev)
                clear_bit(RK29_SDMMC_CARD_PRESENT, &host->flags);
 
        mmc_add_host(mmc);
 #if defined (CONFIG_DEBUG_FS)
        rk29_sdmmc_init_debugfs(host);
 #endif
-
        /* Create card detect handler thread  */
        setup_timer(&host->detect_timer, rk29_sdmmc_detect_change,(unsigned long)host);
-       
        // enable interrupt for command done, data over, data empty, receive ready and error such as transmit, receive timeout, crc error
        rk29_sdmmc_write(host->regs, SDMMC_RINTSTS, 0xFFFFFFFF);
        rk29_sdmmc_write(host->regs, SDMMC_INTMASK,SDMMC_INT_CMD_DONE | SDMMC_INT_DTO | SDMMC_INT_TXDR | SDMMC_INT_RXDR | RK29_SDMMC_ERROR_FLAGS | SDMMC_INT_CD);