ARM: rockchip: rk312x add cpu axi bus support

diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index 6561e9314dea9950d61e513ceac278eee1cae8d7..d91db92bcbbd3366d177ce29f417c81490a8b3bd 100755 (executable)
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -68,6 +68,63 @@
                             <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
        };
 
+       cpu_axi_bus: cpu_axi_bus {
+               compatible = "rockchip,cpu_axi_bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               qos {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       crypto {
+                               reg = <0x10128080 0x20>;
+                       };
+                       core {
+                               reg = <0x1012a000 0x20>;
+                               rockchip,priority = <3 2>;
+                       };
+                       peri {
+                               reg = <0x1012c000 0x20>;
+                       };
+                       gpu {
+                               reg = <0x1012d000 0x20>;
+                       };
+                       vpu {
+                               reg = <0x1012e000 0x20>;
+                       };
+                       rga {
+                               reg = <0x1012f000 0x20>;
+                       };
+                       ebc {
+                               reg = <0x1012f080 0x20>;
+                       };
+                       iep {
+                               reg = <0x1012f100 0x20>;
+                       };
+                       lcdc {
+                               reg = <0x1012f180 0x20>;
+                               rockchip,priority = <3 3>;
+                       };
+                       vip {
+                               reg = <0x1012f200 0x20>;
+                       };
+               };
+
+               msch {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       msch@10128000 {
+                               reg = <0x10128000 0x20>;
+                               rockchip,read-latency = <0x3f>;
+                       };
+               };
+       };
+
        sram: sram@10080000 {
                compatible = "mmio-sram";
                reg = <0x10080000 0x2000>;