specify triple so Windows bots won't be sad
authorSanjay Patel <spatel@rotateright.com>
Mon, 9 Nov 2015 21:53:58 +0000 (21:53 +0000)
committerSanjay Patel <spatel@rotateright.com>
Mon, 9 Nov 2015 21:53:58 +0000 (21:53 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252519 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/X86/x86-64-double-precision-shift-left.ll
test/CodeGen/X86/x86-64-double-precision-shift-right.ll

index 75e9052c1297c9efda275b4883782e038d23241d..7515c46f7ceeea4037cbabdb2dfd1d407e5821a9 100644 (file)
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
 ; Verify that for the architectures that are known to have poor latency
 ; double precision shift instructions we generate alternative sequence 
 ; of instructions with lower latencies instead of shld instruction.
index bc2f39ee666dc8b7c82621509fd7b6124b3f3c86..5e3f229417130dc80450cb1a0c381d906ef254fb 100644 (file)
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
 ; Verify that for the architectures that are known to have poor latency
 ; double precision shift instructions we generate alternative sequence 
 ; of instructions with lower latencies instead of shrd instruction.