ath10k: add cycle/rx_clear counters frequency to hw_params
authorVasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Wed, 12 Aug 2015 10:54:05 +0000 (16:24 +0530)
committerKalle Valo <kvalo@qca.qualcomm.com>
Mon, 17 Aug 2015 13:46:21 +0000 (16:46 +0300)
The frequency at which cycle/rx_clear counters are running might
change from one target type to another. QCA99X0 is running the
counters at 150Mhz while QCA9888X and QCA6174 are running at 88Mhz.
Add a new entry to hw_params to store the target specific frequency
and use it in msecs conversion. This change fixes inconsistent
channel active/busy time.

Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
drivers/net/wireless/ath/ath10k/core.c
drivers/net/wireless/ath/ath10k/core.h
drivers/net/wireless/ath/ath10k/hw.c
drivers/net/wireless/ath/ath10k/hw.h

index 25510679fd2ed643d81f782eb3edc37e9c9f9a86..2efd4e4dd09008abe6fce1d726dec9f97023f65c 100644 (file)
@@ -53,6 +53,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .uart_pin = 7,
                .has_shifted_cc_wraparound = true,
                .otp_exe_param = 0,
+               .channel_counters_freq_hz = 88000,
                .fw = {
                        .dir = QCA988X_HW_2_0_FW_DIR,
                        .fw = QCA988X_HW_2_0_FW_FILE,
@@ -68,6 +69,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
                .uart_pin = 6,
                .otp_exe_param = 0,
+               .channel_counters_freq_hz = 88000,
                .fw = {
                        .dir = QCA6174_HW_2_1_FW_DIR,
                        .fw = QCA6174_HW_2_1_FW_FILE,
@@ -83,6 +85,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
                .uart_pin = 6,
                .otp_exe_param = 0,
+               .channel_counters_freq_hz = 88000,
                .fw = {
                        .dir = QCA6174_HW_3_0_FW_DIR,
                        .fw = QCA6174_HW_3_0_FW_FILE,
@@ -98,6 +101,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
                .uart_pin = 6,
                .otp_exe_param = 0,
+               .channel_counters_freq_hz = 88000,
                .fw = {
                        /* uses same binaries as hw3.0 */
                        .dir = QCA6174_HW_3_0_FW_DIR,
@@ -115,6 +119,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
                .uart_pin = 7,
                .otp_exe_param = 0x00000700,
                .continuous_frag_desc = true,
+               .channel_counters_freq_hz = 150000,
                .fw = {
                        .dir = QCA99X0_HW_2_0_FW_DIR,
                        .fw = QCA99X0_HW_2_0_FW_FILE,
index 6a387bac27b0f8bea60d1ee7a7c4eba223fa4545..862f6d0fac57dfbee026e37eb81756453681c07a 100644 (file)
@@ -609,6 +609,8 @@ struct ath10k {
                 */
                bool continuous_frag_desc;
 
+               u32 channel_counters_freq_hz;
+
                struct ath10k_hw_params_fw {
                        const char *dir;
                        const char *fw;
index fef7ccf6e185eacee92b8eee1a22071edff550a5..7b84d08a5154e7b2f14b79824665836d7c777100 100644 (file)
@@ -152,6 +152,6 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
        cc -= cc_prev - cc_fix;
        rcc -= rcc_prev;
 
-       survey->time = CCNT_TO_MSEC(cc);
-       survey->time_busy = CCNT_TO_MSEC(rcc);
+       survey->time = CCNT_TO_MSEC(ar, cc);
+       survey->time_busy = CCNT_TO_MSEC(ar, rcc);
 }
index d9de4a73847028f7d9c869dcc0ce617195488fbd..23afcda2de967637d73c7039d0f2cdb5f3b777ff 100644 (file)
@@ -552,8 +552,7 @@ enum ath10k_hw_rate_cck {
 #define SCRATCH_3_ADDRESS                      ar->regs->scratch_3_address
 #define CPU_INTR_ADDRESS                       0x0010
 
-/* Cycle counters are running at 88MHz */
-#define CCNT_TO_MSEC(x) ((x) / 88000)
+#define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
 
 /* Firmware indications to the Host via SCRATCH_3 register. */
 #define FW_INDICATOR_ADDRESS                   ar->regs->fw_indicator_address