video: rockchip: hdmi: 3288/3368: set ddc clock to 50KHz.
authorZheng Yang <zhengyang@rock-chips.com>
Fri, 18 Sep 2015 08:58:52 +0000 (16:58 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Mon, 21 Sep 2015 03:04:18 +0000 (11:04 +0800)
Change-Id: I00ba32eb9115fe63606b6ccb441ca3b7e3378880
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

index ae9b34acb62b04490b8123095f27462730d2f676..0e669262c5a3d58573dddf0c39e115bdb1b2550e 100755 (executable)
@@ -179,7 +179,7 @@ static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
        }
 }
 
-#define I2C_DIV_FACTOR 100000
+#define I2C_DIV_FACTOR 1000000
 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 {
        unsigned long tmp_scl_period = 0;
@@ -195,16 +195,24 @@ static u16 i2c_count(u16 sfrclock, u16 sclmintime)
        return (u16)(tmp_scl_period);
 }
 
-#define EDID_I2C_MIN_SS_SCL_HIGH_TIME  50000
-#define EDID_I2C_MIN_SS_SCL_LOW_TIME   50000
+#define EDID_I2C_MIN_SS_SCL_HIGH_TIME  9625
+#define EDID_I2C_MIN_SS_SCL_LOW_TIME   10000
 
 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 {
+       int value;
+
        /* Set DDC I2C CLK which devided from DDC_CLK. */
+       value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME);
        hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
-                   i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME));
+                   value & 0xff);
+       hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_1_ADDR,
+                   (value >> 8) & 0xff);
+       value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME);
        hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
-                   i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME));
+                   value & 0xff);
+       hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_1_ADDR,
+                   (value >> 8) & 0xff);
        hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
                     v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 }